| Ryder Lee | 785e5c6 | 2016-12-19 10:20:44 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Support for MediaTek cryptographic accelerator. |
| 3 | * |
| 4 | * Copyright (c) 2016 MediaTek Inc. |
| 5 | * Author: Ryder Lee <ryder.lee@mediatek.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License. |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | #ifndef __MTK_REGS_H__ |
| 14 | #define __MTK_REGS_H__ |
| 15 | |
| 16 | /* HIA, Command Descriptor Ring Manager */ |
| 17 | #define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12)) |
| 18 | #define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12)) |
| 19 | #define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12)) |
| 20 | #define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12)) |
| 21 | #define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12)) |
| 22 | #define CDR_ACD_BASE_ADDR_HI(x) (0x14 + ((x) << 12)) |
| 23 | #define CDR_RING_SIZE(x) (0x18 + ((x) << 12)) |
| 24 | #define CDR_DESC_SIZE(x) (0x1C + ((x) << 12)) |
| 25 | #define CDR_CFG(x) (0x20 + ((x) << 12)) |
| 26 | #define CDR_DMA_CFG(x) (0x24 + ((x) << 12)) |
| 27 | #define CDR_THRESH(x) (0x28 + ((x) << 12)) |
| 28 | #define CDR_PREP_COUNT(x) (0x2C + ((x) << 12)) |
| 29 | #define CDR_PROC_COUNT(x) (0x30 + ((x) << 12)) |
| 30 | #define CDR_PREP_PNTR(x) (0x34 + ((x) << 12)) |
| 31 | #define CDR_PROC_PNTR(x) (0x38 + ((x) << 12)) |
| 32 | #define CDR_STAT(x) (0x3C + ((x) << 12)) |
| 33 | |
| 34 | /* HIA, Result Descriptor Ring Manager */ |
| 35 | #define RDR_BASE_ADDR_LO(x) (0x800 + ((x) << 12)) |
| 36 | #define RDR_BASE_ADDR_HI(x) (0x804 + ((x) << 12)) |
| 37 | #define RDR_DATA_BASE_ADDR_LO(x) (0x808 + ((x) << 12)) |
| 38 | #define RDR_DATA_BASE_ADDR_HI(x) (0x80C + ((x) << 12)) |
| 39 | #define RDR_ACD_BASE_ADDR_LO(x) (0x810 + ((x) << 12)) |
| 40 | #define RDR_ACD_BASE_ADDR_HI(x) (0x814 + ((x) << 12)) |
| 41 | #define RDR_RING_SIZE(x) (0x818 + ((x) << 12)) |
| 42 | #define RDR_DESC_SIZE(x) (0x81C + ((x) << 12)) |
| 43 | #define RDR_CFG(x) (0x820 + ((x) << 12)) |
| 44 | #define RDR_DMA_CFG(x) (0x824 + ((x) << 12)) |
| 45 | #define RDR_THRESH(x) (0x828 + ((x) << 12)) |
| 46 | #define RDR_PREP_COUNT(x) (0x82C + ((x) << 12)) |
| 47 | #define RDR_PROC_COUNT(x) (0x830 + ((x) << 12)) |
| 48 | #define RDR_PREP_PNTR(x) (0x834 + ((x) << 12)) |
| 49 | #define RDR_PROC_PNTR(x) (0x838 + ((x) << 12)) |
| 50 | #define RDR_STAT(x) (0x83C + ((x) << 12)) |
| 51 | |
| 52 | /* HIA, Ring AIC */ |
| 53 | #define AIC_POL_CTRL(x) (0xE000 - ((x) << 12)) |
| 54 | #define AIC_TYPE_CTRL(x) (0xE004 - ((x) << 12)) |
| 55 | #define AIC_ENABLE_CTRL(x) (0xE008 - ((x) << 12)) |
| 56 | #define AIC_RAW_STAL(x) (0xE00C - ((x) << 12)) |
| 57 | #define AIC_ENABLE_SET(x) (0xE00C - ((x) << 12)) |
| 58 | #define AIC_ENABLED_STAT(x) (0xE010 - ((x) << 12)) |
| 59 | #define AIC_ACK(x) (0xE010 - ((x) << 12)) |
| 60 | #define AIC_ENABLE_CLR(x) (0xE014 - ((x) << 12)) |
| 61 | #define AIC_OPTIONS(x) (0xE018 - ((x) << 12)) |
| 62 | #define AIC_VERSION(x) (0xE01C - ((x) << 12)) |
| 63 | |
| 64 | /* HIA, Global AIC */ |
| 65 | #define AIC_G_POL_CTRL 0xF800 |
| 66 | #define AIC_G_TYPE_CTRL 0xF804 |
| 67 | #define AIC_G_ENABLE_CTRL 0xF808 |
| 68 | #define AIC_G_RAW_STAT 0xF80C |
| 69 | #define AIC_G_ENABLE_SET 0xF80C |
| 70 | #define AIC_G_ENABLED_STAT 0xF810 |
| 71 | #define AIC_G_ACK 0xF810 |
| 72 | #define AIC_G_ENABLE_CLR 0xF814 |
| 73 | #define AIC_G_OPTIONS 0xF818 |
| 74 | #define AIC_G_VERSION 0xF81C |
| 75 | |
| 76 | /* HIA, Data Fetch Engine */ |
| 77 | #define DFE_CFG 0xF000 |
| 78 | #define DFE_PRIO_0 0xF010 |
| 79 | #define DFE_PRIO_1 0xF014 |
| 80 | #define DFE_PRIO_2 0xF018 |
| 81 | #define DFE_PRIO_3 0xF01C |
| 82 | |
| 83 | /* HIA, Data Fetch Engine access monitoring for CDR */ |
| 84 | #define DFE_RING_REGION_LO(x) (0xF080 + ((x) << 3)) |
| 85 | #define DFE_RING_REGION_HI(x) (0xF084 + ((x) << 3)) |
| 86 | |
| 87 | /* HIA, Data Fetch Engine thread control and status for thread */ |
| 88 | #define DFE_THR_CTRL 0xF200 |
| 89 | #define DFE_THR_STAT 0xF204 |
| 90 | #define DFE_THR_DESC_CTRL 0xF208 |
| 91 | #define DFE_THR_DESC_DPTR_LO 0xF210 |
| 92 | #define DFE_THR_DESC_DPTR_HI 0xF214 |
| 93 | #define DFE_THR_DESC_ACDPTR_LO 0xF218 |
| 94 | #define DFE_THR_DESC_ACDPTR_HI 0xF21C |
| 95 | |
| 96 | /* HIA, Data Store Engine */ |
| 97 | #define DSE_CFG 0xF400 |
| 98 | #define DSE_PRIO_0 0xF410 |
| 99 | #define DSE_PRIO_1 0xF414 |
| 100 | #define DSE_PRIO_2 0xF418 |
| 101 | #define DSE_PRIO_3 0xF41C |
| 102 | |
| 103 | /* HIA, Data Store Engine access monitoring for RDR */ |
| 104 | #define DSE_RING_REGION_LO(x) (0xF480 + ((x) << 3)) |
| 105 | #define DSE_RING_REGION_HI(x) (0xF484 + ((x) << 3)) |
| 106 | |
| 107 | /* HIA, Data Store Engine thread control and status for thread */ |
| 108 | #define DSE_THR_CTRL 0xF600 |
| 109 | #define DSE_THR_STAT 0xF604 |
| 110 | #define DSE_THR_DESC_CTRL 0xF608 |
| 111 | #define DSE_THR_DESC_DPTR_LO 0xF610 |
| 112 | #define DSE_THR_DESC_DPTR_HI 0xF614 |
| 113 | #define DSE_THR_DESC_S_DPTR_LO 0xF618 |
| 114 | #define DSE_THR_DESC_S_DPTR_HI 0xF61C |
| 115 | #define DSE_THR_ERROR_STAT 0xF620 |
| 116 | |
| 117 | /* HIA Global */ |
| 118 | #define HIA_MST_CTRL 0xFFF4 |
| 119 | #define HIA_OPTIONS 0xFFF8 |
| 120 | #define HIA_VERSION 0xFFFC |
| 121 | |
| 122 | /* Processing Engine Input Side, Processing Engine */ |
| 123 | #define PE_IN_DBUF_THRESH 0x10000 |
| 124 | #define PE_IN_TBUF_THRESH 0x10100 |
| 125 | |
| 126 | /* Packet Engine Configuration / Status Registers */ |
| 127 | #define PE_TOKEN_CTRL_STAT 0x11000 |
| 128 | #define PE_FUNCTION_EN 0x11004 |
| 129 | #define PE_CONTEXT_CTRL 0x11008 |
| 130 | #define PE_INTERRUPT_CTRL_STAT 0x11010 |
| 131 | #define PE_CONTEXT_STAT 0x1100C |
| 132 | #define PE_OUT_TRANS_CTRL_STAT 0x11018 |
| 133 | #define PE_OUT_BUF_CTRL 0x1101C |
| 134 | |
| 135 | /* Packet Engine PRNG Registers */ |
| 136 | #define PE_PRNG_STAT 0x11040 |
| 137 | #define PE_PRNG_CTRL 0x11044 |
| 138 | #define PE_PRNG_SEED_L 0x11048 |
| 139 | #define PE_PRNG_SEED_H 0x1104C |
| 140 | #define PE_PRNG_KEY_0_L 0x11050 |
| 141 | #define PE_PRNG_KEY_0_H 0x11054 |
| 142 | #define PE_PRNG_KEY_1_L 0x11058 |
| 143 | #define PE_PRNG_KEY_1_H 0x1105C |
| 144 | #define PE_PRNG_RES_0 0x11060 |
| 145 | #define PE_PRNG_RES_1 0x11064 |
| 146 | #define PE_PRNG_RES_2 0x11068 |
| 147 | #define PE_PRNG_RES_3 0x1106C |
| 148 | #define PE_PRNG_LFSR_L 0x11070 |
| 149 | #define PE_PRNG_LFSR_H 0x11074 |
| 150 | |
| 151 | /* Packet Engine AIC */ |
| 152 | #define PE_EIP96_AIC_POL_CTRL 0x113C0 |
| 153 | #define PE_EIP96_AIC_TYPE_CTRL 0x113C4 |
| 154 | #define PE_EIP96_AIC_ENABLE_CTRL 0x113C8 |
| 155 | #define PE_EIP96_AIC_RAW_STAT 0x113CC |
| 156 | #define PE_EIP96_AIC_ENABLE_SET 0x113CC |
| 157 | #define PE_EIP96_AIC_ENABLED_STAT 0x113D0 |
| 158 | #define PE_EIP96_AIC_ACK 0x113D0 |
| 159 | #define PE_EIP96_AIC_ENABLE_CLR 0x113D4 |
| 160 | #define PE_EIP96_AIC_OPTIONS 0x113D8 |
| 161 | #define PE_EIP96_AIC_VERSION 0x113DC |
| 162 | |
| 163 | /* Packet Engine Options & Version Registers */ |
| 164 | #define PE_EIP96_OPTIONS 0x113F8 |
| 165 | #define PE_EIP96_VERSION 0x113FC |
| 166 | |
| 167 | /* Processing Engine Output Side */ |
| 168 | #define PE_OUT_DBUF_THRESH 0x11C00 |
| 169 | #define PE_OUT_TBUF_THRESH 0x11D00 |
| 170 | |
| 171 | /* Processing Engine Local AIC */ |
| 172 | #define PE_AIC_POL_CTRL 0x11F00 |
| 173 | #define PE_AIC_TYPE_CTRL 0x11F04 |
| 174 | #define PE_AIC_ENABLE_CTRL 0x11F08 |
| 175 | #define PE_AIC_RAW_STAT 0x11F0C |
| 176 | #define PE_AIC_ENABLE_SET 0x11F0C |
| 177 | #define PE_AIC_ENABLED_STAT 0x11F10 |
| 178 | #define PE_AIC_ENABLE_CLR 0x11F14 |
| 179 | #define PE_AIC_OPTIONS 0x11F18 |
| 180 | #define PE_AIC_VERSION 0x11F1C |
| 181 | |
| 182 | /* Processing Engine General Configuration and Version */ |
| 183 | #define PE_IN_FLIGHT 0x11FF0 |
| 184 | #define PE_OPTIONS 0x11FF8 |
| 185 | #define PE_VERSION 0x11FFC |
| 186 | |
| 187 | /* EIP-97 - Global */ |
| 188 | #define EIP97_CLOCK_STATE 0x1FFE4 |
| 189 | #define EIP97_FORCE_CLOCK_ON 0x1FFE8 |
| 190 | #define EIP97_FORCE_CLOCK_OFF 0x1FFEC |
| 191 | #define EIP97_MST_CTRL 0x1FFF4 |
| 192 | #define EIP97_OPTIONS 0x1FFF8 |
| 193 | #define EIP97_VERSION 0x1FFFC |
| 194 | #endif /* __MTK_REGS_H__ */ |