blob: f9a2c2fc03c4a4e7bd159a509edfcaae5b5ab02c [file] [log] [blame]
John Linn61ec9012011-04-30 00:07:43 -04001/*
2 * Xilinx PS UART driver
3 *
Soren Brinkmanne555a212014-04-04 17:23:39 -07004 * 2011 - 2014 (C) Xilinx Inc.
John Linn61ec9012011-04-30 00:07:43 -04005 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
John Linn61ec9012011-04-30 00:07:43 -040011 */
12
Vlad Lungu0c0c47b2013-10-17 14:08:06 -070013#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
14#define SUPPORT_SYSRQ
15#endif
16
John Linn61ec9012011-04-30 00:07:43 -040017#include <linux/platform_device.h>
John Linn61ec9012011-04-30 00:07:43 -040018#include <linux/serial.h>
Vlad Lungu0c0c47b2013-10-17 14:08:06 -070019#include <linux/console.h>
Jiri Slabyee160a32011-09-01 16:20:57 +020020#include <linux/serial_core.h>
Soren Brinkmann30e1e282013-05-13 10:46:38 -070021#include <linux/slab.h>
Jiri Slabyee160a32011-09-01 16:20:57 +020022#include <linux/tty.h>
23#include <linux/tty_flip.h>
Josh Cartwright2326669c2013-01-21 19:57:41 +010024#include <linux/clk.h>
John Linn61ec9012011-04-30 00:07:43 -040025#include <linux/irq.h>
26#include <linux/io.h>
27#include <linux/of.h>
Paul Gortmaker578b9ce2011-05-27 16:14:23 -040028#include <linux/module.h>
John Linn61ec9012011-04-30 00:07:43 -040029
30#define XUARTPS_TTY_NAME "ttyPS"
31#define XUARTPS_NAME "xuartps"
32#define XUARTPS_MAJOR 0 /* use dynamic node allocation */
33#define XUARTPS_MINOR 0 /* works best with devtmpfs */
34#define XUARTPS_NR_PORTS 2
Suneel85baf542013-10-17 14:08:08 -070035#define XUARTPS_FIFO_SIZE 64 /* FIFO size */
John Linn61ec9012011-04-30 00:07:43 -040036#define XUARTPS_REGISTER_SPACE 0xFFF
37
38#define xuartps_readl(offset) ioread32(port->membase + offset)
39#define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
40
Suneel85baf542013-10-17 14:08:08 -070041/* Rx Trigger level */
42static int rx_trigger_level = 56;
43module_param(rx_trigger_level, uint, S_IRUGO);
44MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
45
46/* Rx Timeout */
47static int rx_timeout = 10;
48module_param(rx_timeout, uint, S_IRUGO);
49MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
50
Soren Brinkmanne555a212014-04-04 17:23:39 -070051/* Register offsets for the UART. */
52#define XUARTPS_CR_OFFSET 0x00 /* Control Register */
53#define XUARTPS_MR_OFFSET 0x04 /* Mode Register */
54#define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable */
55#define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable */
56#define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask */
57#define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status */
58#define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */
59#define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout */
60#define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */
61#define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control */
62#define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status */
63#define XUARTPS_SR_OFFSET 0x2C /* Channel Status */
64#define XUARTPS_FIFO_OFFSET 0x30 /* FIFO */
65#define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */
66#define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay */
67#define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse Width */
68#define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */
69#define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */
John Linn61ec9012011-04-30 00:07:43 -040070
Soren Brinkmanne555a212014-04-04 17:23:39 -070071/* Control Register Bit Definitions */
John Linn61ec9012011-04-30 00:07:43 -040072#define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
73#define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
74#define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
75#define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
76#define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
77#define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
78#define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
79#define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
80#define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
81
Soren Brinkmanne555a212014-04-04 17:23:39 -070082/*
83 * Mode Register:
John Linn61ec9012011-04-30 00:07:43 -040084 * The mode register (MR) defines the mode of transfer as well as the data
85 * format. If this register is modified during transmission or reception,
86 * data validity cannot be guaranteed.
John Linn61ec9012011-04-30 00:07:43 -040087 */
88#define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
89#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
90#define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
91
92#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
93#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
94
95#define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
96#define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
97#define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
98#define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
99#define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
100
101#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
102#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
103#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
104
Soren Brinkmanne555a212014-04-04 17:23:39 -0700105/*
106 * Interrupt Registers:
John Linn61ec9012011-04-30 00:07:43 -0400107 * Interrupt control logic uses the interrupt enable register (IER) and the
108 * interrupt disable register (IDR) to set the value of the bits in the
109 * interrupt mask register (IMR). The IMR determines whether to pass an
110 * interrupt to the interrupt status register (ISR).
111 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
112 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
113 * Reading either IER or IDR returns 0x00.
John Linn61ec9012011-04-30 00:07:43 -0400114 * All four registers have the same bit definitions.
115 */
116#define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
117#define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
118#define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
119#define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
120#define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
121#define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
122#define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
123#define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
124#define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
125#define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
126#define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
127
Vlad Lungu0c0c47b2013-10-17 14:08:06 -0700128/* Goes in read_status_mask for break detection as the HW doesn't do it*/
129#define XUARTPS_IXR_BRK 0x80000000
130
Soren Brinkmanne555a212014-04-04 17:23:39 -0700131/*
132 * Channel Status Register:
John Linn61ec9012011-04-30 00:07:43 -0400133 * The channel status register (CSR) is provided to enable the control logic
134 * to monitor the status of bits in the channel interrupt status register,
135 * even if these are masked out by the interrupt mask register.
136 */
137#define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
138#define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
139#define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
140#define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
141
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700142/* baud dividers min/max values */
143#define XUARTPS_BDIV_MIN 4
144#define XUARTPS_BDIV_MAX 255
145#define XUARTPS_CD_MAX 65535
146
John Linn61ec9012011-04-30 00:07:43 -0400147/**
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700148 * struct xuartps - device data
Michal Simek489810a12014-04-04 17:23:37 -0700149 * @port: Pointer to the UART port
150 * @refclk: Reference clock
151 * @aperclk: APB clock
152 * @baud: Current baud rate
153 * @clk_rate_change_nb: Notifier block for clock changes
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700154 */
155struct xuartps {
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700156 struct uart_port *port;
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700157 struct clk *refclk;
158 struct clk *aperclk;
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700159 unsigned int baud;
160 struct notifier_block clk_rate_change_nb;
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700161};
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700162#define to_xuartps(_nb) container_of(_nb, struct xuartps, clk_rate_change_nb);
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700163
164/**
John Linn61ec9012011-04-30 00:07:43 -0400165 * xuartps_isr - Interrupt handler
166 * @irq: Irq number
167 * @dev_id: Id of the port
168 *
Michal Simek489810a12014-04-04 17:23:37 -0700169 * Return: IRQHANDLED
170 */
John Linn61ec9012011-04-30 00:07:43 -0400171static irqreturn_t xuartps_isr(int irq, void *dev_id)
172{
173 struct uart_port *port = (struct uart_port *)dev_id;
John Linn61ec9012011-04-30 00:07:43 -0400174 unsigned long flags;
175 unsigned int isrstatus, numbytes;
176 unsigned int data;
177 char status = TTY_NORMAL;
178
John Linn61ec9012011-04-30 00:07:43 -0400179 spin_lock_irqsave(&port->lock, flags);
180
181 /* Read the interrupt status register to determine which
182 * interrupt(s) is/are active.
183 */
184 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
185
Vlad Lungu0c0c47b2013-10-17 14:08:06 -0700186 /*
187 * There is no hardware break detection, so we interpret framing
188 * error with all-zeros data as a break sequence. Most of the time,
189 * there's another non-zero byte at the end of the sequence.
190 */
Vlad Lungu0c0c47b2013-10-17 14:08:06 -0700191 if (isrstatus & XUARTPS_IXR_FRAMING) {
192 while (!(xuartps_readl(XUARTPS_SR_OFFSET) &
193 XUARTPS_SR_RXEMPTY)) {
194 if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) {
195 port->read_status_mask |= XUARTPS_IXR_BRK;
196 isrstatus &= ~XUARTPS_IXR_FRAMING;
197 }
198 }
199 xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET);
200 }
201
John Linn61ec9012011-04-30 00:07:43 -0400202 /* drop byte with parity error if IGNPAR specified */
203 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
204 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
205
206 isrstatus &= port->read_status_mask;
207 isrstatus &= ~port->ignore_status_mask;
208
209 if ((isrstatus & XUARTPS_IXR_TOUT) ||
210 (isrstatus & XUARTPS_IXR_RXTRIG)) {
211 /* Receive Timeout Interrupt */
212 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
213 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
214 data = xuartps_readl(XUARTPS_FIFO_OFFSET);
Vlad Lungu0c0c47b2013-10-17 14:08:06 -0700215
216 /* Non-NULL byte after BREAK is garbage (99%) */
217 if (data && (port->read_status_mask &
218 XUARTPS_IXR_BRK)) {
219 port->read_status_mask &= ~XUARTPS_IXR_BRK;
220 port->icount.brk++;
221 if (uart_handle_break(port))
222 continue;
223 }
224
Soren Brinkmannc2db11e2013-12-02 11:38:38 -0800225#ifdef SUPPORT_SYSRQ
Vlad Lungu0c0c47b2013-10-17 14:08:06 -0700226 /*
227 * uart_handle_sysrq_char() doesn't work if
228 * spinlocked, for some reason
229 */
230 if (port->sysrq) {
231 spin_unlock(&port->lock);
232 if (uart_handle_sysrq_char(port,
233 (unsigned char)data)) {
234 spin_lock(&port->lock);
235 continue;
236 }
237 spin_lock(&port->lock);
238 }
Soren Brinkmannc2db11e2013-12-02 11:38:38 -0800239#endif
Vlad Lungu0c0c47b2013-10-17 14:08:06 -0700240
John Linn61ec9012011-04-30 00:07:43 -0400241 port->icount.rx++;
242
243 if (isrstatus & XUARTPS_IXR_PARITY) {
244 port->icount.parity++;
245 status = TTY_PARITY;
246 } else if (isrstatus & XUARTPS_IXR_FRAMING) {
247 port->icount.frame++;
248 status = TTY_FRAME;
Soren Brinkmanne555a212014-04-04 17:23:39 -0700249 } else if (isrstatus & XUARTPS_IXR_OVERRUN) {
John Linn61ec9012011-04-30 00:07:43 -0400250 port->icount.overrun++;
Soren Brinkmanne555a212014-04-04 17:23:39 -0700251 }
John Linn61ec9012011-04-30 00:07:43 -0400252
Jiri Slaby2e124b42013-01-03 15:53:06 +0100253 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN,
254 data, status);
John Linn61ec9012011-04-30 00:07:43 -0400255 }
256 spin_unlock(&port->lock);
Jiri Slaby2e124b42013-01-03 15:53:06 +0100257 tty_flip_buffer_push(&port->state->port);
John Linn61ec9012011-04-30 00:07:43 -0400258 spin_lock(&port->lock);
259 }
260
261 /* Dispatch an appropriate handler */
262 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
263 if (uart_circ_empty(&port->state->xmit)) {
264 xuartps_writel(XUARTPS_IXR_TXEMPTY,
265 XUARTPS_IDR_OFFSET);
266 } else {
267 numbytes = port->fifosize;
268 /* Break if no more data available in the UART buffer */
269 while (numbytes--) {
270 if (uart_circ_empty(&port->state->xmit))
271 break;
272 /* Get the data from the UART circular buffer
273 * and write it to the xuartps's TX_FIFO
274 * register.
275 */
276 xuartps_writel(
277 port->state->xmit.buf[port->state->xmit.
278 tail], XUARTPS_FIFO_OFFSET);
279
280 port->icount.tx++;
281
282 /* Adjust the tail of the UART buffer and wrap
283 * the buffer if it reaches limit.
284 */
285 port->state->xmit.tail =
Soren Brinkmanne555a212014-04-04 17:23:39 -0700286 (port->state->xmit.tail + 1) &
John Linn61ec9012011-04-30 00:07:43 -0400287 (UART_XMIT_SIZE - 1);
288 }
289
290 if (uart_circ_chars_pending(
291 &port->state->xmit) < WAKEUP_CHARS)
292 uart_write_wakeup(port);
293 }
294 }
295
296 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
297
298 /* be sure to release the lock and tty before leaving */
299 spin_unlock_irqrestore(&port->lock, flags);
John Linn61ec9012011-04-30 00:07:43 -0400300
301 return IRQ_HANDLED;
302}
303
304/**
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700305 * xuartps_calc_baud_divs - Calculate baud rate divisors
306 * @clk: UART module input clock
307 * @baud: Desired baud rate
308 * @rbdiv: BDIV value (return value)
309 * @rcd: CD value (return value)
310 * @div8: Value for clk_sel bit in mod (return value)
Michal Simek489810a12014-04-04 17:23:37 -0700311 * Return: baud rate, requested baud when possible, or actual baud when there
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700312 * was too much error, zero if no valid divisors are found.
313 *
314 * Formula to obtain baud rate is
315 * baud_tx/rx rate = clk/CD * (BDIV + 1)
316 * input_clk = (Uart User Defined Clock or Apb Clock)
317 * depends on UCLKEN in MR Reg
318 * clk = input_clk or input_clk/8;
319 * depends on CLKS in MR reg
320 * CD and BDIV depends on values in
321 * baud rate generate register
322 * baud rate clock divisor register
323 */
324static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
325 u32 *rbdiv, u32 *rcd, int *div8)
John Linn61ec9012011-04-30 00:07:43 -0400326{
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700327 u32 cd, bdiv;
328 unsigned int calc_baud;
329 unsigned int bestbaud = 0;
John Linn61ec9012011-04-30 00:07:43 -0400330 unsigned int bauderror;
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700331 unsigned int besterror = ~0;
John Linn61ec9012011-04-30 00:07:43 -0400332
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700333 if (baud < clk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX)) {
334 *div8 = 1;
335 clk /= 8;
336 } else {
337 *div8 = 0;
338 }
John Linn61ec9012011-04-30 00:07:43 -0400339
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700340 for (bdiv = XUARTPS_BDIV_MIN; bdiv <= XUARTPS_BDIV_MAX; bdiv++) {
341 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
342 if (cd < 1 || cd > XUARTPS_CD_MAX)
John Linn61ec9012011-04-30 00:07:43 -0400343 continue;
344
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700345 calc_baud = clk / (cd * (bdiv + 1));
John Linn61ec9012011-04-30 00:07:43 -0400346
347 if (baud > calc_baud)
348 bauderror = baud - calc_baud;
349 else
350 bauderror = calc_baud - baud;
351
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700352 if (besterror > bauderror) {
353 *rbdiv = bdiv;
354 *rcd = cd;
355 bestbaud = calc_baud;
356 besterror = bauderror;
John Linn61ec9012011-04-30 00:07:43 -0400357 }
358 }
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700359 /* use the values when percent error is acceptable */
360 if (((besterror * 100) / baud) < 3)
361 bestbaud = baud;
John Linn61ec9012011-04-30 00:07:43 -0400362
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700363 return bestbaud;
364}
365
366/**
367 * xuartps_set_baud_rate - Calculate and set the baud rate
368 * @port: Handle to the uart port structure
369 * @baud: Baud rate to set
Michal Simek489810a12014-04-04 17:23:37 -0700370 * Return: baud rate, requested baud when possible, or actual baud when there
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700371 * was too much error, zero if no valid divisors are found.
372 */
373static unsigned int xuartps_set_baud_rate(struct uart_port *port,
374 unsigned int baud)
375{
376 unsigned int calc_baud;
Soren Brinkmannd54b1812013-10-21 16:40:59 -0700377 u32 cd = 0, bdiv = 0;
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700378 u32 mreg;
379 int div8;
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700380 struct xuartps *xuartps = port->private_data;
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700381
382 calc_baud = xuartps_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
383 &div8);
384
385 /* Write new divisors to hardware */
386 mreg = xuartps_readl(XUARTPS_MR_OFFSET);
387 if (div8)
388 mreg |= XUARTPS_MR_CLKSEL;
389 else
390 mreg &= ~XUARTPS_MR_CLKSEL;
391 xuartps_writel(mreg, XUARTPS_MR_OFFSET);
392 xuartps_writel(cd, XUARTPS_BAUDGEN_OFFSET);
393 xuartps_writel(bdiv, XUARTPS_BAUDDIV_OFFSET);
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700394 xuartps->baud = baud;
John Linn61ec9012011-04-30 00:07:43 -0400395
396 return calc_baud;
397}
398
Soren Brinkmann7ac57342013-10-21 16:41:01 -0700399#ifdef CONFIG_COMMON_CLK
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700400/**
401 * xuartps_clk_notitifer_cb - Clock notifier callback
402 * @nb: Notifier block
403 * @event: Notify event
404 * @data: Notifier data
Soren Brinkmanne555a212014-04-04 17:23:39 -0700405 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700406 */
407static int xuartps_clk_notifier_cb(struct notifier_block *nb,
408 unsigned long event, void *data)
409{
410 u32 ctrl_reg;
411 struct uart_port *port;
412 int locked = 0;
413 struct clk_notifier_data *ndata = data;
414 unsigned long flags = 0;
415 struct xuartps *xuartps = to_xuartps(nb);
416
417 port = xuartps->port;
418 if (port->suspended)
419 return NOTIFY_OK;
420
421 switch (event) {
422 case PRE_RATE_CHANGE:
423 {
Soren Brinkmanne555a212014-04-04 17:23:39 -0700424 u32 bdiv, cd;
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700425 int div8;
426
427 /*
428 * Find out if current baud-rate can be achieved with new clock
429 * frequency.
430 */
431 if (!xuartps_calc_baud_divs(ndata->new_rate, xuartps->baud,
Soren Brinkmann5ce15d22014-04-04 17:23:40 -0700432 &bdiv, &cd, &div8)) {
433 dev_warn(port->dev, "clock rate change rejected\n");
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700434 return NOTIFY_BAD;
Soren Brinkmann5ce15d22014-04-04 17:23:40 -0700435 }
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700436
437 spin_lock_irqsave(&xuartps->port->lock, flags);
438
439 /* Disable the TX and RX to set baud rate */
Soren Brinkmann35dc5a52014-04-04 17:23:41 -0700440 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
441 ctrl_reg |= XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS;
442 xuartps_writel(ctrl_reg, XUARTPS_CR_OFFSET);
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700443
444 spin_unlock_irqrestore(&xuartps->port->lock, flags);
445
446 return NOTIFY_OK;
447 }
448 case POST_RATE_CHANGE:
449 /*
450 * Set clk dividers to generate correct baud with new clock
451 * frequency.
452 */
453
454 spin_lock_irqsave(&xuartps->port->lock, flags);
455
456 locked = 1;
457 port->uartclk = ndata->new_rate;
458
459 xuartps->baud = xuartps_set_baud_rate(xuartps->port,
460 xuartps->baud);
461 /* fall through */
462 case ABORT_RATE_CHANGE:
463 if (!locked)
464 spin_lock_irqsave(&xuartps->port->lock, flags);
465
466 /* Set TX/RX Reset */
Soren Brinkmann35dc5a52014-04-04 17:23:41 -0700467 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
468 ctrl_reg |= XUARTPS_CR_TXRST | XUARTPS_CR_RXRST;
469 xuartps_writel(ctrl_reg, XUARTPS_CR_OFFSET);
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700470
471 while (xuartps_readl(XUARTPS_CR_OFFSET) &
472 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST))
473 cpu_relax();
474
475 /*
476 * Clear the RX disable and TX disable bits and then set the TX
477 * enable bit and RX enable bit to enable the transmitter and
478 * receiver.
479 */
480 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
481 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
Soren Brinkmann35dc5a52014-04-04 17:23:41 -0700482 ctrl_reg &= ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS);
483 ctrl_reg |= XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN;
484 xuartps_writel(ctrl_reg, XUARTPS_CR_OFFSET);
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700485
486 spin_unlock_irqrestore(&xuartps->port->lock, flags);
487
488 return NOTIFY_OK;
489 default:
490 return NOTIFY_DONE;
491 }
492}
Soren Brinkmann7ac57342013-10-21 16:41:01 -0700493#endif
Soren Brinkmannc4b05102013-10-17 14:08:11 -0700494
John Linn61ec9012011-04-30 00:07:43 -0400495/**
496 * xuartps_start_tx - Start transmitting bytes
497 * @port: Handle to the uart port structure
Michal Simek489810a12014-04-04 17:23:37 -0700498 */
John Linn61ec9012011-04-30 00:07:43 -0400499static void xuartps_start_tx(struct uart_port *port)
500{
501 unsigned int status, numbytes = port->fifosize;
502
503 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
504 return;
505
506 status = xuartps_readl(XUARTPS_CR_OFFSET);
507 /* Set the TX enable bit and clear the TX disable bit to enable the
508 * transmitter.
509 */
510 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
511 XUARTPS_CR_OFFSET);
512
Soren Brinkmanne555a212014-04-04 17:23:39 -0700513 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET) &
514 XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
John Linn61ec9012011-04-30 00:07:43 -0400515 /* Break if no more data available in the UART buffer */
516 if (uart_circ_empty(&port->state->xmit))
517 break;
518
519 /* Get the data from the UART circular buffer and
520 * write it to the xuartps's TX_FIFO register.
521 */
522 xuartps_writel(
523 port->state->xmit.buf[port->state->xmit.tail],
524 XUARTPS_FIFO_OFFSET);
525 port->icount.tx++;
526
527 /* Adjust the tail of the UART buffer and wrap
528 * the buffer if it reaches limit.
529 */
530 port->state->xmit.tail = (port->state->xmit.tail + 1) &
531 (UART_XMIT_SIZE - 1);
532 }
Suneel85baf542013-10-17 14:08:08 -0700533 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_ISR_OFFSET);
John Linn61ec9012011-04-30 00:07:43 -0400534 /* Enable the TX Empty interrupt */
535 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
536
537 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
538 uart_write_wakeup(port);
539}
540
541/**
542 * xuartps_stop_tx - Stop TX
543 * @port: Handle to the uart port structure
Michal Simek489810a12014-04-04 17:23:37 -0700544 */
John Linn61ec9012011-04-30 00:07:43 -0400545static void xuartps_stop_tx(struct uart_port *port)
546{
547 unsigned int regval;
548
549 regval = xuartps_readl(XUARTPS_CR_OFFSET);
550 regval |= XUARTPS_CR_TX_DIS;
551 /* Disable the transmitter */
552 xuartps_writel(regval, XUARTPS_CR_OFFSET);
553}
554
555/**
556 * xuartps_stop_rx - Stop RX
557 * @port: Handle to the uart port structure
Michal Simek489810a12014-04-04 17:23:37 -0700558 */
John Linn61ec9012011-04-30 00:07:43 -0400559static void xuartps_stop_rx(struct uart_port *port)
560{
561 unsigned int regval;
562
563 regval = xuartps_readl(XUARTPS_CR_OFFSET);
564 regval |= XUARTPS_CR_RX_DIS;
565 /* Disable the receiver */
566 xuartps_writel(regval, XUARTPS_CR_OFFSET);
567}
568
569/**
570 * xuartps_tx_empty - Check whether TX is empty
571 * @port: Handle to the uart port structure
572 *
Michal Simek489810a12014-04-04 17:23:37 -0700573 * Return: TIOCSER_TEMT on success, 0 otherwise
574 */
John Linn61ec9012011-04-30 00:07:43 -0400575static unsigned int xuartps_tx_empty(struct uart_port *port)
576{
577 unsigned int status;
578
579 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
580 return status ? TIOCSER_TEMT : 0;
581}
582
583/**
584 * xuartps_break_ctl - Based on the input ctl we have to start or stop
585 * transmitting char breaks
586 * @port: Handle to the uart port structure
587 * @ctl: Value based on which start or stop decision is taken
Michal Simek489810a12014-04-04 17:23:37 -0700588 */
John Linn61ec9012011-04-30 00:07:43 -0400589static void xuartps_break_ctl(struct uart_port *port, int ctl)
590{
591 unsigned int status;
592 unsigned long flags;
593
594 spin_lock_irqsave(&port->lock, flags);
595
596 status = xuartps_readl(XUARTPS_CR_OFFSET);
597
598 if (ctl == -1)
599 xuartps_writel(XUARTPS_CR_STARTBRK | status,
600 XUARTPS_CR_OFFSET);
601 else {
602 if ((status & XUARTPS_CR_STOPBRK) == 0)
603 xuartps_writel(XUARTPS_CR_STOPBRK | status,
604 XUARTPS_CR_OFFSET);
605 }
606 spin_unlock_irqrestore(&port->lock, flags);
607}
608
609/**
610 * xuartps_set_termios - termios operations, handling data length, parity,
611 * stop bits, flow control, baud rate
612 * @port: Handle to the uart port structure
613 * @termios: Handle to the input termios structure
614 * @old: Values of the previously saved termios structure
Michal Simek489810a12014-04-04 17:23:37 -0700615 */
John Linn61ec9012011-04-30 00:07:43 -0400616static void xuartps_set_termios(struct uart_port *port,
617 struct ktermios *termios, struct ktermios *old)
618{
619 unsigned int cval = 0;
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700620 unsigned int baud, minbaud, maxbaud;
John Linn61ec9012011-04-30 00:07:43 -0400621 unsigned long flags;
622 unsigned int ctrl_reg, mode_reg;
623
624 spin_lock_irqsave(&port->lock, flags);
625
626 /* Empty the receive FIFO 1st before making changes */
627 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
628 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
629 xuartps_readl(XUARTPS_FIFO_OFFSET);
630 }
631
632 /* Disable the TX and RX to set baud rate */
Soren Brinkmann35dc5a52014-04-04 17:23:41 -0700633 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
634 ctrl_reg |= XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS;
635 xuartps_writel(ctrl_reg, XUARTPS_CR_OFFSET);
John Linn61ec9012011-04-30 00:07:43 -0400636
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700637 /*
638 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
639 * min and max baud should be calculated here based on port->uartclk.
640 * this way we get a valid baud and can safely call set_baud()
641 */
642 minbaud = port->uartclk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX * 8);
643 maxbaud = port->uartclk / (XUARTPS_BDIV_MIN + 1);
644 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
John Linn61ec9012011-04-30 00:07:43 -0400645 baud = xuartps_set_baud_rate(port, baud);
646 if (tty_termios_baud_rate(termios))
647 tty_termios_encode_baud_rate(termios, baud, baud);
648
Soren Brinkmanne555a212014-04-04 17:23:39 -0700649 /* Update the per-port timeout. */
John Linn61ec9012011-04-30 00:07:43 -0400650 uart_update_timeout(port, termios->c_cflag, baud);
651
652 /* Set TX/RX Reset */
John Linn61ec9012011-04-30 00:07:43 -0400653 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
Soren Brinkmann35dc5a52014-04-04 17:23:41 -0700654 ctrl_reg |= XUARTPS_CR_TXRST | XUARTPS_CR_RXRST;
655 xuartps_writel(ctrl_reg, XUARTPS_CR_OFFSET);
John Linn61ec9012011-04-30 00:07:43 -0400656
Soren Brinkmanne555a212014-04-04 17:23:39 -0700657 /*
658 * Clear the RX disable and TX disable bits and then set the TX enable
John Linn61ec9012011-04-30 00:07:43 -0400659 * bit and RX enable bit to enable the transmitter and receiver.
660 */
Soren Brinkmann35dc5a52014-04-04 17:23:41 -0700661 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
662 ctrl_reg &= ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS);
663 ctrl_reg |= XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN;
664 xuartps_writel(ctrl_reg, XUARTPS_CR_OFFSET);
John Linn61ec9012011-04-30 00:07:43 -0400665
Suneel85baf542013-10-17 14:08:08 -0700666 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
John Linn61ec9012011-04-30 00:07:43 -0400667
668 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
669 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
670 port->ignore_status_mask = 0;
671
672 if (termios->c_iflag & INPCK)
673 port->read_status_mask |= XUARTPS_IXR_PARITY |
674 XUARTPS_IXR_FRAMING;
675
676 if (termios->c_iflag & IGNPAR)
677 port->ignore_status_mask |= XUARTPS_IXR_PARITY |
678 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
679
680 /* ignore all characters if CREAD is not set */
681 if ((termios->c_cflag & CREAD) == 0)
682 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
683 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
684 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
685
686 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
687
688 /* Handling Data Size */
689 switch (termios->c_cflag & CSIZE) {
690 case CS6:
691 cval |= XUARTPS_MR_CHARLEN_6_BIT;
692 break;
693 case CS7:
694 cval |= XUARTPS_MR_CHARLEN_7_BIT;
695 break;
696 default:
697 case CS8:
698 cval |= XUARTPS_MR_CHARLEN_8_BIT;
699 termios->c_cflag &= ~CSIZE;
700 termios->c_cflag |= CS8;
701 break;
702 }
703
704 /* Handling Parity and Stop Bits length */
705 if (termios->c_cflag & CSTOPB)
706 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */
707 else
708 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */
709
710 if (termios->c_cflag & PARENB) {
711 /* Mark or Space parity */
712 if (termios->c_cflag & CMSPAR) {
713 if (termios->c_cflag & PARODD)
714 cval |= XUARTPS_MR_PARITY_MARK;
715 else
716 cval |= XUARTPS_MR_PARITY_SPACE;
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700717 } else {
718 if (termios->c_cflag & PARODD)
John Linn61ec9012011-04-30 00:07:43 -0400719 cval |= XUARTPS_MR_PARITY_ODD;
720 else
721 cval |= XUARTPS_MR_PARITY_EVEN;
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700722 }
723 } else {
John Linn61ec9012011-04-30 00:07:43 -0400724 cval |= XUARTPS_MR_PARITY_NONE;
Soren Brinkmanne6b39bf2013-10-17 14:08:10 -0700725 }
726 cval |= mode_reg & 1;
727 xuartps_writel(cval, XUARTPS_MR_OFFSET);
John Linn61ec9012011-04-30 00:07:43 -0400728
729 spin_unlock_irqrestore(&port->lock, flags);
730}
731
732/**
733 * xuartps_startup - Called when an application opens a xuartps port
734 * @port: Handle to the uart port structure
735 *
Soren Brinkmanne555a212014-04-04 17:23:39 -0700736 * Return: 0 on success, negative errno otherwise
Michal Simek489810a12014-04-04 17:23:37 -0700737 */
John Linn61ec9012011-04-30 00:07:43 -0400738static int xuartps_startup(struct uart_port *port)
739{
740 unsigned int retval = 0, status = 0;
741
742 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
743 (void *)port);
744 if (retval)
745 return retval;
746
747 /* Disable the TX and RX */
748 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
749 XUARTPS_CR_OFFSET);
750
751 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
752 * no break chars.
753 */
754 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
755 XUARTPS_CR_OFFSET);
756
757 status = xuartps_readl(XUARTPS_CR_OFFSET);
758
759 /* Clear the RX disable and TX disable bits and then set the TX enable
760 * bit and RX enable bit to enable the transmitter and receiver.
761 */
762 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
763 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
764 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
765
766 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
767 * no parity.
768 */
769 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
770 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
771 XUARTPS_MR_OFFSET);
772
Suneel85baf542013-10-17 14:08:08 -0700773 /*
774 * Set the RX FIFO Trigger level to use most of the FIFO, but it
775 * can be tuned with a module parameter
776 */
777 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
John Linn61ec9012011-04-30 00:07:43 -0400778
Suneel85baf542013-10-17 14:08:08 -0700779 /*
780 * Receive Timeout register is enabled but it
781 * can be tuned with a module parameter
782 */
783 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
John Linn61ec9012011-04-30 00:07:43 -0400784
John Linn855f6fd2013-03-22 18:49:27 +0100785 /* Clear out any pending interrupts before enabling them */
786 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET);
John Linn61ec9012011-04-30 00:07:43 -0400787
788 /* Set the Interrupt Registers with desired interrupts */
789 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
790 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
791 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
John Linn61ec9012011-04-30 00:07:43 -0400792
793 return retval;
794}
795
796/**
797 * xuartps_shutdown - Called when an application closes a xuartps port
798 * @port: Handle to the uart port structure
Michal Simek489810a12014-04-04 17:23:37 -0700799 */
John Linn61ec9012011-04-30 00:07:43 -0400800static void xuartps_shutdown(struct uart_port *port)
801{
802 int status;
803
804 /* Disable interrupts */
805 status = xuartps_readl(XUARTPS_IMR_OFFSET);
806 xuartps_writel(status, XUARTPS_IDR_OFFSET);
807
808 /* Disable the TX and RX */
809 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
810 XUARTPS_CR_OFFSET);
811 free_irq(port->irq, port);
812}
813
814/**
815 * xuartps_type - Set UART type to xuartps port
816 * @port: Handle to the uart port structure
817 *
Michal Simek489810a12014-04-04 17:23:37 -0700818 * Return: string on success, NULL otherwise
819 */
John Linn61ec9012011-04-30 00:07:43 -0400820static const char *xuartps_type(struct uart_port *port)
821{
822 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
823}
824
825/**
826 * xuartps_verify_port - Verify the port params
827 * @port: Handle to the uart port structure
828 * @ser: Handle to the structure whose members are compared
829 *
Soren Brinkmanne555a212014-04-04 17:23:39 -0700830 * Return: 0 on success, negative errno otherwise.
Michal Simek489810a12014-04-04 17:23:37 -0700831 */
John Linn61ec9012011-04-30 00:07:43 -0400832static int xuartps_verify_port(struct uart_port *port,
833 struct serial_struct *ser)
834{
835 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
836 return -EINVAL;
837 if (port->irq != ser->irq)
838 return -EINVAL;
839 if (ser->io_type != UPIO_MEM)
840 return -EINVAL;
841 if (port->iobase != ser->port)
842 return -EINVAL;
843 if (ser->hub6 != 0)
844 return -EINVAL;
845 return 0;
846}
847
848/**
849 * xuartps_request_port - Claim the memory region attached to xuartps port,
850 * called when the driver adds a xuartps port via
851 * uart_add_one_port()
852 * @port: Handle to the uart port structure
853 *
Soren Brinkmanne555a212014-04-04 17:23:39 -0700854 * Return: 0 on success, negative errno otherwise.
Michal Simek489810a12014-04-04 17:23:37 -0700855 */
John Linn61ec9012011-04-30 00:07:43 -0400856static int xuartps_request_port(struct uart_port *port)
857{
858 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
859 XUARTPS_NAME)) {
860 return -ENOMEM;
861 }
862
863 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
864 if (!port->membase) {
865 dev_err(port->dev, "Unable to map registers\n");
866 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
867 return -ENOMEM;
868 }
869 return 0;
870}
871
872/**
Soren Brinkmanne555a212014-04-04 17:23:39 -0700873 * xuartps_release_port - Release UART port
John Linn61ec9012011-04-30 00:07:43 -0400874 * @port: Handle to the uart port structure
Soren Brinkmanne555a212014-04-04 17:23:39 -0700875 *
876 * Release the memory region attached to a xuartps port. Called when the
877 * driver removes a xuartps port via uart_remove_one_port().
Michal Simek489810a12014-04-04 17:23:37 -0700878 */
John Linn61ec9012011-04-30 00:07:43 -0400879static void xuartps_release_port(struct uart_port *port)
880{
881 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
882 iounmap(port->membase);
883 port->membase = NULL;
884}
885
886/**
Soren Brinkmanne555a212014-04-04 17:23:39 -0700887 * xuartps_config_port - Configure UART port
John Linn61ec9012011-04-30 00:07:43 -0400888 * @port: Handle to the uart port structure
889 * @flags: If any
Michal Simek489810a12014-04-04 17:23:37 -0700890 */
John Linn61ec9012011-04-30 00:07:43 -0400891static void xuartps_config_port(struct uart_port *port, int flags)
892{
893 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
894 port->type = PORT_XUARTPS;
895}
896
897/**
898 * xuartps_get_mctrl - Get the modem control state
John Linn61ec9012011-04-30 00:07:43 -0400899 * @port: Handle to the uart port structure
900 *
Michal Simek489810a12014-04-04 17:23:37 -0700901 * Return: the modem control state
902 */
John Linn61ec9012011-04-30 00:07:43 -0400903static unsigned int xuartps_get_mctrl(struct uart_port *port)
904{
905 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
906}
907
908static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
909{
910 /* N/A */
911}
912
913static void xuartps_enable_ms(struct uart_port *port)
914{
915 /* N/A */
916}
917
Vlad Lungu6ee04c62013-10-17 14:08:07 -0700918#ifdef CONFIG_CONSOLE_POLL
919static int xuartps_poll_get_char(struct uart_port *port)
920{
921 u32 imr;
922 int c;
923
924 /* Disable all interrupts */
925 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
926 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
927
928 /* Check if FIFO is empty */
929 if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY)
930 c = NO_POLL_CHAR;
931 else /* Read a character */
932 c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET);
933
934 /* Enable interrupts */
935 xuartps_writel(imr, XUARTPS_IER_OFFSET);
936
937 return c;
938}
939
940static void xuartps_poll_put_char(struct uart_port *port, unsigned char c)
941{
942 u32 imr;
943
944 /* Disable all interrupts */
945 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
946 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
947
948 /* Wait until FIFO is empty */
949 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
950 cpu_relax();
951
952 /* Write a character */
953 xuartps_writel(c, XUARTPS_FIFO_OFFSET);
954
955 /* Wait until FIFO is empty */
956 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
957 cpu_relax();
958
959 /* Enable interrupts */
960 xuartps_writel(imr, XUARTPS_IER_OFFSET);
961
962 return;
963}
964#endif
965
John Linn61ec9012011-04-30 00:07:43 -0400966static struct uart_ops xuartps_ops = {
967 .set_mctrl = xuartps_set_mctrl,
968 .get_mctrl = xuartps_get_mctrl,
969 .enable_ms = xuartps_enable_ms,
Soren Brinkmanne555a212014-04-04 17:23:39 -0700970 .start_tx = xuartps_start_tx,
971 .stop_tx = xuartps_stop_tx,
972 .stop_rx = xuartps_stop_rx,
973 .tx_empty = xuartps_tx_empty,
974 .break_ctl = xuartps_break_ctl,
975 .set_termios = xuartps_set_termios,
976 .startup = xuartps_startup,
977 .shutdown = xuartps_shutdown,
978 .type = xuartps_type,
979 .verify_port = xuartps_verify_port,
980 .request_port = xuartps_request_port,
981 .release_port = xuartps_release_port,
982 .config_port = xuartps_config_port,
Vlad Lungu6ee04c62013-10-17 14:08:07 -0700983#ifdef CONFIG_CONSOLE_POLL
984 .poll_get_char = xuartps_poll_get_char,
985 .poll_put_char = xuartps_poll_put_char,
986#endif
John Linn61ec9012011-04-30 00:07:43 -0400987};
988
989static struct uart_port xuartps_port[2];
990
991/**
Soren Brinkmanne555a212014-04-04 17:23:39 -0700992 * xuartps_get_port - Configure the port from the platform device resource info
Michal Simek928e9262014-04-04 17:23:38 -0700993 * @id: Port id
994 *
Michal Simek489810a12014-04-04 17:23:37 -0700995 * Return: a pointer to a uart_port or NULL for failure
996 */
Michal Simek928e9262014-04-04 17:23:38 -0700997static struct uart_port *xuartps_get_port(int id)
John Linn61ec9012011-04-30 00:07:43 -0400998{
999 struct uart_port *port;
John Linn61ec9012011-04-30 00:07:43 -04001000
Michal Simek928e9262014-04-04 17:23:38 -07001001 /* Try the given port id if failed use default method */
1002 if (xuartps_port[id].mapbase != 0) {
1003 /* Find the next unused port */
1004 for (id = 0; id < XUARTPS_NR_PORTS; id++)
1005 if (xuartps_port[id].mapbase == 0)
1006 break;
1007 }
John Linn61ec9012011-04-30 00:07:43 -04001008
1009 if (id >= XUARTPS_NR_PORTS)
1010 return NULL;
1011
1012 port = &xuartps_port[id];
1013
1014 /* At this point, we've got an empty uart_port struct, initialize it */
1015 spin_lock_init(&port->lock);
1016 port->membase = NULL;
1017 port->iobase = 1; /* mark port in use */
1018 port->irq = 0;
1019 port->type = PORT_UNKNOWN;
1020 port->iotype = UPIO_MEM32;
1021 port->flags = UPF_BOOT_AUTOCONF;
1022 port->ops = &xuartps_ops;
1023 port->fifosize = XUARTPS_FIFO_SIZE;
1024 port->line = id;
1025 port->dev = NULL;
1026 return port;
1027}
1028
John Linn61ec9012011-04-30 00:07:43 -04001029#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1030/**
1031 * xuartps_console_wait_tx - Wait for the TX to be full
1032 * @port: Handle to the uart port structure
Michal Simek489810a12014-04-04 17:23:37 -07001033 */
John Linn61ec9012011-04-30 00:07:43 -04001034static void xuartps_console_wait_tx(struct uart_port *port)
1035{
1036 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
1037 != XUARTPS_SR_TXEMPTY)
1038 barrier();
1039}
1040
1041/**
1042 * xuartps_console_putchar - write the character to the FIFO buffer
1043 * @port: Handle to the uart port structure
1044 * @ch: Character to be written
Michal Simek489810a12014-04-04 17:23:37 -07001045 */
John Linn61ec9012011-04-30 00:07:43 -04001046static void xuartps_console_putchar(struct uart_port *port, int ch)
1047{
1048 xuartps_console_wait_tx(port);
1049 xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
1050}
1051
1052/**
1053 * xuartps_console_write - perform write operation
Michal Simek489810a12014-04-04 17:23:37 -07001054 * @co: Console handle
John Linn61ec9012011-04-30 00:07:43 -04001055 * @s: Pointer to character array
1056 * @count: No of characters
Michal Simek489810a12014-04-04 17:23:37 -07001057 */
John Linn61ec9012011-04-30 00:07:43 -04001058static void xuartps_console_write(struct console *co, const char *s,
1059 unsigned int count)
1060{
1061 struct uart_port *port = &xuartps_port[co->index];
1062 unsigned long flags;
Lars-Peter Clausend3755f52013-10-17 14:08:09 -07001063 unsigned int imr, ctrl;
John Linn61ec9012011-04-30 00:07:43 -04001064 int locked = 1;
1065
1066 if (oops_in_progress)
1067 locked = spin_trylock_irqsave(&port->lock, flags);
1068 else
1069 spin_lock_irqsave(&port->lock, flags);
1070
1071 /* save and disable interrupt */
1072 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
1073 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
1074
Lars-Peter Clausend3755f52013-10-17 14:08:09 -07001075 /*
1076 * Make sure that the tx part is enabled. Set the TX enable bit and
1077 * clear the TX disable bit to enable the transmitter.
1078 */
1079 ctrl = xuartps_readl(XUARTPS_CR_OFFSET);
1080 xuartps_writel((ctrl & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
1081 XUARTPS_CR_OFFSET);
1082
John Linn61ec9012011-04-30 00:07:43 -04001083 uart_console_write(port, s, count, xuartps_console_putchar);
1084 xuartps_console_wait_tx(port);
1085
Lars-Peter Clausend3755f52013-10-17 14:08:09 -07001086 xuartps_writel(ctrl, XUARTPS_CR_OFFSET);
1087
Soren Brinkmannb494a5f2014-04-04 17:23:42 -07001088 /* restore interrupt state */
John Linn61ec9012011-04-30 00:07:43 -04001089 xuartps_writel(imr, XUARTPS_IER_OFFSET);
1090
1091 if (locked)
1092 spin_unlock_irqrestore(&port->lock, flags);
1093}
1094
1095/**
1096 * xuartps_console_setup - Initialize the uart to default config
1097 * @co: Console handle
1098 * @options: Initial settings of uart
1099 *
Soren Brinkmanne555a212014-04-04 17:23:39 -07001100 * Return: 0 on success, negative errno otherwise.
Michal Simek489810a12014-04-04 17:23:37 -07001101 */
John Linn61ec9012011-04-30 00:07:43 -04001102static int __init xuartps_console_setup(struct console *co, char *options)
1103{
1104 struct uart_port *port = &xuartps_port[co->index];
1105 int baud = 9600;
1106 int bits = 8;
1107 int parity = 'n';
1108 int flow = 'n';
1109
1110 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
1111 return -EINVAL;
1112
1113 if (!port->mapbase) {
1114 pr_debug("console on ttyPS%i not present\n", co->index);
1115 return -ENODEV;
1116 }
1117
1118 if (options)
1119 uart_parse_options(options, &baud, &parity, &bits, &flow);
1120
1121 return uart_set_options(port, co, baud, parity, bits, flow);
1122}
1123
1124static struct uart_driver xuartps_uart_driver;
1125
1126static struct console xuartps_console = {
1127 .name = XUARTPS_TTY_NAME,
1128 .write = xuartps_console_write,
1129 .device = uart_console_device,
1130 .setup = xuartps_console_setup,
1131 .flags = CON_PRINTBUFFER,
1132 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1133 .data = &xuartps_uart_driver,
1134};
1135
1136/**
1137 * xuartps_console_init - Initialization call
1138 *
Soren Brinkmanne555a212014-04-04 17:23:39 -07001139 * Return: 0 on success, negative errno otherwise
Michal Simek489810a12014-04-04 17:23:37 -07001140 */
John Linn61ec9012011-04-30 00:07:43 -04001141static int __init xuartps_console_init(void)
1142{
1143 register_console(&xuartps_console);
1144 return 0;
1145}
1146
1147console_initcall(xuartps_console_init);
1148
1149#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1150
Soren Brinkmannd3641f62013-10-21 16:41:00 -07001151static struct uart_driver xuartps_uart_driver = {
Soren Brinkmanne555a212014-04-04 17:23:39 -07001152 .owner = THIS_MODULE,
1153 .driver_name = XUARTPS_NAME,
1154 .dev_name = XUARTPS_TTY_NAME,
1155 .major = XUARTPS_MAJOR,
1156 .minor = XUARTPS_MINOR,
1157 .nr = XUARTPS_NR_PORTS,
Soren Brinkmannd3641f62013-10-21 16:41:00 -07001158#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
Soren Brinkmanne555a212014-04-04 17:23:39 -07001159 .cons = &xuartps_console,
Soren Brinkmannd3641f62013-10-21 16:41:00 -07001160#endif
1161};
1162
Soren Brinkmann4b47d9a2013-10-17 14:08:12 -07001163#ifdef CONFIG_PM_SLEEP
1164/**
1165 * xuartps_suspend - suspend event
1166 * @device: Pointer to the device structure
1167 *
Michal Simek489810a12014-04-04 17:23:37 -07001168 * Return: 0
Soren Brinkmann4b47d9a2013-10-17 14:08:12 -07001169 */
1170static int xuartps_suspend(struct device *device)
1171{
1172 struct uart_port *port = dev_get_drvdata(device);
1173 struct tty_struct *tty;
1174 struct device *tty_dev;
1175 int may_wake = 0;
1176
1177 /* Get the tty which could be NULL so don't assume it's valid */
1178 tty = tty_port_tty_get(&port->state->port);
1179 if (tty) {
1180 tty_dev = tty->dev;
1181 may_wake = device_may_wakeup(tty_dev);
1182 tty_kref_put(tty);
1183 }
1184
1185 /*
1186 * Call the API provided in serial_core.c file which handles
1187 * the suspend.
1188 */
1189 uart_suspend_port(&xuartps_uart_driver, port);
1190 if (console_suspend_enabled && !may_wake) {
1191 struct xuartps *xuartps = port->private_data;
1192
1193 clk_disable(xuartps->refclk);
1194 clk_disable(xuartps->aperclk);
1195 } else {
1196 unsigned long flags = 0;
1197
1198 spin_lock_irqsave(&port->lock, flags);
1199 /* Empty the receive FIFO 1st before making changes */
1200 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY))
1201 xuartps_readl(XUARTPS_FIFO_OFFSET);
1202 /* set RX trigger level to 1 */
1203 xuartps_writel(1, XUARTPS_RXWM_OFFSET);
1204 /* disable RX timeout interrups */
1205 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IDR_OFFSET);
1206 spin_unlock_irqrestore(&port->lock, flags);
1207 }
1208
1209 return 0;
1210}
1211
1212/**
1213 * xuartps_resume - Resume after a previous suspend
1214 * @device: Pointer to the device structure
1215 *
Michal Simek489810a12014-04-04 17:23:37 -07001216 * Return: 0
Soren Brinkmann4b47d9a2013-10-17 14:08:12 -07001217 */
1218static int xuartps_resume(struct device *device)
1219{
1220 struct uart_port *port = dev_get_drvdata(device);
1221 unsigned long flags = 0;
1222 u32 ctrl_reg;
1223 struct tty_struct *tty;
1224 struct device *tty_dev;
1225 int may_wake = 0;
1226
1227 /* Get the tty which could be NULL so don't assume it's valid */
1228 tty = tty_port_tty_get(&port->state->port);
1229 if (tty) {
1230 tty_dev = tty->dev;
1231 may_wake = device_may_wakeup(tty_dev);
1232 tty_kref_put(tty);
1233 }
1234
1235 if (console_suspend_enabled && !may_wake) {
1236 struct xuartps *xuartps = port->private_data;
1237
1238 clk_enable(xuartps->aperclk);
1239 clk_enable(xuartps->refclk);
1240
1241 spin_lock_irqsave(&port->lock, flags);
1242
1243 /* Set TX/RX Reset */
Soren Brinkmann35dc5a52014-04-04 17:23:41 -07001244 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
1245 ctrl_reg |= XUARTPS_CR_TXRST | XUARTPS_CR_RXRST;
1246 xuartps_writel(ctrl_reg, XUARTPS_CR_OFFSET);
Soren Brinkmann4b47d9a2013-10-17 14:08:12 -07001247 while (xuartps_readl(XUARTPS_CR_OFFSET) &
1248 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST))
1249 cpu_relax();
1250
1251 /* restore rx timeout value */
1252 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
1253 /* Enable Tx/Rx */
1254 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
Soren Brinkmann35dc5a52014-04-04 17:23:41 -07001255 ctrl_reg &= ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS);
1256 ctrl_reg |= XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN;
1257 xuartps_writel(ctrl_reg, XUARTPS_CR_OFFSET);
Soren Brinkmann4b47d9a2013-10-17 14:08:12 -07001258
1259 spin_unlock_irqrestore(&port->lock, flags);
1260 } else {
1261 spin_lock_irqsave(&port->lock, flags);
1262 /* restore original rx trigger level */
1263 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
1264 /* enable RX timeout interrupt */
1265 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
1266 spin_unlock_irqrestore(&port->lock, flags);
1267 }
1268
1269 return uart_resume_port(&xuartps_uart_driver, port);
1270}
1271#endif /* ! CONFIG_PM_SLEEP */
1272
1273static SIMPLE_DEV_PM_OPS(xuartps_dev_pm_ops, xuartps_suspend, xuartps_resume);
1274
John Linn61ec9012011-04-30 00:07:43 -04001275/**
1276 * xuartps_probe - Platform driver probe
1277 * @pdev: Pointer to the platform device structure
1278 *
Soren Brinkmanne555a212014-04-04 17:23:39 -07001279 * Return: 0 on success, negative errno otherwise
Michal Simek489810a12014-04-04 17:23:37 -07001280 */
Bill Pemberton9671f092012-11-19 13:21:50 -05001281static int xuartps_probe(struct platform_device *pdev)
John Linn61ec9012011-04-30 00:07:43 -04001282{
Michal Simek928e9262014-04-04 17:23:38 -07001283 int rc, id;
John Linn61ec9012011-04-30 00:07:43 -04001284 struct uart_port *port;
1285 struct resource *res, *res2;
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001286 struct xuartps *xuartps_data;
John Linn61ec9012011-04-30 00:07:43 -04001287
Soren Brinkmannc03cae12013-10-17 14:08:05 -07001288 xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data),
1289 GFP_KERNEL);
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001290 if (!xuartps_data)
1291 return -ENOMEM;
1292
Soren Brinkmann991fc252013-10-17 14:08:04 -07001293 xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk");
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001294 if (IS_ERR(xuartps_data->aperclk)) {
1295 dev_err(&pdev->dev, "aper_clk clock not found.\n");
Soren Brinkmannc03cae12013-10-17 14:08:05 -07001296 return PTR_ERR(xuartps_data->aperclk);
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001297 }
Soren Brinkmann991fc252013-10-17 14:08:04 -07001298 xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk");
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001299 if (IS_ERR(xuartps_data->refclk)) {
1300 dev_err(&pdev->dev, "ref_clk clock not found.\n");
Soren Brinkmannc03cae12013-10-17 14:08:05 -07001301 return PTR_ERR(xuartps_data->refclk);
Josh Cartwright2326669c2013-01-21 19:57:41 +01001302 }
1303
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001304 rc = clk_prepare_enable(xuartps_data->aperclk);
Josh Cartwright2326669c2013-01-21 19:57:41 +01001305 if (rc) {
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001306 dev_err(&pdev->dev, "Unable to enable APER clock.\n");
Soren Brinkmannc03cae12013-10-17 14:08:05 -07001307 return rc;
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001308 }
1309 rc = clk_prepare_enable(xuartps_data->refclk);
1310 if (rc) {
1311 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1312 goto err_out_clk_dis_aper;
John Linn61ec9012011-04-30 00:07:43 -04001313 }
1314
1315 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001316 if (!res) {
1317 rc = -ENODEV;
1318 goto err_out_clk_disable;
1319 }
John Linn61ec9012011-04-30 00:07:43 -04001320
1321 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001322 if (!res2) {
1323 rc = -ENODEV;
1324 goto err_out_clk_disable;
1325 }
John Linn61ec9012011-04-30 00:07:43 -04001326
Soren Brinkmann7ac57342013-10-21 16:41:01 -07001327#ifdef CONFIG_COMMON_CLK
Soren Brinkmannc4b05102013-10-17 14:08:11 -07001328 xuartps_data->clk_rate_change_nb.notifier_call =
1329 xuartps_clk_notifier_cb;
1330 if (clk_notifier_register(xuartps_data->refclk,
1331 &xuartps_data->clk_rate_change_nb))
1332 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
Soren Brinkmann7ac57342013-10-21 16:41:01 -07001333#endif
Michal Simek928e9262014-04-04 17:23:38 -07001334 /* Look for a serialN alias */
1335 id = of_alias_get_id(pdev->dev.of_node, "serial");
1336 if (id < 0)
1337 id = 0;
Soren Brinkmannc4b05102013-10-17 14:08:11 -07001338
John Linn61ec9012011-04-30 00:07:43 -04001339 /* Initialize the port structure */
Michal Simek928e9262014-04-04 17:23:38 -07001340 port = xuartps_get_port(id);
John Linn61ec9012011-04-30 00:07:43 -04001341
1342 if (!port) {
1343 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001344 rc = -ENODEV;
Soren Brinkmannc4b05102013-10-17 14:08:11 -07001345 goto err_out_notif_unreg;
John Linn61ec9012011-04-30 00:07:43 -04001346 } else {
1347 /* Register the port.
1348 * This function also registers this device with the tty layer
1349 * and triggers invocation of the config_port() entry point.
1350 */
1351 port->mapbase = res->start;
1352 port->irq = res2->start;
1353 port->dev = &pdev->dev;
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001354 port->uartclk = clk_get_rate(xuartps_data->refclk);
1355 port->private_data = xuartps_data;
Soren Brinkmannc4b05102013-10-17 14:08:11 -07001356 xuartps_data->port = port;
Jingoo Han696faed2013-05-23 19:39:36 +09001357 platform_set_drvdata(pdev, port);
John Linn61ec9012011-04-30 00:07:43 -04001358 rc = uart_add_one_port(&xuartps_uart_driver, port);
1359 if (rc) {
1360 dev_err(&pdev->dev,
1361 "uart_add_one_port() failed; err=%i\n", rc);
Soren Brinkmannc4b05102013-10-17 14:08:11 -07001362 goto err_out_notif_unreg;
John Linn61ec9012011-04-30 00:07:43 -04001363 }
1364 return 0;
1365 }
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001366
Soren Brinkmannc4b05102013-10-17 14:08:11 -07001367err_out_notif_unreg:
Soren Brinkmann7ac57342013-10-21 16:41:01 -07001368#ifdef CONFIG_COMMON_CLK
Soren Brinkmannc4b05102013-10-17 14:08:11 -07001369 clk_notifier_unregister(xuartps_data->refclk,
1370 &xuartps_data->clk_rate_change_nb);
Soren Brinkmann7ac57342013-10-21 16:41:01 -07001371#endif
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001372err_out_clk_disable:
1373 clk_disable_unprepare(xuartps_data->refclk);
1374err_out_clk_dis_aper:
1375 clk_disable_unprepare(xuartps_data->aperclk);
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001376
1377 return rc;
John Linn61ec9012011-04-30 00:07:43 -04001378}
1379
1380/**
1381 * xuartps_remove - called when the platform driver is unregistered
1382 * @pdev: Pointer to the platform device structure
1383 *
Soren Brinkmanne555a212014-04-04 17:23:39 -07001384 * Return: 0 on success, negative errno otherwise
Michal Simek489810a12014-04-04 17:23:37 -07001385 */
Bill Pembertonae8d8a12012-11-19 13:26:18 -05001386static int xuartps_remove(struct platform_device *pdev)
John Linn61ec9012011-04-30 00:07:43 -04001387{
Jingoo Han696faed2013-05-23 19:39:36 +09001388 struct uart_port *port = platform_get_drvdata(pdev);
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001389 struct xuartps *xuartps_data = port->private_data;
Josh Cartwright2326669c2013-01-21 19:57:41 +01001390 int rc;
John Linn61ec9012011-04-30 00:07:43 -04001391
1392 /* Remove the xuartps port from the serial core */
Soren Brinkmann7ac57342013-10-21 16:41:01 -07001393#ifdef CONFIG_COMMON_CLK
Soren Brinkmannc4b05102013-10-17 14:08:11 -07001394 clk_notifier_unregister(xuartps_data->refclk,
1395 &xuartps_data->clk_rate_change_nb);
Soren Brinkmann7ac57342013-10-21 16:41:01 -07001396#endif
Josh Cartwright2326669c2013-01-21 19:57:41 +01001397 rc = uart_remove_one_port(&xuartps_uart_driver, port);
Josh Cartwright2326669c2013-01-21 19:57:41 +01001398 port->mapbase = 0;
Soren Brinkmann30e1e282013-05-13 10:46:38 -07001399 clk_disable_unprepare(xuartps_data->refclk);
1400 clk_disable_unprepare(xuartps_data->aperclk);
John Linn61ec9012011-04-30 00:07:43 -04001401 return rc;
1402}
1403
John Linn61ec9012011-04-30 00:07:43 -04001404/* Match table for of_platform binding */
Bill Pembertonde88b342012-11-19 13:24:32 -05001405static struct of_device_id xuartps_of_match[] = {
John Linn61ec9012011-04-30 00:07:43 -04001406 { .compatible = "xlnx,xuartps", },
1407 {}
1408};
1409MODULE_DEVICE_TABLE(of, xuartps_of_match);
John Linn61ec9012011-04-30 00:07:43 -04001410
1411static struct platform_driver xuartps_platform_driver = {
Soren Brinkmanne555a212014-04-04 17:23:39 -07001412 .probe = xuartps_probe,
1413 .remove = xuartps_remove,
John Linn61ec9012011-04-30 00:07:43 -04001414 .driver = {
1415 .owner = THIS_MODULE,
Soren Brinkmanne555a212014-04-04 17:23:39 -07001416 .name = XUARTPS_NAME,
John Linn61ec9012011-04-30 00:07:43 -04001417 .of_match_table = xuartps_of_match,
Soren Brinkmann4b47d9a2013-10-17 14:08:12 -07001418 .pm = &xuartps_dev_pm_ops,
John Linn61ec9012011-04-30 00:07:43 -04001419 },
1420};
1421
John Linn61ec9012011-04-30 00:07:43 -04001422static int __init xuartps_init(void)
1423{
1424 int retval = 0;
1425
1426 /* Register the xuartps driver with the serial core */
1427 retval = uart_register_driver(&xuartps_uart_driver);
1428 if (retval)
1429 return retval;
1430
1431 /* Register the platform driver */
1432 retval = platform_driver_register(&xuartps_platform_driver);
1433 if (retval)
1434 uart_unregister_driver(&xuartps_uart_driver);
1435
1436 return retval;
1437}
1438
John Linn61ec9012011-04-30 00:07:43 -04001439static void __exit xuartps_exit(void)
1440{
John Linn61ec9012011-04-30 00:07:43 -04001441 /* Unregister the platform driver */
1442 platform_driver_unregister(&xuartps_platform_driver);
1443
1444 /* Unregister the xuartps driver */
1445 uart_unregister_driver(&xuartps_uart_driver);
1446}
1447
1448module_init(xuartps_init);
1449module_exit(xuartps_exit);
1450
1451MODULE_DESCRIPTION("Driver for PS UART");
1452MODULE_AUTHOR("Xilinx Inc.");
1453MODULE_LICENSE("GPL");