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Tim Harveye3946fe2014-02-07 15:24:56 +08001/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Tim Harvey326cdb12014-09-08 23:07:28 -070012#include <dt-bindings/gpio/gpio.h>
13
Tim Harveye3946fe2014-02-07 15:24:56 +080014/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
Tim Harveye3946fe2014-02-07 15:24:56 +080017 led0 = &led0;
18 led1 = &led1;
19 led2 = &led2;
20 nand = &gpmi;
21 ssi0 = &ssi1;
22 usb0 = &usbh1;
23 usb1 = &usbotg;
Tim Harveye3946fe2014-02-07 15:24:56 +080024 };
25
26 chosen {
27 bootargs = "console=ttymxc1,115200";
28 };
29
Tim Harveyb3253242014-04-30 23:32:30 -070030 backlight {
31 compatible = "pwm-backlight";
32 pwms = <&pwm4 0 5000000>;
33 brightness-levels = <0 4 8 16 32 64 128 255>;
34 default-brightness-level = <7>;
35 };
36
Tim Harveye3946fe2014-02-07 15:24:56 +080037 leds {
38 compatible = "gpio-leds";
Tim Harveyb5f37b72014-09-08 23:07:30 -070039 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_gpio_leds>;
Tim Harveye3946fe2014-02-07 15:24:56 +080041
42 led0: user1 {
43 label = "user1";
Tim Harvey326cdb12014-09-08 23:07:28 -070044 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
Tim Harveye3946fe2014-02-07 15:24:56 +080045 default-state = "on";
46 linux,default-trigger = "heartbeat";
47 };
48
49 led1: user2 {
50 label = "user2";
Tim Harvey326cdb12014-09-08 23:07:28 -070051 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
Tim Harveye3946fe2014-02-07 15:24:56 +080052 default-state = "off";
53 };
54
55 led2: user3 {
56 label = "user3";
Tim Harvey326cdb12014-09-08 23:07:28 -070057 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
Tim Harveye3946fe2014-02-07 15:24:56 +080058 default-state = "off";
59 };
60 };
61
62 memory {
63 reg = <0x10000000 0x20000000>;
64 };
65
66 pps {
67 compatible = "pps-gpio";
Tim Harveyb5f37b72014-09-08 23:07:30 -070068 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pps>;
Tim Harvey326cdb12014-09-08 23:07:28 -070070 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
Tim Harveye3946fe2014-02-07 15:24:56 +080071 status = "okay";
72 };
73
74 regulators {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 reg_1p0v: regulator@0 {
80 compatible = "regulator-fixed";
81 reg = <0>;
82 regulator-name = "1P0V";
83 regulator-min-microvolt = <1000000>;
84 regulator-max-microvolt = <1000000>;
85 regulator-always-on;
86 };
87
88 /* remove this fixed regulator once ltc3676__sw2 driver available */
89 reg_1p8v: regulator@1 {
90 compatible = "regulator-fixed";
91 reg = <1>;
92 regulator-name = "1P8V";
93 regulator-min-microvolt = <1800000>;
94 regulator-max-microvolt = <1800000>;
95 regulator-always-on;
96 };
97
98 reg_3p3v: regulator@2 {
99 compatible = "regulator-fixed";
100 reg = <2>;
101 regulator-name = "3P3V";
102 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>;
104 regulator-always-on;
105 };
106
107 reg_5p0v: regulator@3 {
108 compatible = "regulator-fixed";
109 reg = <3>;
110 regulator-name = "5P0V";
111 regulator-min-microvolt = <5000000>;
112 regulator-max-microvolt = <5000000>;
113 regulator-always-on;
114 };
115
116 reg_usb_otg_vbus: regulator@4 {
117 compatible = "regulator-fixed";
118 reg = <4>;
119 regulator-name = "usb_otg_vbus";
120 regulator-min-microvolt = <5000000>;
121 regulator-max-microvolt = <5000000>;
Tim Harvey326cdb12014-09-08 23:07:28 -0700122 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
Tim Harveye3946fe2014-02-07 15:24:56 +0800123 enable-active-high;
124 };
125 };
126
127 sound {
Tim Harveyb12d1e92014-05-21 23:04:54 -0700128 compatible = "fsl,imx6q-ventana-sgtl5000",
Tim Harveye3946fe2014-02-07 15:24:56 +0800129 "fsl,imx-audio-sgtl5000";
Tim Harveyb12d1e92014-05-21 23:04:54 -0700130 model = "sgtl5000-audio";
Tim Harveye3946fe2014-02-07 15:24:56 +0800131 ssi-controller = <&ssi1>;
132 audio-codec = <&codec>;
133 audio-routing =
134 "MIC_IN", "Mic Jack",
135 "Mic Jack", "Mic Bias",
136 "Headphone Jack", "HP_OUT";
137 mux-int-port = <1>;
138 mux-ext-port = <4>;
139 };
140};
141
142&audmux {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_audmux>;
145 status = "okay";
146};
147
148&fec {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_enet>;
151 phy-mode = "rgmii";
Tim Harvey326cdb12014-09-08 23:07:28 -0700152 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
Tim Harveye3946fe2014-02-07 15:24:56 +0800153 status = "okay";
154};
155
156&gpmi {
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_gpmi_nand>;
159 status = "okay";
160};
161
Tim Harveyaef15db2014-04-23 00:47:51 -0700162&hdmi {
163 ddc-i2c-bus = <&i2c3>;
164 status = "okay";
165};
166
Tim Harveye3946fe2014-02-07 15:24:56 +0800167&i2c1 {
168 clock-frequency = <100000>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_i2c1>;
171 status = "okay";
172
173 eeprom1: eeprom@50 {
174 compatible = "atmel,24c02";
175 reg = <0x50>;
176 pagesize = <16>;
177 };
178
179 eeprom2: eeprom@51 {
180 compatible = "atmel,24c02";
181 reg = <0x51>;
182 pagesize = <16>;
183 };
184
185 eeprom3: eeprom@52 {
186 compatible = "atmel,24c02";
187 reg = <0x52>;
188 pagesize = <16>;
189 };
190
191 eeprom4: eeprom@53 {
192 compatible = "atmel,24c02";
193 reg = <0x53>;
194 pagesize = <16>;
195 };
196
197 gpio: pca9555@23 {
198 compatible = "nxp,pca9555";
199 reg = <0x23>;
200 gpio-controller;
201 #gpio-cells = <2>;
202 };
203
Tim Harveye3946fe2014-02-07 15:24:56 +0800204 rtc: ds1672@68 {
205 compatible = "dallas,ds1672";
206 reg = <0x68>;
207 };
208};
209
210&i2c2 {
211 clock-frequency = <100000>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_i2c2>;
214 status = "okay";
Tim Harveye3946fe2014-02-07 15:24:56 +0800215};
216
217&i2c3 {
218 clock-frequency = <100000>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_i2c3>;
221 status = "okay";
222
Tim Harveye3946fe2014-02-07 15:24:56 +0800223 codec: sgtl5000@0a {
224 compatible = "fsl,sgtl5000";
225 reg = <0x0a>;
Tim Harvey5b4c1802014-06-02 11:44:01 -0700226 clocks = <&clks 201>;
Tim Harveye3946fe2014-02-07 15:24:56 +0800227 VDDA-supply = <&reg_1p8v>;
228 VDDIO-supply = <&reg_3p3v>;
229 };
230
231 touchscreen: egalax_ts@04 {
232 compatible = "eeti,egalax_ts";
233 reg = <0x04>;
234 interrupt-parent = <&gpio7>;
Tim Harvey326cdb12014-09-08 23:07:28 -0700235 interrupts = <12 2>;
236 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
Tim Harveye3946fe2014-02-07 15:24:56 +0800237 };
Tim Harveye3946fe2014-02-07 15:24:56 +0800238};
239
Tim Harveyb5f37b72014-09-08 23:07:30 -0700240&ldb {
241 status = "okay";
Tim Harveye3946fe2014-02-07 15:24:56 +0800242
Tim Harveyb5f37b72014-09-08 23:07:30 -0700243 lvds-channel@0 {
244 fsl,data-mapping = "spwg";
245 fsl,data-width = <18>;
246 status = "okay";
247
248 display-timings {
249 native-mode = <&timing0>;
250 timing0: hsd100pxn1 {
251 clock-frequency = <65000000>;
252 hactive = <1024>;
253 vactive = <768>;
254 hback-porch = <220>;
255 hfront-porch = <40>;
256 vback-porch = <21>;
257 vfront-porch = <7>;
258 hsync-len = <60>;
259 vsync-len = <10>;
260 };
Tim Harveye3946fe2014-02-07 15:24:56 +0800261 };
Tim Harveyb5f37b72014-09-08 23:07:30 -0700262 };
263};
Tim Harveye3946fe2014-02-07 15:24:56 +0800264
Tim Harveyb5f37b72014-09-08 23:07:30 -0700265&pcie {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_pcie>;
268 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
269 status = "okay";
270};
271
272&pwm4 {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_pwm4>;
275 status = "okay";
276};
277
278&ssi1 {
279 fsl,mode = "i2s-slave";
280 status = "okay";
281};
282
283&uart1 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_uart1>;
286 status = "okay";
287};
288
289&uart2 {
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_uart2>;
292 status = "okay";
293};
294
295&uart5 {
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_uart5>;
298 status = "okay";
299};
300
301&usbotg {
302 vbus-supply = <&reg_usb_otg_vbus>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_usbotg>;
305 disable-over-current;
306 status = "okay";
307};
308
309&usbh1 {
310 status = "okay";
311};
312
313&usdhc3 {
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usdhc3>;
316 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
317 vmmc-supply = <&reg_3p3v>;
318 status = "okay";
319};
320
321&iomuxc {
322 imx6qdl-gw52xx {
Tim Harveye3946fe2014-02-07 15:24:56 +0800323 pinctrl_audmux: audmuxgrp {
324 fsl,pins = <
325 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
326 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
327 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
328 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
Tim Harveyb5f37b72014-09-08 23:07:30 -0700329 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
Tim Harveye3946fe2014-02-07 15:24:56 +0800330 >;
331 };
332
333 pinctrl_enet: enetgrp {
334 fsl,pins = <
335 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
336 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
337 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
338 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
339 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
340 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
341 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
342 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
343 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
344 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
345 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
346 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
347 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
348 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
349 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
350 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
Tim Harveyb5f37b72014-09-08 23:07:30 -0700351 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
352 >;
353 };
354
355 pinctrl_gpio_leds: gpioledsgrp {
356 fsl,pins = <
357 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
358 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
359 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
Tim Harveye3946fe2014-02-07 15:24:56 +0800360 >;
361 };
362
363 pinctrl_gpmi_nand: gpminandgrp {
364 fsl,pins = <
365 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
366 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
367 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
368 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
369 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
370 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
371 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
372 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
373 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
374 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
375 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
376 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
377 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
378 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
379 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
380 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
381 >;
382 };
383
384 pinctrl_i2c1: i2c1grp {
385 fsl,pins = <
386 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
387 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
388 >;
389 };
390
391 pinctrl_i2c2: i2c2grp {
392 fsl,pins = <
393 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
394 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
395 >;
396 };
397
398 pinctrl_i2c3: i2c3grp {
399 fsl,pins = <
400 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
401 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
402 >;
403 };
404
Tim Harveyb5f37b72014-09-08 23:07:30 -0700405 pinctrl_pcie: pciegrp {
406 fsl,pins = <
407 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
408 >;
409 };
410
411 pinctrl_pps: ppsgrp {
412 fsl,pins = <
413 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
414 >;
415 };
416
Tim Harveyb3253242014-04-30 23:32:30 -0700417 pinctrl_pwm4: pwm4grp {
418 fsl,pins = <
419 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
420 >;
421 };
422
Tim Harveye3946fe2014-02-07 15:24:56 +0800423 pinctrl_uart1: uart1grp {
424 fsl,pins = <
425 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
426 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
427 >;
428 };
429
430 pinctrl_uart2: uart2grp {
431 fsl,pins = <
432 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
433 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
434 >;
435 };
436
437 pinctrl_uart5: uart5grp {
438 fsl,pins = <
439 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
440 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
441 >;
442 };
443
444 pinctrl_usbotg: usbotggrp {
445 fsl,pins = <
446 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
Tim Harveyb5f37b72014-09-08 23:07:30 -0700447 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
Tim Harveye3946fe2014-02-07 15:24:56 +0800448 >;
449 };
450
451 pinctrl_usdhc3: usdhc3grp {
452 fsl,pins = <
453 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
454 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
455 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
456 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
457 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
458 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
Tim Harveyb5f37b72014-09-08 23:07:30 -0700459 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
Tim Harveye3946fe2014-02-07 15:24:56 +0800460 >;
461 };
462 };
463};