Sascha Hauer | 2af9e6d | 2012-03-09 09:11:55 +0100 | [diff] [blame] | 1 | #include <linux/clk-provider.h> |
| 2 | #include <linux/io.h> |
| 3 | #include <linux/slab.h> |
| 4 | #include <linux/kernel.h> |
| 5 | #include <linux/err.h> |
Sascha Hauer | 3a84d17 | 2012-09-11 08:50:00 +0200 | [diff] [blame] | 6 | |
Sascha Hauer | 2af9e6d | 2012-03-09 09:11:55 +0100 | [diff] [blame] | 7 | #include "clk.h" |
| 8 | |
| 9 | /** |
| 10 | * pll v1 |
| 11 | * |
| 12 | * @clk_hw clock source |
| 13 | * @parent the parent clock name |
| 14 | * @base base address of pll registers |
| 15 | * |
| 16 | * PLL clock version 1, found on i.MX1/21/25/27/31/35 |
| 17 | */ |
Alexander Shiyan | a594790 | 2013-11-10 13:34:49 +0400 | [diff] [blame] | 18 | |
| 19 | #define MFN_BITS (10) |
| 20 | #define MFN_SIGN (BIT(MFN_BITS - 1)) |
| 21 | #define MFN_MASK (MFN_SIGN - 1) |
| 22 | |
Sascha Hauer | 2af9e6d | 2012-03-09 09:11:55 +0100 | [diff] [blame] | 23 | struct clk_pllv1 { |
| 24 | struct clk_hw hw; |
| 25 | void __iomem *base; |
Shawn Guo | 3bec5f8 | 2015-04-26 13:33:39 +0800 | [diff] [blame] | 26 | enum imx_pllv1_type type; |
Sascha Hauer | 2af9e6d | 2012-03-09 09:11:55 +0100 | [diff] [blame] | 27 | }; |
| 28 | |
| 29 | #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk)) |
| 30 | |
Shawn Guo | 3bec5f8 | 2015-04-26 13:33:39 +0800 | [diff] [blame] | 31 | static inline bool is_imx1_pllv1(struct clk_pllv1 *pll) |
Alexander Shiyan | a594790 | 2013-11-10 13:34:49 +0400 | [diff] [blame] | 32 | { |
Shawn Guo | 3bec5f8 | 2015-04-26 13:33:39 +0800 | [diff] [blame] | 33 | return pll->type == IMX_PLLV1_IMX1; |
| 34 | } |
| 35 | |
| 36 | static inline bool is_imx21_pllv1(struct clk_pllv1 *pll) |
| 37 | { |
| 38 | return pll->type == IMX_PLLV1_IMX21; |
| 39 | } |
| 40 | |
| 41 | static inline bool is_imx27_pllv1(struct clk_pllv1 *pll) |
| 42 | { |
| 43 | return pll->type == IMX_PLLV1_IMX27; |
| 44 | } |
| 45 | |
| 46 | static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn) |
| 47 | { |
| 48 | return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN); |
Alexander Shiyan | a594790 | 2013-11-10 13:34:49 +0400 | [diff] [blame] | 49 | } |
| 50 | |
Sascha Hauer | 2af9e6d | 2012-03-09 09:11:55 +0100 | [diff] [blame] | 51 | static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, |
| 52 | unsigned long parent_rate) |
| 53 | { |
| 54 | struct clk_pllv1 *pll = to_clk_pllv1(hw); |
Sascha Hauer | a6dd3c8 | 2012-09-11 08:40:38 +0200 | [diff] [blame] | 55 | long long ll; |
| 56 | int mfn_abs; |
| 57 | unsigned int mfi, mfn, mfd, pd; |
| 58 | u32 reg; |
| 59 | unsigned long rate; |
Sascha Hauer | 2af9e6d | 2012-03-09 09:11:55 +0100 | [diff] [blame] | 60 | |
Sascha Hauer | a6dd3c8 | 2012-09-11 08:40:38 +0200 | [diff] [blame] | 61 | reg = readl(pll->base); |
| 62 | |
| 63 | /* |
| 64 | * Get the resulting clock rate from a PLL register value and the input |
| 65 | * frequency. PLLs with this register layout can be found on i.MX1, |
| 66 | * i.MX21, i.MX27 and i,MX31 |
| 67 | * |
| 68 | * mfi + mfn / (mfd + 1) |
| 69 | * f = 2 * f_ref * -------------------- |
| 70 | * pd + 1 |
| 71 | */ |
| 72 | |
| 73 | mfi = (reg >> 10) & 0xf; |
| 74 | mfn = reg & 0x3ff; |
| 75 | mfd = (reg >> 16) & 0x3ff; |
| 76 | pd = (reg >> 26) & 0xf; |
| 77 | |
| 78 | mfi = mfi <= 5 ? 5 : mfi; |
| 79 | |
| 80 | mfn_abs = mfn; |
| 81 | |
| 82 | /* |
| 83 | * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit |
Alexander Shiyan | a594790 | 2013-11-10 13:34:49 +0400 | [diff] [blame] | 84 | * 2's complements number. |
| 85 | * On i.MX27 the bit 9 is the sign bit. |
Sascha Hauer | a6dd3c8 | 2012-09-11 08:40:38 +0200 | [diff] [blame] | 86 | */ |
Shawn Guo | 3bec5f8 | 2015-04-26 13:33:39 +0800 | [diff] [blame] | 87 | if (mfn_is_negative(pll, mfn)) { |
| 88 | if (is_imx27_pllv1(pll)) |
Alexander Shiyan | a594790 | 2013-11-10 13:34:49 +0400 | [diff] [blame] | 89 | mfn_abs = mfn & MFN_MASK; |
| 90 | else |
| 91 | mfn_abs = BIT(MFN_BITS) - mfn; |
| 92 | } |
Sascha Hauer | a6dd3c8 | 2012-09-11 08:40:38 +0200 | [diff] [blame] | 93 | |
| 94 | rate = parent_rate * 2; |
| 95 | rate /= pd + 1; |
| 96 | |
| 97 | ll = (unsigned long long)rate * mfn_abs; |
| 98 | |
| 99 | do_div(ll, mfd + 1); |
| 100 | |
Shawn Guo | 3bec5f8 | 2015-04-26 13:33:39 +0800 | [diff] [blame] | 101 | if (mfn_is_negative(pll, mfn)) |
Sascha Hauer | a6dd3c8 | 2012-09-11 08:40:38 +0200 | [diff] [blame] | 102 | ll = -ll; |
| 103 | |
| 104 | ll = (rate * mfi) + ll; |
| 105 | |
| 106 | return ll; |
Sascha Hauer | 2af9e6d | 2012-03-09 09:11:55 +0100 | [diff] [blame] | 107 | } |
| 108 | |
Fabio Estevam | e9d8ab8 | 2013-03-25 09:20:33 -0300 | [diff] [blame] | 109 | static struct clk_ops clk_pllv1_ops = { |
Sascha Hauer | 2af9e6d | 2012-03-09 09:11:55 +0100 | [diff] [blame] | 110 | .recalc_rate = clk_pllv1_recalc_rate, |
| 111 | }; |
| 112 | |
Shawn Guo | 3bec5f8 | 2015-04-26 13:33:39 +0800 | [diff] [blame] | 113 | struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, |
| 114 | const char *parent, void __iomem *base) |
Sascha Hauer | 2af9e6d | 2012-03-09 09:11:55 +0100 | [diff] [blame] | 115 | { |
| 116 | struct clk_pllv1 *pll; |
| 117 | struct clk *clk; |
| 118 | struct clk_init_data init; |
| 119 | |
| 120 | pll = kmalloc(sizeof(*pll), GFP_KERNEL); |
| 121 | if (!pll) |
| 122 | return ERR_PTR(-ENOMEM); |
| 123 | |
| 124 | pll->base = base; |
Shawn Guo | 3bec5f8 | 2015-04-26 13:33:39 +0800 | [diff] [blame] | 125 | pll->type = type; |
Sascha Hauer | 2af9e6d | 2012-03-09 09:11:55 +0100 | [diff] [blame] | 126 | |
| 127 | init.name = name; |
| 128 | init.ops = &clk_pllv1_ops; |
| 129 | init.flags = 0; |
| 130 | init.parent_names = &parent; |
| 131 | init.num_parents = 1; |
| 132 | |
| 133 | pll->hw.init = &init; |
| 134 | |
| 135 | clk = clk_register(NULL, &pll->hw); |
| 136 | if (IS_ERR(clk)) |
| 137 | kfree(pll); |
| 138 | |
| 139 | return clk; |
| 140 | } |