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Russell Kinga09e64f2008-08-05 16:14:15 +01001/*
2 * arch/arm/mach-at91/include/mach/at91_dbgu.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Debug Unit (DBGU) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_DBGU_H
17#define AT91_DBGU_H
18
Jean-Christophe PLAGNIOL-VILLARD13079a72011-11-02 01:43:31 +080019#if !defined(CONFIG_ARCH_AT91X40)
Jean-Christophe PLAGNIOL-VILLARD1ff5b1b2011-05-03 01:11:25 +080020#define AT91_DBGU_CR (0x00) /* Control Register */
21#define AT91_DBGU_MR (0x04) /* Mode Register */
22#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
Russell Kinga09e64f2008-08-05 16:14:15 +010023#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
24#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
Jean-Christophe PLAGNIOL-VILLARD1ff5b1b2011-05-03 01:11:25 +080025#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */
26#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */
27#define AT91_DBGU_SR (0x14) /* Status Register */
28#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */
29#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
30#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */
Russell Kinga09e64f2008-08-05 16:14:15 +010031
Jean-Christophe PLAGNIOL-VILLARD1ff5b1b2011-05-03 01:11:25 +080032#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */
33#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */
34#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
Russell Kinga09e64f2008-08-05 16:14:15 +010035#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
36
37#endif /* AT91_DBGU */
38
39/*
40 * Some AT91 parts that don't have full DEBUG units still support the ID
41 * and extensions register.
42 */
43#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
44#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
45#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
46#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
47#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
48#define AT91_CIDR_SRAMSIZ_1K (1 << 16)
49#define AT91_CIDR_SRAMSIZ_2K (2 << 16)
50#define AT91_CIDR_SRAMSIZ_112K (4 << 16)
51#define AT91_CIDR_SRAMSIZ_4K (5 << 16)
52#define AT91_CIDR_SRAMSIZ_80K (6 << 16)
53#define AT91_CIDR_SRAMSIZ_160K (7 << 16)
54#define AT91_CIDR_SRAMSIZ_8K (8 << 16)
55#define AT91_CIDR_SRAMSIZ_16K (9 << 16)
56#define AT91_CIDR_SRAMSIZ_32K (10 << 16)
57#define AT91_CIDR_SRAMSIZ_64K (11 << 16)
58#define AT91_CIDR_SRAMSIZ_128K (12 << 16)
59#define AT91_CIDR_SRAMSIZ_256K (13 << 16)
60#define AT91_CIDR_SRAMSIZ_96K (14 << 16)
61#define AT91_CIDR_SRAMSIZ_512K (15 << 16)
62#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
63#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
64#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
65
66#endif