Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
| 3 | * VA Linux Systems Inc., Fremont, California. |
| 4 | * Copyright 2008 Red Hat Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Original Authors: |
| 25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
| 26 | * |
| 27 | * Kernel port Author: Dave Airlie |
| 28 | */ |
| 29 | |
| 30 | #ifndef RADEON_MODE_H |
| 31 | #define RADEON_MODE_H |
| 32 | |
| 33 | #include <drm_crtc.h> |
| 34 | #include <drm_mode.h> |
| 35 | #include <drm_edid.h> |
| 36 | #include <linux/i2c.h> |
| 37 | #include <linux/i2c-id.h> |
| 38 | #include <linux/i2c-algo-bit.h> |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 39 | #include "radeon_fixed.h" |
| 40 | |
| 41 | struct radeon_device; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 42 | |
| 43 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
| 44 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
| 45 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
| 46 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
| 47 | |
| 48 | enum radeon_connector_type { |
| 49 | CONNECTOR_NONE, |
| 50 | CONNECTOR_VGA, |
| 51 | CONNECTOR_DVI_I, |
| 52 | CONNECTOR_DVI_D, |
| 53 | CONNECTOR_DVI_A, |
| 54 | CONNECTOR_STV, |
| 55 | CONNECTOR_CTV, |
| 56 | CONNECTOR_LVDS, |
| 57 | CONNECTOR_DIGITAL, |
| 58 | CONNECTOR_SCART, |
| 59 | CONNECTOR_HDMI_TYPE_A, |
| 60 | CONNECTOR_HDMI_TYPE_B, |
| 61 | CONNECTOR_0XC, |
| 62 | CONNECTOR_0XD, |
| 63 | CONNECTOR_DIN, |
| 64 | CONNECTOR_DISPLAY_PORT, |
| 65 | CONNECTOR_UNSUPPORTED |
| 66 | }; |
| 67 | |
| 68 | enum radeon_dvi_type { |
| 69 | DVI_AUTO, |
| 70 | DVI_DIGITAL, |
| 71 | DVI_ANALOG |
| 72 | }; |
| 73 | |
| 74 | enum radeon_rmx_type { |
| 75 | RMX_OFF, |
| 76 | RMX_FULL, |
| 77 | RMX_CENTER, |
| 78 | RMX_ASPECT |
| 79 | }; |
| 80 | |
| 81 | enum radeon_tv_std { |
| 82 | TV_STD_NTSC, |
| 83 | TV_STD_PAL, |
| 84 | TV_STD_PAL_M, |
| 85 | TV_STD_PAL_60, |
| 86 | TV_STD_NTSC_J, |
| 87 | TV_STD_SCART_PAL, |
| 88 | TV_STD_SECAM, |
| 89 | TV_STD_PAL_CN, |
| 90 | }; |
| 91 | |
| 92 | struct radeon_i2c_bus_rec { |
| 93 | bool valid; |
| 94 | uint32_t mask_clk_reg; |
| 95 | uint32_t mask_data_reg; |
| 96 | uint32_t a_clk_reg; |
| 97 | uint32_t a_data_reg; |
| 98 | uint32_t put_clk_reg; |
| 99 | uint32_t put_data_reg; |
| 100 | uint32_t get_clk_reg; |
| 101 | uint32_t get_data_reg; |
| 102 | uint32_t mask_clk_mask; |
| 103 | uint32_t mask_data_mask; |
| 104 | uint32_t put_clk_mask; |
| 105 | uint32_t put_data_mask; |
| 106 | uint32_t get_clk_mask; |
| 107 | uint32_t get_data_mask; |
| 108 | uint32_t a_clk_mask; |
| 109 | uint32_t a_data_mask; |
| 110 | }; |
| 111 | |
| 112 | struct radeon_tmds_pll { |
| 113 | uint32_t freq; |
| 114 | uint32_t value; |
| 115 | }; |
| 116 | |
| 117 | #define RADEON_MAX_BIOS_CONNECTOR 16 |
| 118 | |
| 119 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
| 120 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
| 121 | #define RADEON_PLL_USE_REF_DIV (1 << 2) |
| 122 | #define RADEON_PLL_LEGACY (1 << 3) |
| 123 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
| 124 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
| 125 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
| 126 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
| 127 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
| 128 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
| 129 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
Alex Deucher | d0e275a | 2009-07-13 11:08:18 -0400 | [diff] [blame] | 130 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 131 | |
| 132 | struct radeon_pll { |
| 133 | uint16_t reference_freq; |
| 134 | uint16_t reference_div; |
| 135 | uint32_t pll_in_min; |
| 136 | uint32_t pll_in_max; |
| 137 | uint32_t pll_out_min; |
| 138 | uint32_t pll_out_max; |
| 139 | uint16_t xclk; |
| 140 | |
| 141 | uint32_t min_ref_div; |
| 142 | uint32_t max_ref_div; |
| 143 | uint32_t min_post_div; |
| 144 | uint32_t max_post_div; |
| 145 | uint32_t min_feedback_div; |
| 146 | uint32_t max_feedback_div; |
| 147 | uint32_t min_frac_feedback_div; |
| 148 | uint32_t max_frac_feedback_div; |
| 149 | uint32_t best_vco; |
| 150 | }; |
| 151 | |
| 152 | struct radeon_i2c_chan { |
| 153 | struct drm_device *dev; |
| 154 | struct i2c_adapter adapter; |
| 155 | struct i2c_algo_bit_data algo; |
| 156 | struct radeon_i2c_bus_rec rec; |
| 157 | }; |
| 158 | |
| 159 | /* mostly for macs, but really any system without connector tables */ |
| 160 | enum radeon_connector_table { |
| 161 | CT_NONE, |
| 162 | CT_GENERIC, |
| 163 | CT_IBOOK, |
| 164 | CT_POWERBOOK_EXTERNAL, |
| 165 | CT_POWERBOOK_INTERNAL, |
| 166 | CT_POWERBOOK_VGA, |
| 167 | CT_MINI_EXTERNAL, |
| 168 | CT_MINI_INTERNAL, |
| 169 | CT_IMAC_G5_ISIGHT, |
| 170 | CT_EMAC, |
| 171 | }; |
| 172 | |
| 173 | struct radeon_mode_info { |
| 174 | struct atom_context *atom_context; |
Mathias Fröhlich | 61c4b24 | 2009-10-27 15:08:01 -0400 | [diff] [blame] | 175 | struct card_info *atom_card_info; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 176 | enum radeon_connector_table connector_table; |
| 177 | bool mode_config_initialized; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 178 | struct radeon_crtc *crtcs[2]; |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 179 | /* DVI-I properties */ |
| 180 | struct drm_property *coherent_mode_property; |
| 181 | /* DAC enable load detect */ |
| 182 | struct drm_property *load_detect_property; |
| 183 | /* TV standard load detect */ |
| 184 | struct drm_property *tv_std_property; |
| 185 | /* legacy TMDS PLL detect */ |
| 186 | struct drm_property *tmds_pll_property; |
| 187 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 188 | }; |
| 189 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 190 | #define MAX_H_CODE_TIMING_LEN 32 |
| 191 | #define MAX_V_CODE_TIMING_LEN 32 |
| 192 | |
| 193 | /* need to store these as reading |
| 194 | back code tables is excessive */ |
| 195 | struct radeon_tv_regs { |
| 196 | uint32_t tv_uv_adr; |
| 197 | uint32_t timing_cntl; |
| 198 | uint32_t hrestart; |
| 199 | uint32_t vrestart; |
| 200 | uint32_t frestart; |
| 201 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; |
| 202 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
| 203 | }; |
| 204 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 205 | struct radeon_crtc { |
| 206 | struct drm_crtc base; |
| 207 | int crtc_id; |
| 208 | u16 lut_r[256], lut_g[256], lut_b[256]; |
| 209 | bool enabled; |
| 210 | bool can_tile; |
| 211 | uint32_t crtc_offset; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 212 | struct drm_gem_object *cursor_bo; |
| 213 | uint64_t cursor_addr; |
| 214 | int cursor_width; |
| 215 | int cursor_height; |
Dave Airlie | 4162338 | 2009-07-09 15:04:19 +1000 | [diff] [blame] | 216 | uint32_t legacy_display_base_addr; |
Alex Deucher | c836e86 | 2009-07-13 13:51:03 -0400 | [diff] [blame] | 217 | uint32_t legacy_cursor_offset; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 218 | enum radeon_rmx_type rmx_type; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 219 | fixed20_12 vsc; |
| 220 | fixed20_12 hsc; |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 221 | struct drm_display_mode native_mode; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 222 | }; |
| 223 | |
| 224 | struct radeon_encoder_primary_dac { |
| 225 | /* legacy primary dac */ |
| 226 | uint32_t ps2_pdac_adj; |
| 227 | }; |
| 228 | |
| 229 | struct radeon_encoder_lvds { |
| 230 | /* legacy lvds */ |
| 231 | uint16_t panel_vcc_delay; |
| 232 | uint8_t panel_pwr_delay; |
| 233 | uint8_t panel_digon_delay; |
| 234 | uint8_t panel_blon_delay; |
| 235 | uint16_t panel_ref_divider; |
| 236 | uint8_t panel_post_divider; |
| 237 | uint16_t panel_fb_divider; |
| 238 | bool use_bios_dividers; |
| 239 | uint32_t lvds_gen_cntl; |
| 240 | /* panel mode */ |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 241 | struct drm_display_mode native_mode; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 242 | }; |
| 243 | |
| 244 | struct radeon_encoder_tv_dac { |
| 245 | /* legacy tv dac */ |
| 246 | uint32_t ps2_tvdac_adj; |
| 247 | uint32_t ntsc_tvdac_adj; |
| 248 | uint32_t pal_tvdac_adj; |
| 249 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 250 | int h_pos; |
| 251 | int v_pos; |
| 252 | int h_size; |
| 253 | int supported_tv_stds; |
| 254 | bool tv_on; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 255 | enum radeon_tv_std tv_std; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 256 | struct radeon_tv_regs tv; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 257 | }; |
| 258 | |
| 259 | struct radeon_encoder_int_tmds { |
| 260 | /* legacy int tmds */ |
| 261 | struct radeon_tmds_pll tmds_pll[4]; |
| 262 | }; |
| 263 | |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 264 | /* spread spectrum */ |
| 265 | struct radeon_atom_ss { |
| 266 | uint16_t percentage; |
| 267 | uint8_t type; |
| 268 | uint8_t step; |
| 269 | uint8_t delay; |
| 270 | uint8_t range; |
| 271 | uint8_t refdiv; |
| 272 | }; |
| 273 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 274 | struct radeon_encoder_atom_dig { |
| 275 | /* atom dig */ |
| 276 | bool coherent_mode; |
| 277 | int dig_block; |
| 278 | /* atom lvds */ |
| 279 | uint32_t lvds_misc; |
| 280 | uint16_t panel_pwr_delay; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 281 | struct radeon_atom_ss *ss; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 282 | /* panel mode */ |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 283 | struct drm_display_mode native_mode; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 284 | }; |
| 285 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 286 | struct radeon_encoder_atom_dac { |
| 287 | enum radeon_tv_std tv_std; |
| 288 | }; |
| 289 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 290 | struct radeon_encoder { |
| 291 | struct drm_encoder base; |
| 292 | uint32_t encoder_id; |
| 293 | uint32_t devices; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 294 | uint32_t active_device; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 295 | uint32_t flags; |
| 296 | uint32_t pixel_clock; |
| 297 | enum radeon_rmx_type rmx_type; |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 298 | struct drm_display_mode native_mode; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 299 | void *enc_priv; |
| 300 | }; |
| 301 | |
| 302 | struct radeon_connector_atom_dig { |
| 303 | uint32_t igp_lane_info; |
| 304 | bool linkb; |
| 305 | }; |
| 306 | |
| 307 | struct radeon_connector { |
| 308 | struct drm_connector base; |
| 309 | uint32_t connector_id; |
| 310 | uint32_t devices; |
| 311 | struct radeon_i2c_chan *ddc_bus; |
Alex Deucher | 0294cf4f | 2009-10-15 16:16:35 -0400 | [diff] [blame] | 312 | /* some systems have a an hdmi and vga port with a shared ddc line */ |
| 313 | bool shared_ddc; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 314 | bool use_digital; |
| 315 | /* we need to mind the EDID between detect |
| 316 | and get modes due to analog/digital/tvencoder */ |
| 317 | struct edid *edid; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 318 | void *con_priv; |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 319 | bool dac_load_detect; |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame^] | 320 | uint16_t connector_object_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 321 | }; |
| 322 | |
| 323 | struct radeon_framebuffer { |
| 324 | struct drm_framebuffer base; |
| 325 | struct drm_gem_object *obj; |
| 326 | }; |
| 327 | |
| 328 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
| 329 | struct radeon_i2c_bus_rec *rec, |
| 330 | const char *name); |
| 331 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
| 332 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); |
| 333 | extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); |
| 334 | |
| 335 | extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); |
| 336 | |
| 337 | extern void radeon_compute_pll(struct radeon_pll *pll, |
| 338 | uint64_t freq, |
| 339 | uint32_t *dot_clock_p, |
| 340 | uint32_t *fb_div_p, |
| 341 | uint32_t *frac_fb_div_p, |
| 342 | uint32_t *ref_div_p, |
| 343 | uint32_t *post_div_p, |
| 344 | int flags); |
| 345 | |
| 346 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
| 347 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
| 348 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
| 349 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
| 350 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
| 351 | extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); |
| 352 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 353 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 354 | |
| 355 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
| 356 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 357 | struct drm_framebuffer *old_fb); |
| 358 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
| 359 | struct drm_display_mode *mode, |
| 360 | struct drm_display_mode *adjusted_mode, |
| 361 | int x, int y, |
| 362 | struct drm_framebuffer *old_fb); |
| 363 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
| 364 | |
| 365 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 366 | struct drm_framebuffer *old_fb); |
| 367 | extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc); |
| 368 | |
| 369 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
| 370 | struct drm_file *file_priv, |
| 371 | uint32_t handle, |
| 372 | uint32_t width, |
| 373 | uint32_t height); |
| 374 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
| 375 | int x, int y); |
| 376 | |
| 377 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
| 378 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
| 379 | extern struct radeon_encoder_atom_dig * |
| 380 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 381 | bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
| 382 | struct radeon_encoder_int_tmds *tmds); |
| 383 | bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
| 384 | struct radeon_encoder_int_tmds *tmds); |
| 385 | bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
| 386 | struct radeon_encoder_int_tmds *tmds); |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 387 | extern struct radeon_encoder_primary_dac * |
| 388 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
| 389 | extern struct radeon_encoder_tv_dac * |
| 390 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 391 | extern struct radeon_encoder_lvds * |
| 392 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 393 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
| 394 | extern struct radeon_encoder_tv_dac * |
| 395 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
| 396 | extern struct radeon_encoder_primary_dac * |
| 397 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
| 398 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
| 399 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
| 400 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
| 401 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 402 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
| 403 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 404 | extern void |
| 405 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
| 406 | extern void |
| 407 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
| 408 | extern void |
| 409 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
| 410 | extern void |
| 411 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
| 412 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| 413 | u16 blue, int regno); |
Dave Airlie | b8c00ac | 2009-10-06 13:54:01 +1000 | [diff] [blame] | 414 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 415 | u16 *blue, int regno); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 416 | struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, |
| 417 | struct drm_mode_fb_cmd *mode_cmd, |
| 418 | struct drm_gem_object *obj); |
| 419 | |
| 420 | int radeonfb_probe(struct drm_device *dev); |
| 421 | |
| 422 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
| 423 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
| 424 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
| 425 | void radeon_atombios_init_crtc(struct drm_device *dev, |
| 426 | struct radeon_crtc *radeon_crtc); |
| 427 | void radeon_legacy_init_crtc(struct drm_device *dev, |
| 428 | struct radeon_crtc *radeon_crtc); |
| 429 | void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state); |
| 430 | |
| 431 | void radeon_get_clock_info(struct drm_device *dev); |
| 432 | |
| 433 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
| 434 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
| 435 | |
| 436 | void radeon_rmx_mode_fixup(struct drm_encoder *encoder, |
| 437 | struct drm_display_mode *mode, |
| 438 | struct drm_display_mode *adjusted_mode); |
| 439 | void radeon_enc_destroy(struct drm_encoder *encoder); |
| 440 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
| 441 | void radeon_combios_asic_init(struct drm_device *dev); |
| 442 | extern int radeon_static_clocks_init(struct drm_device *dev); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 443 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
| 444 | struct drm_display_mode *mode, |
| 445 | struct drm_display_mode *adjusted_mode); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 446 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 447 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 448 | /* legacy tv */ |
| 449 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, |
| 450 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, |
| 451 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); |
| 452 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, |
| 453 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, |
| 454 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); |
| 455 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, |
| 456 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, |
| 457 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); |
| 458 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, |
| 459 | struct drm_display_mode *mode, |
| 460 | struct drm_display_mode *adjusted_mode); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 461 | #endif |