blob: 2a4ee6302122f8942ac08f6d26dbdf2f369f4e6e [file] [log] [blame]
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -07001
2PAT (Page Attribute Table)
3
4x86 Page Attribute Table (PAT) allows for setting the memory attribute at the
5page level granularity. PAT is complementary to the MTRR settings which allows
6for setting of memory types over physical address ranges. However, PAT is
7more flexible than MTRR due to its capability to set attributes at page level
8and also due to the fact that there are no hardware limitations on number of
9such attribute settings allowed. Added flexibility comes with guidelines for
10not having memory type aliasing for the same physical memory with multiple
11virtual addresses.
12
13PAT allows for different types of memory attributes. The most commonly used
14ones that will be supported at this time are Write-back, Uncached,
Toshi Kanid8382702015-06-04 18:55:15 +020015Write-combined, Write-through and Uncached Minus.
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -070016
venkatesh.pallipadi@intel.com59dfc3f2008-08-20 16:45:54 -070017
18PAT APIs
19--------
20
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -070021There are many different APIs in the kernel that allows setting of memory
22attributes at the page level. In order to avoid aliasing, these interfaces
23should be used thoughtfully. Below is a table of interfaces available,
24their intended usage and their memory attribute relationships. Internally,
25these APIs use a reserve_memtype()/free_memtype() interface on the physical
26address range to avoid any aliasing.
27
28
29-------------------------------------------------------------------
30API | RAM | ACPI,... | Reserved/Holes |
31-----------------------|----------|------------|------------------|
32 | | | |
venkatesh.pallipadi@intel.com59dfc3f2008-08-20 16:45:54 -070033ioremap | -- | UC- | UC- |
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -070034 | | | |
35ioremap_cache | -- | WB | WB |
36 | | | |
Luis R. Rodriguez2f9e8972015-05-26 10:28:12 +020037ioremap_uc | -- | UC | UC |
38 | | | |
venkatesh.pallipadi@intel.com59dfc3f2008-08-20 16:45:54 -070039ioremap_nocache | -- | UC- | UC- |
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -070040 | | | |
41ioremap_wc | -- | -- | WC |
42 | | | |
Toshi Kanid8382702015-06-04 18:55:15 +020043ioremap_wt | -- | -- | WT |
44 | | | |
venkatesh.pallipadi@intel.com59dfc3f2008-08-20 16:45:54 -070045set_memory_uc | UC- | -- | -- |
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -070046 set_memory_wb | | | |
47 | | | |
48set_memory_wc | WC | -- | -- |
49 set_memory_wb | | | |
50 | | | |
Toshi Kani623dffb2015-06-04 18:55:20 +020051set_memory_wt | WT | -- | -- |
52 set_memory_wb | | | |
53 | | | |
venkatesh.pallipadi@intel.com59dfc3f2008-08-20 16:45:54 -070054pci sysfs resource | -- | -- | UC- |
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -070055 | | | |
56pci sysfs resource_wc | -- | -- | WC |
57 is IORESOURCE_PREFETCH| | | |
58 | | | |
venkatesh.pallipadi@intel.com59dfc3f2008-08-20 16:45:54 -070059pci proc | -- | -- | UC- |
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -070060 !PCIIOC_WRITE_COMBINE | | | |
61 | | | |
62pci proc | -- | -- | WC |
63 PCIIOC_WRITE_COMBINE | | | |
64 | | | |
venkatesh.pallipadi@intel.com59dfc3f2008-08-20 16:45:54 -070065/dev/mem | -- | WB/WC/UC- | WB/WC/UC- |
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -070066 read-write | | | |
67 | | | |
venkatesh.pallipadi@intel.com59dfc3f2008-08-20 16:45:54 -070068/dev/mem | -- | UC- | UC- |
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -070069 mmap SYNC flag | | | |
70 | | | |
venkatesh.pallipadi@intel.com59dfc3f2008-08-20 16:45:54 -070071/dev/mem | -- | WB/WC/UC- | WB/WC/UC- |
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -070072 mmap !SYNC flag | |(from exist-| (from exist- |
73 and | | ing alias)| ing alias) |
74 any alias to this area| | | |
75 | | | |
76/dev/mem | -- | WB | WB |
77 mmap !SYNC flag | | | |
78 no alias to this area | | | |
79 and | | | |
80 MTRR says WB | | | |
81 | | | |
venkatesh.pallipadi@intel.com59dfc3f2008-08-20 16:45:54 -070082/dev/mem | -- | -- | UC- |
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -070083 mmap !SYNC flag | | | |
84 no alias to this area | | | |
85 and | | | |
86 MTRR says !WB | | | |
87 | | | |
88-------------------------------------------------------------------
89
venkatesh.pallipadi@intel.coma2ced6e2008-12-18 11:41:33 -080090Advanced APIs for drivers
91-------------------------
venkatesh.pallipadi@intel.com67bac792008-12-19 13:47:30 -080092A. Exporting pages to users with remap_pfn_range, io_remap_pfn_range,
venkatesh.pallipadi@intel.coma2ced6e2008-12-18 11:41:33 -080093vm_insert_pfn
94
venkatesh.pallipadi@intel.com67bac792008-12-19 13:47:30 -080095Drivers wanting to export some pages to userspace do it by using mmap
venkatesh.pallipadi@intel.coma2ced6e2008-12-18 11:41:33 -080096interface and a combination of
971) pgprot_noncached()
982) io_remap_pfn_range() or remap_pfn_range() or vm_insert_pfn()
99
venkatesh.pallipadi@intel.com67bac792008-12-19 13:47:30 -0800100With PAT support, a new API pgprot_writecombine is being added. So, drivers can
venkatesh.pallipadi@intel.coma2ced6e2008-12-18 11:41:33 -0800101continue to use the above sequence, with either pgprot_noncached() or
102pgprot_writecombine() in step 1, followed by step 2.
103
104In addition, step 2 internally tracks the region as UC or WC in memtype
105list in order to ensure no conflicting mapping.
106
venkatesh.pallipadi@intel.com67bac792008-12-19 13:47:30 -0800107Note that this set of APIs only works with IO (non RAM) regions. If driver
108wants to export a RAM region, it has to do set_memory_uc() or set_memory_wc()
venkatesh.pallipadi@intel.coma2ced6e2008-12-18 11:41:33 -0800109as step 0 above and also track the usage of those pages and use set_memory_wb()
110before the page is freed to free pool.
111
Luis R. Rodriguez2f9e8972015-05-26 10:28:12 +0200112MTRR effects on PAT / non-PAT systems
113-------------------------------------
venkatesh.pallipadi@intel.coma2ced6e2008-12-18 11:41:33 -0800114
Luis R. Rodriguez2f9e8972015-05-26 10:28:12 +0200115The following table provides the effects of using write-combining MTRRs when
116using ioremap*() calls on x86 for both non-PAT and PAT systems. Ideally
117mtrr_add() usage will be phased out in favor of arch_phys_wc_add() which will
118be a no-op on PAT enabled systems. The region over which a arch_phys_wc_add()
119is made, should already have been ioremapped with WC attributes or PAT entries,
120this can be done by using ioremap_wc() / set_memory_wc(). Devices which
121combine areas of IO memory desired to remain uncacheable with areas where
122write-combining is desirable should consider use of ioremap_uc() followed by
123set_memory_wc() to white-list effective write-combined areas. Such use is
124nevertheless discouraged as the effective memory type is considered
125implementation defined, yet this strategy can be used as last resort on devices
126with size-constrained regions where otherwise MTRR write-combining would
127otherwise not be effective.
128
129----------------------------------------------------------------------
130MTRR Non-PAT PAT Linux ioremap value Effective memory type
131----------------------------------------------------------------------
132 Non-PAT | PAT
133 PAT
134 |PCD
135 ||PWT
136 |||
137WC 000 WB _PAGE_CACHE_MODE_WB WC | WC
138WC 001 WC _PAGE_CACHE_MODE_WC WC* | WC
139WC 010 UC- _PAGE_CACHE_MODE_UC_MINUS WC* | UC
140WC 011 UC _PAGE_CACHE_MODE_UC UC | UC
141----------------------------------------------------------------------
142
143(*) denotes implementation defined and is discouraged
venkatesh.pallipadi@intel.coma2ced6e2008-12-18 11:41:33 -0800144
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -0700145Notes:
146
147-- in the above table mean "Not suggested usage for the API". Some of the --'s
148are strictly enforced by the kernel. Some others are not really enforced
149today, but may be enforced in future.
150
151For ioremap and pci access through /sys or /proc - The actual type returned
152can be more restrictive, in case of any existing aliasing for that address.
153For example: If there is an existing uncached mapping, a new ioremap_wc can
154return uncached mapping in place of write-combine requested.
155
Toshi Kani623dffb2015-06-04 18:55:20 +0200156set_memory_[uc|wc|wt] and set_memory_wb should be used in pairs, where driver
157will first make a region uc, wc or wt and switch it back to wb after use.
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -0700158
159Over time writes to /proc/mtrr will be deprecated in favor of using PAT based
160interfaces. Users writing to /proc/mtrr are suggested to use above interfaces.
161
162Drivers should use ioremap_[uc|wc] to access PCI BARs with [uc|wc] access
163types.
164
Toshi Kani623dffb2015-06-04 18:55:20 +0200165Drivers should use set_memory_[uc|wc|wt] to set access type for RAM ranges.
venkatesh.pallipadi@intel.comd27554d2008-03-18 17:00:13 -0700166
venkatesh.pallipadi@intel.com59dfc3f2008-08-20 16:45:54 -0700167
168PAT debugging
169-------------
170
171With CONFIG_DEBUG_FS enabled, PAT memtype list can be examined by
172
173# mount -t debugfs debugfs /sys/kernel/debug
174# cat /sys/kernel/debug/x86/pat_memtype_list
175PAT memtype list:
176uncached-minus @ 0x7fadf000-0x7fae0000
177uncached-minus @ 0x7fb19000-0x7fb1a000
178uncached-minus @ 0x7fb1a000-0x7fb1b000
179uncached-minus @ 0x7fb1b000-0x7fb1c000
180uncached-minus @ 0x7fb1c000-0x7fb1d000
181uncached-minus @ 0x7fb1d000-0x7fb1e000
182uncached-minus @ 0x7fb1e000-0x7fb25000
183uncached-minus @ 0x7fb25000-0x7fb26000
184uncached-minus @ 0x7fb26000-0x7fb27000
185uncached-minus @ 0x7fb27000-0x7fb28000
186uncached-minus @ 0x7fb28000-0x7fb2e000
187uncached-minus @ 0x7fb2e000-0x7fb2f000
188uncached-minus @ 0x7fb2f000-0x7fb30000
189uncached-minus @ 0x7fb31000-0x7fb32000
190uncached-minus @ 0x80000000-0x90000000
191
192This list shows physical address ranges and various PAT settings used to
193access those physical address ranges.
194
195Another, more verbose way of getting PAT related debug messages is with
196"debugpat" boot parameter. With this parameter, various debug messages are
197printed to dmesg log.
198
Toshi Kanib6350c22016-03-23 15:42:03 -0600199PAT Initialization
200------------------
201
202The following table describes how PAT is initialized under various
203configurations. The PAT MSR must be updated by Linux in order to support WC
204and WT attributes. Otherwise, the PAT MSR has the value programmed in it
205by the firmware. Note, Xen enables WC attribute in the PAT MSR for guests.
206
207 MTRR PAT Call Sequence PAT State PAT MSR
208 =========================================================
209 E E MTRR -> PAT init Enabled OS
210 E D MTRR -> PAT init Disabled -
211 D E MTRR -> PAT disable Disabled BIOS
212 D D MTRR -> PAT disable Disabled -
213 - np/E PAT -> PAT disable Disabled BIOS
214 - np/D PAT -> PAT disable Disabled -
215 E !P/E MTRR -> PAT init Disabled BIOS
216 D !P/E MTRR -> PAT disable Disabled BIOS
217 !M !P/E MTRR stub -> PAT disable Disabled BIOS
218
219 Legend
220 ------------------------------------------------
221 E Feature enabled in CPU
222 D Feature disabled/unsupported in CPU
223 np "nopat" boot option specified
224 !P CONFIG_X86_PAT option unset
225 !M CONFIG_MTRR option unset
226 Enabled PAT state set to enabled
227 Disabled PAT state set to disabled
228 OS PAT initializes PAT MSR with OS setting
229 BIOS PAT keeps PAT MSR with BIOS setting
230