Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/include/linux/clk-provider.h |
| 3 | * |
| 4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> |
| 5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | #ifndef __LINUX_CLK_PROVIDER_H |
| 12 | #define __LINUX_CLK_PROVIDER_H |
| 13 | |
| 14 | #include <linux/clk.h> |
Gerhard Sittig | aa514ce | 2013-07-22 14:14:40 +0200 | [diff] [blame] | 15 | #include <linux/io.h> |
Maxime Ripard | 355bb16 | 2014-08-30 21:18:00 +0200 | [diff] [blame] | 16 | #include <linux/of.h> |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 17 | |
| 18 | #ifdef CONFIG_COMMON_CLK |
| 19 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 20 | /* |
| 21 | * flags used across common struct clk. these flags should only affect the |
| 22 | * top-level framework. custom flags for dealing with hardware specifics |
| 23 | * belong in struct clk_foo |
| 24 | */ |
| 25 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ |
| 26 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ |
| 27 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ |
| 28 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ |
| 29 | #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ |
Rajendra Nayak | f7d8caa | 2012-06-01 14:02:47 +0530 | [diff] [blame] | 30 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
Ulf Hansson | a093bde | 2012-08-31 14:21:28 +0200 | [diff] [blame] | 31 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 32 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
Boris BREZILLON | 5279fc4 | 2013-12-21 10:34:47 +0100 | [diff] [blame] | 33 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 34 | |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 35 | struct clk_hw; |
Tomeu Vizoso | 035a61c | 2015-01-23 12:03:30 +0100 | [diff] [blame] | 36 | struct clk_core; |
Alex Elder | c646cbf | 2014-03-21 06:43:56 -0500 | [diff] [blame] | 37 | struct dentry; |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 38 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 39 | /** |
| 40 | * struct clk_ops - Callback operations for hardware clocks; these are to |
| 41 | * be provided by the clock implementation, and will be called by drivers |
| 42 | * through the clk_* api. |
| 43 | * |
| 44 | * @prepare: Prepare the clock for enabling. This must not return until |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 45 | * the clock is fully prepared, and it's safe to call clk_enable. |
| 46 | * This callback is intended to allow clock implementations to |
| 47 | * do any initialisation that may sleep. Called with |
| 48 | * prepare_lock held. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 49 | * |
| 50 | * @unprepare: Release the clock from its prepared state. This will typically |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 51 | * undo any work done in the @prepare callback. Called with |
| 52 | * prepare_lock held. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 53 | * |
Ulf Hansson | 3d6ee28 | 2013-03-12 20:26:02 +0100 | [diff] [blame] | 54 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
| 55 | * This function is allowed to sleep. Optional, if this op is not |
| 56 | * set then the prepare count will be used. |
| 57 | * |
Ulf Hansson | 3cc8247 | 2013-03-12 20:26:04 +0100 | [diff] [blame] | 58 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
| 59 | * clk_disable_unused for prepare clocks with special needs. |
| 60 | * Called with prepare mutex held. This function may sleep. |
| 61 | * |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 62 | * @enable: Enable the clock atomically. This must not return until the |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 63 | * clock is generating a valid clock signal, usable by consumer |
| 64 | * devices. Called with enable_lock held. This function must not |
| 65 | * sleep. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 66 | * |
| 67 | * @disable: Disable the clock atomically. Called with enable_lock held. |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 68 | * This function must not sleep. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 69 | * |
Stephen Boyd | 119c712 | 2012-10-03 23:38:53 -0700 | [diff] [blame] | 70 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 71 | * This function must not sleep. Optional, if this op is not |
| 72 | * set then the enable count will be used. |
Stephen Boyd | 119c712 | 2012-10-03 23:38:53 -0700 | [diff] [blame] | 73 | * |
Mike Turquette | 7c045a5 | 2012-12-04 11:00:35 -0800 | [diff] [blame] | 74 | * @disable_unused: Disable the clock atomically. Only called from |
| 75 | * clk_disable_unused for gate clocks with special needs. |
| 76 | * Called with enable_lock held. This function must not |
| 77 | * sleep. |
| 78 | * |
Stephen Boyd | 7ce3e8c | 2012-10-03 23:38:54 -0700 | [diff] [blame] | 79 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 80 | * parent rate is an input parameter. It is up to the caller to |
| 81 | * ensure that the prepare_mutex is held across this call. |
| 82 | * Returns the calculated rate. Optional, but recommended - if |
| 83 | * this op is not set then clock rate will be initialized to 0. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 84 | * |
| 85 | * @round_rate: Given a target rate as input, returns the closest rate actually |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 86 | * supported by the clock. The parent rate is an input/output |
| 87 | * parameter. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 88 | * |
James Hogan | 71472c0 | 2013-07-29 12:25:00 +0100 | [diff] [blame] | 89 | * @determine_rate: Given a target rate as input, returns the closest rate |
| 90 | * actually supported by the clock, and optionally the parent clock |
| 91 | * that should be used to provide the clock rate. |
| 92 | * |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 93 | * @set_parent: Change the input source of this clock; for clocks with multiple |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 94 | * possible parents specify a new parent by passing in the index |
| 95 | * as a u8 corresponding to the parent in either the .parent_names |
| 96 | * or .parents arrays. This function in affect translates an |
| 97 | * array index into the value programmed into the hardware. |
| 98 | * Returns 0 on success, -EERROR otherwise. |
| 99 | * |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 100 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 101 | * return value is a u8 which specifies the index corresponding to |
| 102 | * the parent clock. This index can be applied to either the |
| 103 | * .parent_names or .parents arrays. In short, this function |
| 104 | * translates the parent value read from hardware into an array |
| 105 | * index. Currently only called when the clock is initialized by |
| 106 | * __clk_init. This callback is mandatory for clocks with |
| 107 | * multiple parents. It is optional (and unnecessary) for clocks |
| 108 | * with 0 or 1 parents. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 109 | * |
Shawn Guo | 1c0035d | 2012-04-12 20:50:18 +0800 | [diff] [blame] | 110 | * @set_rate: Change the rate of this clock. The requested rate is specified |
| 111 | * by the second argument, which should typically be the return |
| 112 | * of .round_rate call. The third argument gives the parent rate |
| 113 | * which is likely helpful for most .set_rate implementation. |
| 114 | * Returns 0 on success, -EERROR otherwise. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 115 | * |
Stephen Boyd | 3fa2252 | 2014-01-15 10:47:22 -0800 | [diff] [blame] | 116 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
| 117 | * requested rate is specified by the second argument, which |
| 118 | * should typically be the return of .round_rate call. The |
| 119 | * third argument gives the parent rate which is likely helpful |
| 120 | * for most .set_rate_and_parent implementation. The fourth |
| 121 | * argument gives the parent index. This callback is optional (and |
| 122 | * unnecessary) for clocks with 0 or 1 parents as well as |
| 123 | * for clocks that can tolerate switching the rate and the parent |
| 124 | * separately via calls to .set_parent and .set_rate. |
| 125 | * Returns 0 on success, -EERROR otherwise. |
| 126 | * |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 127 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
| 128 | * is expressed in ppb (parts per billion). The parent accuracy is |
| 129 | * an input parameter. |
| 130 | * Returns the calculated accuracy. Optional - if this op is not |
| 131 | * set then clock accuracy will be initialized to parent accuracy |
| 132 | * or 0 (perfect clock) if clock has no parent. |
| 133 | * |
Maxime Ripard | 9824cf7 | 2014-07-14 13:53:27 +0200 | [diff] [blame] | 134 | * @get_phase: Queries the hardware to get the current phase of a clock. |
| 135 | * Returned values are 0-359 degrees on success, negative |
| 136 | * error codes on failure. |
| 137 | * |
Mike Turquette | e59c537 | 2014-02-18 21:21:25 -0800 | [diff] [blame] | 138 | * @set_phase: Shift the phase this clock signal in degrees specified |
| 139 | * by the second argument. Valid values for degrees are |
| 140 | * 0-359. Return 0 on success, otherwise -EERROR. |
| 141 | * |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 142 | * @init: Perform platform-specific initialization magic. |
| 143 | * This is not not used by any of the basic clock types. |
| 144 | * Please consider other ways of solving initialization problems |
| 145 | * before using this callback, as its use is discouraged. |
| 146 | * |
Alex Elder | c646cbf | 2014-03-21 06:43:56 -0500 | [diff] [blame] | 147 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
| 148 | * is called once, after the debugfs directory entry for this |
| 149 | * clock has been created. The dentry pointer representing that |
| 150 | * directory is provided as an argument. Called with |
| 151 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. |
| 152 | * |
Stephen Boyd | 3fa2252 | 2014-01-15 10:47:22 -0800 | [diff] [blame] | 153 | * |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 154 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
| 155 | * implementations to split any work between atomic (enable) and sleepable |
| 156 | * (prepare) contexts. If enabling a clock requires code that might sleep, |
| 157 | * this must be done in clk_prepare. Clock enable code that will never be |
Stephen Boyd | 7ce3e8c | 2012-10-03 23:38:54 -0700 | [diff] [blame] | 158 | * called in a sleepable context may be implemented in clk_enable. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 159 | * |
| 160 | * Typically, drivers will call clk_prepare when a clock may be needed later |
| 161 | * (eg. when a device is opened), and clk_enable when the clock is actually |
| 162 | * required (eg. from an interrupt). Note that clk_prepare MUST have been |
| 163 | * called before clk_enable. |
| 164 | */ |
| 165 | struct clk_ops { |
| 166 | int (*prepare)(struct clk_hw *hw); |
| 167 | void (*unprepare)(struct clk_hw *hw); |
Ulf Hansson | 3d6ee28 | 2013-03-12 20:26:02 +0100 | [diff] [blame] | 168 | int (*is_prepared)(struct clk_hw *hw); |
Ulf Hansson | 3cc8247 | 2013-03-12 20:26:04 +0100 | [diff] [blame] | 169 | void (*unprepare_unused)(struct clk_hw *hw); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 170 | int (*enable)(struct clk_hw *hw); |
| 171 | void (*disable)(struct clk_hw *hw); |
| 172 | int (*is_enabled)(struct clk_hw *hw); |
Mike Turquette | 7c045a5 | 2012-12-04 11:00:35 -0800 | [diff] [blame] | 173 | void (*disable_unused)(struct clk_hw *hw); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 174 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
| 175 | unsigned long parent_rate); |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 176 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
| 177 | unsigned long *parent_rate); |
Tomeu Vizoso | 1c8e600 | 2015-01-23 12:03:31 +0100 | [diff] [blame] | 178 | long (*determine_rate)(struct clk_hw *hw, |
| 179 | unsigned long rate, |
| 180 | unsigned long min_rate, |
| 181 | unsigned long max_rate, |
| 182 | unsigned long *best_parent_rate, |
| 183 | struct clk_hw **best_parent_hw); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 184 | int (*set_parent)(struct clk_hw *hw, u8 index); |
| 185 | u8 (*get_parent)(struct clk_hw *hw); |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 186 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
| 187 | unsigned long parent_rate); |
Stephen Boyd | 3fa2252 | 2014-01-15 10:47:22 -0800 | [diff] [blame] | 188 | int (*set_rate_and_parent)(struct clk_hw *hw, |
| 189 | unsigned long rate, |
| 190 | unsigned long parent_rate, u8 index); |
Boris BREZILLON | 5279fc4 | 2013-12-21 10:34:47 +0100 | [diff] [blame] | 191 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
| 192 | unsigned long parent_accuracy); |
Maxime Ripard | 9824cf7 | 2014-07-14 13:53:27 +0200 | [diff] [blame] | 193 | int (*get_phase)(struct clk_hw *hw); |
Mike Turquette | e59c537 | 2014-02-18 21:21:25 -0800 | [diff] [blame] | 194 | int (*set_phase)(struct clk_hw *hw, int degrees); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 195 | void (*init)(struct clk_hw *hw); |
Alex Elder | c646cbf | 2014-03-21 06:43:56 -0500 | [diff] [blame] | 196 | int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 197 | }; |
| 198 | |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 199 | /** |
| 200 | * struct clk_init_data - holds init data that's common to all clocks and is |
| 201 | * shared between the clock provider and the common clock framework. |
| 202 | * |
| 203 | * @name: clock name |
| 204 | * @ops: operations this clock supports |
| 205 | * @parent_names: array of string names for all possible parents |
| 206 | * @num_parents: number of possible parents |
| 207 | * @flags: framework-level hints and quirks |
| 208 | */ |
| 209 | struct clk_init_data { |
| 210 | const char *name; |
| 211 | const struct clk_ops *ops; |
| 212 | const char **parent_names; |
| 213 | u8 num_parents; |
| 214 | unsigned long flags; |
| 215 | }; |
| 216 | |
| 217 | /** |
| 218 | * struct clk_hw - handle for traversing from a struct clk to its corresponding |
| 219 | * hardware-specific structure. struct clk_hw should be declared within struct |
| 220 | * clk_foo and then referenced by the struct clk instance that uses struct |
| 221 | * clk_foo's clk_ops |
| 222 | * |
Tomeu Vizoso | 035a61c | 2015-01-23 12:03:30 +0100 | [diff] [blame] | 223 | * @core: pointer to the struct clk_core instance that points back to this |
| 224 | * struct clk_hw instance |
| 225 | * |
| 226 | * @clk: pointer to the per-user struct clk instance that can be used to call |
| 227 | * into the clk API |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 228 | * |
| 229 | * @init: pointer to struct clk_init_data that contains the init data shared |
| 230 | * with the common clock framework. |
| 231 | */ |
| 232 | struct clk_hw { |
Tomeu Vizoso | 035a61c | 2015-01-23 12:03:30 +0100 | [diff] [blame] | 233 | struct clk_core *core; |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 234 | struct clk *clk; |
Mark Brown | dc4cd94 | 2012-05-14 15:12:42 +0100 | [diff] [blame] | 235 | const struct clk_init_data *init; |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 236 | }; |
| 237 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 238 | /* |
| 239 | * DOC: Basic clock implementations common to many platforms |
| 240 | * |
| 241 | * Each basic clock hardware type is comprised of a structure describing the |
| 242 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, |
| 243 | * unique flags for that hardware type, a registration function and an |
| 244 | * alternative macro for static initialization |
| 245 | */ |
| 246 | |
| 247 | /** |
| 248 | * struct clk_fixed_rate - fixed-rate clock |
| 249 | * @hw: handle between common and hardware-specific interfaces |
| 250 | * @fixed_rate: constant frequency of clock |
| 251 | */ |
| 252 | struct clk_fixed_rate { |
| 253 | struct clk_hw hw; |
| 254 | unsigned long fixed_rate; |
Boris BREZILLON | 0903ea6 | 2013-12-21 10:34:48 +0100 | [diff] [blame] | 255 | unsigned long fixed_accuracy; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 256 | u8 flags; |
| 257 | }; |
| 258 | |
Shawn Guo | bffad66 | 2012-03-27 15:23:23 +0800 | [diff] [blame] | 259 | extern const struct clk_ops clk_fixed_rate_ops; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 260 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
| 261 | const char *parent_name, unsigned long flags, |
| 262 | unsigned long fixed_rate); |
Boris BREZILLON | 0903ea6 | 2013-12-21 10:34:48 +0100 | [diff] [blame] | 263 | struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, |
| 264 | const char *name, const char *parent_name, unsigned long flags, |
| 265 | unsigned long fixed_rate, unsigned long fixed_accuracy); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 266 | |
Grant Likely | 015ba40 | 2012-04-07 21:39:39 -0500 | [diff] [blame] | 267 | void of_fixed_clk_setup(struct device_node *np); |
| 268 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 269 | /** |
| 270 | * struct clk_gate - gating clock |
| 271 | * |
| 272 | * @hw: handle between common and hardware-specific interfaces |
| 273 | * @reg: register controlling gate |
| 274 | * @bit_idx: single bit controlling gate |
| 275 | * @flags: hardware-specific flags |
| 276 | * @lock: register lock |
| 277 | * |
| 278 | * Clock which can gate its output. Implements .enable & .disable |
| 279 | * |
| 280 | * Flags: |
Viresh Kumar | 1f73f31 | 2012-04-17 16:45:35 +0530 | [diff] [blame] | 281 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 282 | * enable the clock. Setting this flag does the opposite: setting the bit |
| 283 | * disable the clock and clearing it enables the clock |
Haojian Zhuang | 0457799 | 2013-06-08 22:47:19 +0800 | [diff] [blame] | 284 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 285 | * of this register, and mask of gate bits are in higher 16-bit of this |
| 286 | * register. While setting the gate bits, higher 16-bit should also be |
| 287 | * updated to indicate changing gate bits. |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 288 | */ |
| 289 | struct clk_gate { |
| 290 | struct clk_hw hw; |
| 291 | void __iomem *reg; |
| 292 | u8 bit_idx; |
| 293 | u8 flags; |
| 294 | spinlock_t *lock; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 295 | }; |
| 296 | |
| 297 | #define CLK_GATE_SET_TO_DISABLE BIT(0) |
Haojian Zhuang | 0457799 | 2013-06-08 22:47:19 +0800 | [diff] [blame] | 298 | #define CLK_GATE_HIWORD_MASK BIT(1) |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 299 | |
Shawn Guo | bffad66 | 2012-03-27 15:23:23 +0800 | [diff] [blame] | 300 | extern const struct clk_ops clk_gate_ops; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 301 | struct clk *clk_register_gate(struct device *dev, const char *name, |
| 302 | const char *parent_name, unsigned long flags, |
| 303 | void __iomem *reg, u8 bit_idx, |
| 304 | u8 clk_gate_flags, spinlock_t *lock); |
Krzysztof Kozlowski | 4e3c021 | 2015-01-05 10:52:40 +0100 | [diff] [blame] | 305 | void clk_unregister_gate(struct clk *clk); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 306 | |
Rajendra Nayak | 357c3f0 | 2012-06-29 19:06:32 +0530 | [diff] [blame] | 307 | struct clk_div_table { |
| 308 | unsigned int val; |
| 309 | unsigned int div; |
| 310 | }; |
| 311 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 312 | /** |
| 313 | * struct clk_divider - adjustable divider clock |
| 314 | * |
| 315 | * @hw: handle between common and hardware-specific interfaces |
| 316 | * @reg: register containing the divider |
| 317 | * @shift: shift to the divider bit field |
| 318 | * @width: width of the divider bit field |
Rajendra Nayak | 357c3f0 | 2012-06-29 19:06:32 +0530 | [diff] [blame] | 319 | * @table: array of value/divider pairs, last entry should have div = 0 |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 320 | * @lock: register lock |
| 321 | * |
| 322 | * Clock with an adjustable divider affecting its output frequency. Implements |
| 323 | * .recalc_rate, .set_rate and .round_rate |
| 324 | * |
| 325 | * Flags: |
| 326 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 327 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
| 328 | * the raw value read from the register, with the value of zero considered |
Soren Brinkmann | 056b2053 | 2013-04-02 15:36:56 -0700 | [diff] [blame] | 329 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 330 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 331 | * the hardware register |
Soren Brinkmann | 056b2053 | 2013-04-02 15:36:56 -0700 | [diff] [blame] | 332 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
| 333 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. |
| 334 | * Some hardware implementations gracefully handle this case and allow a |
| 335 | * zero divisor by not modifying their input clock |
| 336 | * (divide by one / bypass). |
Haojian Zhuang | d57dfe7 | 2013-06-08 22:47:18 +0800 | [diff] [blame] | 337 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 338 | * of this register, and mask of divider bits are in higher 16-bit of this |
| 339 | * register. While setting the divider bits, higher 16-bit should also be |
| 340 | * updated to indicate changing divider bits. |
Maxime COQUELIN | 774b514 | 2014-01-29 17:24:07 +0100 | [diff] [blame] | 341 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
| 342 | * to the closest integer instead of the up one. |
Heiko Stuebner | 79c6ab5 | 2014-05-23 18:32:15 +0530 | [diff] [blame] | 343 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
| 344 | * not be changed by the clock framework. |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 345 | */ |
| 346 | struct clk_divider { |
| 347 | struct clk_hw hw; |
| 348 | void __iomem *reg; |
| 349 | u8 shift; |
| 350 | u8 width; |
| 351 | u8 flags; |
Rajendra Nayak | 357c3f0 | 2012-06-29 19:06:32 +0530 | [diff] [blame] | 352 | const struct clk_div_table *table; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 353 | spinlock_t *lock; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 354 | }; |
| 355 | |
| 356 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
| 357 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) |
Soren Brinkmann | 056b2053 | 2013-04-02 15:36:56 -0700 | [diff] [blame] | 358 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
Haojian Zhuang | d57dfe7 | 2013-06-08 22:47:18 +0800 | [diff] [blame] | 359 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
Maxime COQUELIN | 774b514 | 2014-01-29 17:24:07 +0100 | [diff] [blame] | 360 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
Heiko Stuebner | 79c6ab5 | 2014-05-23 18:32:15 +0530 | [diff] [blame] | 361 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 362 | |
Shawn Guo | bffad66 | 2012-03-27 15:23:23 +0800 | [diff] [blame] | 363 | extern const struct clk_ops clk_divider_ops; |
Stephen Boyd | bca9690 | 2015-01-19 18:05:29 -0800 | [diff] [blame] | 364 | |
| 365 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, |
| 366 | unsigned int val, const struct clk_div_table *table, |
| 367 | unsigned long flags); |
| 368 | long divider_round_rate(struct clk_hw *hw, unsigned long rate, |
| 369 | unsigned long *prate, const struct clk_div_table *table, |
| 370 | u8 width, unsigned long flags); |
| 371 | int divider_get_val(unsigned long rate, unsigned long parent_rate, |
| 372 | const struct clk_div_table *table, u8 width, |
| 373 | unsigned long flags); |
| 374 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 375 | struct clk *clk_register_divider(struct device *dev, const char *name, |
| 376 | const char *parent_name, unsigned long flags, |
| 377 | void __iomem *reg, u8 shift, u8 width, |
| 378 | u8 clk_divider_flags, spinlock_t *lock); |
Rajendra Nayak | 357c3f0 | 2012-06-29 19:06:32 +0530 | [diff] [blame] | 379 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
| 380 | const char *parent_name, unsigned long flags, |
| 381 | void __iomem *reg, u8 shift, u8 width, |
| 382 | u8 clk_divider_flags, const struct clk_div_table *table, |
| 383 | spinlock_t *lock); |
Krzysztof Kozlowski | 4e3c021 | 2015-01-05 10:52:40 +0100 | [diff] [blame] | 384 | void clk_unregister_divider(struct clk *clk); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 385 | |
| 386 | /** |
| 387 | * struct clk_mux - multiplexer clock |
| 388 | * |
| 389 | * @hw: handle between common and hardware-specific interfaces |
| 390 | * @reg: register controlling multiplexer |
| 391 | * @shift: shift to multiplexer bit field |
| 392 | * @width: width of mutliplexer bit field |
James Hogan | 3566d40 | 2013-03-25 14:35:07 +0000 | [diff] [blame] | 393 | * @flags: hardware-specific flags |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 394 | * @lock: register lock |
| 395 | * |
| 396 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent |
| 397 | * and .recalc_rate |
| 398 | * |
| 399 | * Flags: |
| 400 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 |
Viresh Kumar | 1f73f31 | 2012-04-17 16:45:35 +0530 | [diff] [blame] | 401 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
Haojian Zhuang | ba492e9 | 2013-06-08 22:47:17 +0800 | [diff] [blame] | 402 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 403 | * register, and mask of mux bits are in higher 16-bit of this register. |
| 404 | * While setting the mux bits, higher 16-bit should also be updated to |
| 405 | * indicate changing mux bits. |
Stephen Boyd | 15a02c1 | 2015-01-19 18:05:28 -0800 | [diff] [blame] | 406 | * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired |
| 407 | * frequency. |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 408 | */ |
| 409 | struct clk_mux { |
| 410 | struct clk_hw hw; |
| 411 | void __iomem *reg; |
Peter De Schrijver | ce4f331 | 2013-03-22 14:07:53 +0200 | [diff] [blame] | 412 | u32 *table; |
| 413 | u32 mask; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 414 | u8 shift; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 415 | u8 flags; |
| 416 | spinlock_t *lock; |
| 417 | }; |
| 418 | |
| 419 | #define CLK_MUX_INDEX_ONE BIT(0) |
| 420 | #define CLK_MUX_INDEX_BIT BIT(1) |
Haojian Zhuang | ba492e9 | 2013-06-08 22:47:17 +0800 | [diff] [blame] | 421 | #define CLK_MUX_HIWORD_MASK BIT(2) |
Stephen Boyd | 15a02c1 | 2015-01-19 18:05:28 -0800 | [diff] [blame] | 422 | #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ |
| 423 | #define CLK_MUX_ROUND_CLOSEST BIT(4) |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 424 | |
Shawn Guo | bffad66 | 2012-03-27 15:23:23 +0800 | [diff] [blame] | 425 | extern const struct clk_ops clk_mux_ops; |
Tomasz Figa | c57acd1 | 2013-07-23 01:49:18 +0200 | [diff] [blame] | 426 | extern const struct clk_ops clk_mux_ro_ops; |
Peter De Schrijver | ce4f331 | 2013-03-22 14:07:53 +0200 | [diff] [blame] | 427 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 428 | struct clk *clk_register_mux(struct device *dev, const char *name, |
Mark Brown | d305fb7 | 2012-03-21 20:01:20 +0000 | [diff] [blame] | 429 | const char **parent_names, u8 num_parents, unsigned long flags, |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 430 | void __iomem *reg, u8 shift, u8 width, |
| 431 | u8 clk_mux_flags, spinlock_t *lock); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 432 | |
Peter De Schrijver | ce4f331 | 2013-03-22 14:07:53 +0200 | [diff] [blame] | 433 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
| 434 | const char **parent_names, u8 num_parents, unsigned long flags, |
| 435 | void __iomem *reg, u8 shift, u32 mask, |
| 436 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); |
| 437 | |
Krzysztof Kozlowski | 4e3c021 | 2015-01-05 10:52:40 +0100 | [diff] [blame] | 438 | void clk_unregister_mux(struct clk *clk); |
| 439 | |
Gregory CLEMENT | 79b1664 | 2013-04-12 13:57:44 +0200 | [diff] [blame] | 440 | void of_fixed_factor_clk_setup(struct device_node *node); |
| 441 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 442 | /** |
Sascha Hauer | f0948f5 | 2012-05-03 15:36:14 +0530 | [diff] [blame] | 443 | * struct clk_fixed_factor - fixed multiplier and divider clock |
| 444 | * |
| 445 | * @hw: handle between common and hardware-specific interfaces |
| 446 | * @mult: multiplier |
| 447 | * @div: divider |
| 448 | * |
| 449 | * Clock with a fixed multiplier and divider. The output frequency is the |
| 450 | * parent clock rate divided by div and multiplied by mult. |
| 451 | * Implements .recalc_rate, .set_rate and .round_rate |
| 452 | */ |
| 453 | |
| 454 | struct clk_fixed_factor { |
| 455 | struct clk_hw hw; |
| 456 | unsigned int mult; |
| 457 | unsigned int div; |
| 458 | }; |
| 459 | |
| 460 | extern struct clk_ops clk_fixed_factor_ops; |
| 461 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
| 462 | const char *parent_name, unsigned long flags, |
| 463 | unsigned int mult, unsigned int div); |
| 464 | |
Heikki Krogerus | e2d0e90 | 2014-05-15 16:40:25 +0300 | [diff] [blame] | 465 | /** |
| 466 | * struct clk_fractional_divider - adjustable fractional divider clock |
| 467 | * |
| 468 | * @hw: handle between common and hardware-specific interfaces |
| 469 | * @reg: register containing the divider |
| 470 | * @mshift: shift to the numerator bit field |
| 471 | * @mwidth: width of the numerator bit field |
| 472 | * @nshift: shift to the denominator bit field |
| 473 | * @nwidth: width of the denominator bit field |
| 474 | * @lock: register lock |
| 475 | * |
| 476 | * Clock with adjustable fractional divider affecting its output frequency. |
| 477 | */ |
| 478 | |
| 479 | struct clk_fractional_divider { |
| 480 | struct clk_hw hw; |
| 481 | void __iomem *reg; |
| 482 | u8 mshift; |
| 483 | u32 mmask; |
| 484 | u8 nshift; |
| 485 | u32 nmask; |
| 486 | u8 flags; |
| 487 | spinlock_t *lock; |
| 488 | }; |
| 489 | |
| 490 | extern const struct clk_ops clk_fractional_divider_ops; |
| 491 | struct clk *clk_register_fractional_divider(struct device *dev, |
| 492 | const char *name, const char *parent_name, unsigned long flags, |
| 493 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, |
| 494 | u8 clk_divider_flags, spinlock_t *lock); |
| 495 | |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 496 | /*** |
| 497 | * struct clk_composite - aggregate clock of mux, divider and gate clocks |
| 498 | * |
| 499 | * @hw: handle between common and hardware-specific interfaces |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 500 | * @mux_hw: handle between composite and hardware-specific mux clock |
| 501 | * @rate_hw: handle between composite and hardware-specific rate clock |
| 502 | * @gate_hw: handle between composite and hardware-specific gate clock |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 503 | * @mux_ops: clock ops for mux |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 504 | * @rate_ops: clock ops for rate |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 505 | * @gate_ops: clock ops for gate |
| 506 | */ |
| 507 | struct clk_composite { |
| 508 | struct clk_hw hw; |
| 509 | struct clk_ops ops; |
| 510 | |
| 511 | struct clk_hw *mux_hw; |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 512 | struct clk_hw *rate_hw; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 513 | struct clk_hw *gate_hw; |
| 514 | |
| 515 | const struct clk_ops *mux_ops; |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 516 | const struct clk_ops *rate_ops; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 517 | const struct clk_ops *gate_ops; |
| 518 | }; |
| 519 | |
| 520 | struct clk *clk_register_composite(struct device *dev, const char *name, |
| 521 | const char **parent_names, int num_parents, |
| 522 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 523 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 524 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
| 525 | unsigned long flags); |
| 526 | |
Jyri Sarha | c873d14 | 2014-09-05 15:21:34 +0300 | [diff] [blame] | 527 | /*** |
| 528 | * struct clk_gpio_gate - gpio gated clock |
| 529 | * |
| 530 | * @hw: handle between common and hardware-specific interfaces |
| 531 | * @gpiod: gpio descriptor |
| 532 | * |
| 533 | * Clock with a gpio control for enabling and disabling the parent clock. |
| 534 | * Implements .enable, .disable and .is_enabled |
| 535 | */ |
| 536 | |
| 537 | struct clk_gpio { |
| 538 | struct clk_hw hw; |
| 539 | struct gpio_desc *gpiod; |
| 540 | }; |
| 541 | |
| 542 | extern const struct clk_ops clk_gpio_gate_ops; |
| 543 | struct clk *clk_register_gpio_gate(struct device *dev, const char *name, |
| 544 | const char *parent_name, struct gpio_desc *gpio, |
| 545 | unsigned long flags); |
| 546 | |
| 547 | void of_gpio_clk_gate_setup(struct device_node *node); |
| 548 | |
Sascha Hauer | f0948f5 | 2012-05-03 15:36:14 +0530 | [diff] [blame] | 549 | /** |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 550 | * clk_register - allocate a new clock, register it and return an opaque cookie |
| 551 | * @dev: device that is registering this clock |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 552 | * @hw: link to hardware-specific clock data |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 553 | * |
| 554 | * clk_register is the primary interface for populating the clock tree with new |
| 555 | * clock nodes. It returns a pointer to the newly allocated struct clk which |
| 556 | * cannot be dereferenced by driver code but may be used in conjuction with the |
Mike Turquette | d1302a3 | 2012-03-29 14:30:40 -0700 | [diff] [blame] | 557 | * rest of the clock API. In the event of an error clk_register will return an |
| 558 | * error code; drivers must test for an error code after calling clk_register. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 559 | */ |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 560 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
Stephen Boyd | 46c8773 | 2012-09-24 13:38:04 -0700 | [diff] [blame] | 561 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 562 | |
Mark Brown | 1df5c93 | 2012-04-18 09:07:12 +0100 | [diff] [blame] | 563 | void clk_unregister(struct clk *clk); |
Stephen Boyd | 46c8773 | 2012-09-24 13:38:04 -0700 | [diff] [blame] | 564 | void devm_clk_unregister(struct device *dev, struct clk *clk); |
Mark Brown | 1df5c93 | 2012-04-18 09:07:12 +0100 | [diff] [blame] | 565 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 566 | /* helper functions */ |
| 567 | const char *__clk_get_name(struct clk *clk); |
| 568 | struct clk_hw *__clk_get_hw(struct clk *clk); |
| 569 | u8 __clk_get_num_parents(struct clk *clk); |
| 570 | struct clk *__clk_get_parent(struct clk *clk); |
James Hogan | 7ef3dcc | 2013-07-29 12:24:58 +0100 | [diff] [blame] | 571 | struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); |
Linus Torvalds | 9387468 | 2012-12-11 11:25:08 -0800 | [diff] [blame] | 572 | unsigned int __clk_get_enable_count(struct clk *clk); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 573 | unsigned long __clk_get_rate(struct clk *clk); |
| 574 | unsigned long __clk_get_flags(struct clk *clk); |
Ulf Hansson | 3d6ee28 | 2013-03-12 20:26:02 +0100 | [diff] [blame] | 575 | bool __clk_is_prepared(struct clk *clk); |
Stephen Boyd | 2ac6b1f | 2012-10-03 23:38:55 -0700 | [diff] [blame] | 576 | bool __clk_is_enabled(struct clk *clk); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 577 | struct clk *__clk_lookup(const char *name); |
James Hogan | e366fdd | 2013-07-29 12:25:02 +0100 | [diff] [blame] | 578 | long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, |
Tomeu Vizoso | 1c8e600 | 2015-01-23 12:03:31 +0100 | [diff] [blame] | 579 | unsigned long min_rate, |
| 580 | unsigned long max_rate, |
James Hogan | e366fdd | 2013-07-29 12:25:02 +0100 | [diff] [blame] | 581 | unsigned long *best_parent_rate, |
Tomeu Vizoso | 646cafc | 2014-12-02 08:54:22 +0100 | [diff] [blame] | 582 | struct clk_hw **best_parent_p); |
Tomeu Vizoso | 1c8e600 | 2015-01-23 12:03:31 +0100 | [diff] [blame] | 583 | unsigned long __clk_determine_rate(struct clk_hw *core, |
| 584 | unsigned long rate, |
| 585 | unsigned long min_rate, |
| 586 | unsigned long max_rate); |
Stephen Boyd | 15a02c1 | 2015-01-19 18:05:28 -0800 | [diff] [blame] | 587 | long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate, |
Tomeu Vizoso | 1c8e600 | 2015-01-23 12:03:31 +0100 | [diff] [blame] | 588 | unsigned long min_rate, |
| 589 | unsigned long max_rate, |
Stephen Boyd | 15a02c1 | 2015-01-19 18:05:28 -0800 | [diff] [blame] | 590 | unsigned long *best_parent_rate, |
| 591 | struct clk_hw **best_parent_p); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 592 | |
Javier Martinez Canillas | 2e65d8b | 2015-02-12 14:58:29 +0100 | [diff] [blame] | 593 | static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) |
| 594 | { |
| 595 | dst->clk = src->clk; |
| 596 | dst->core = src->core; |
| 597 | } |
| 598 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 599 | /* |
| 600 | * FIXME clock api without lock protection |
| 601 | */ |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 602 | unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); |
| 603 | |
Grant Likely | 766e6a4 | 2012-04-09 14:50:06 -0500 | [diff] [blame] | 604 | struct of_device_id; |
| 605 | |
| 606 | typedef void (*of_clk_init_cb_t)(struct device_node *); |
| 607 | |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 608 | struct clk_onecell_data { |
| 609 | struct clk **clks; |
| 610 | unsigned int clk_num; |
| 611 | }; |
| 612 | |
Tero Kristo | 819b486 | 2013-10-22 11:39:36 +0300 | [diff] [blame] | 613 | extern struct of_device_id __clk_of_table; |
| 614 | |
Rob Herring | 54196cc | 2014-05-08 16:09:24 -0500 | [diff] [blame] | 615 | #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 616 | |
| 617 | #ifdef CONFIG_OF |
Grant Likely | 766e6a4 | 2012-04-09 14:50:06 -0500 | [diff] [blame] | 618 | int of_clk_add_provider(struct device_node *np, |
| 619 | struct clk *(*clk_src_get)(struct of_phandle_args *args, |
| 620 | void *data), |
| 621 | void *data); |
| 622 | void of_clk_del_provider(struct device_node *np); |
| 623 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, |
| 624 | void *data); |
Shawn Guo | 494bfec | 2012-08-22 21:36:27 +0800 | [diff] [blame] | 625 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
Mike Turquette | f610274 | 2013-10-07 23:12:13 -0700 | [diff] [blame] | 626 | int of_clk_get_parent_count(struct device_node *np); |
Grant Likely | 766e6a4 | 2012-04-09 14:50:06 -0500 | [diff] [blame] | 627 | const char *of_clk_get_parent_name(struct device_node *np, int index); |
Prashant Gaikwad | f2f6c25 | 2013-01-04 12:30:52 +0530 | [diff] [blame] | 628 | |
Grant Likely | 766e6a4 | 2012-04-09 14:50:06 -0500 | [diff] [blame] | 629 | void of_clk_init(const struct of_device_id *matches); |
| 630 | |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 631 | #else /* !CONFIG_OF */ |
Prashant Gaikwad | f2f6c25 | 2013-01-04 12:30:52 +0530 | [diff] [blame] | 632 | |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 633 | static inline int of_clk_add_provider(struct device_node *np, |
| 634 | struct clk *(*clk_src_get)(struct of_phandle_args *args, |
| 635 | void *data), |
| 636 | void *data) |
| 637 | { |
| 638 | return 0; |
| 639 | } |
| 640 | #define of_clk_del_provider(np) \ |
| 641 | { while (0); } |
| 642 | static inline struct clk *of_clk_src_simple_get( |
| 643 | struct of_phandle_args *clkspec, void *data) |
| 644 | { |
| 645 | return ERR_PTR(-ENOENT); |
| 646 | } |
| 647 | static inline struct clk *of_clk_src_onecell_get( |
| 648 | struct of_phandle_args *clkspec, void *data) |
| 649 | { |
| 650 | return ERR_PTR(-ENOENT); |
| 651 | } |
| 652 | static inline const char *of_clk_get_parent_name(struct device_node *np, |
| 653 | int index) |
| 654 | { |
| 655 | return NULL; |
| 656 | } |
| 657 | #define of_clk_init(matches) \ |
| 658 | { while (0); } |
| 659 | #endif /* CONFIG_OF */ |
Gerhard Sittig | aa514ce | 2013-07-22 14:14:40 +0200 | [diff] [blame] | 660 | |
| 661 | /* |
| 662 | * wrap access to peripherals in accessor routines |
| 663 | * for improved portability across platforms |
| 664 | */ |
| 665 | |
Gerhard Sittig | 6d8cdb6 | 2013-11-30 23:51:24 +0100 | [diff] [blame] | 666 | #if IS_ENABLED(CONFIG_PPC) |
| 667 | |
| 668 | static inline u32 clk_readl(u32 __iomem *reg) |
| 669 | { |
| 670 | return ioread32be(reg); |
| 671 | } |
| 672 | |
| 673 | static inline void clk_writel(u32 val, u32 __iomem *reg) |
| 674 | { |
| 675 | iowrite32be(val, reg); |
| 676 | } |
| 677 | |
| 678 | #else /* platform dependent I/O accessors */ |
| 679 | |
Gerhard Sittig | aa514ce | 2013-07-22 14:14:40 +0200 | [diff] [blame] | 680 | static inline u32 clk_readl(u32 __iomem *reg) |
| 681 | { |
| 682 | return readl(reg); |
| 683 | } |
| 684 | |
| 685 | static inline void clk_writel(u32 val, u32 __iomem *reg) |
| 686 | { |
| 687 | writel(val, reg); |
| 688 | } |
| 689 | |
Gerhard Sittig | 6d8cdb6 | 2013-11-30 23:51:24 +0100 | [diff] [blame] | 690 | #endif /* platform dependent I/O accessors */ |
| 691 | |
Peter De Schrijver | fb2b3c9 | 2014-06-26 18:00:53 +0300 | [diff] [blame] | 692 | #ifdef CONFIG_DEBUG_FS |
Tomeu Vizoso | 61c7cdd | 2014-12-02 08:54:21 +0100 | [diff] [blame] | 693 | struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode, |
Peter De Schrijver | fb2b3c9 | 2014-06-26 18:00:53 +0300 | [diff] [blame] | 694 | void *data, const struct file_operations *fops); |
| 695 | #endif |
| 696 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 697 | #endif /* CONFIG_COMMON_CLK */ |
| 698 | #endif /* CLK_PROVIDER_H */ |