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gerrit-public.fairphone.software / kernel / msm-4.19 / b81eec09a484c588ead035003ce7555ca8a9963a / . / include / linux / mfd / palmas.h
blob: 061cce0b119a2d039f222642f81226e0d6fd0644 [file] [log] [blame]
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]1/*
2 * TI Palmas
3 *
Ian Lartey654003e2013-03-22 14:55:12 +0000[diff] [blame]4 * Copyright 2011-2013 Texas Instruments Inc.
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
Ian Lartey654003e2013-03-22 14:55:12 +0000[diff] [blame]7 * Author: Ian Lartey <ian@slimlogic.co.uk>
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __LINUX_MFD_PALMAS_H
17#define __LINUX_MFD_PALMAS_H
18
19#include <linux/usb/otg.h>
20#include <linux/leds.h>
21#include <linux/regmap.h>
22#include <linux/regulator/driver.h>
Graeme Gregoryb1f254e2013-05-28 10:50:11 +0900[diff] [blame]23#include <linux/extcon.h>
24#include <linux/usb/phy_companion.h>
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]25
26#define PALMAS_NUM_CLIENTS 3
27
Ian Lartey654003e2013-03-22 14:55:12 +0000[diff] [blame]28/* The ID_REVISION NUMBERS */
29#define PALMAS_CHIP_OLD_ID 0x0000
30#define PALMAS_CHIP_ID 0xC035
31#define PALMAS_CHIP_CHARGER_ID 0xC036
32
33#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
34 ((a) == PALMAS_CHIP_ID))
35#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
36
J Keerthy1ffb0be2013-06-19 11:27:48 +0530[diff] [blame]37/**
38 * Palmas PMIC feature types
39 *
40 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
41 * regulator.
42 *
43 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
44 * specific feature (above) or not. Return non-zero, if yes.
45 */
46#define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
47#define PALMAS_PMIC_HAS(b, f) \
48 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
49
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]50struct palmas_pmic;
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]51struct palmas_gpadc;
52struct palmas_resource;
53struct palmas_usb;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]54
Graeme Gregoryb1f254e2013-05-28 10:50:11 +0900[diff] [blame]55enum palmas_usb_state {
56 PALMAS_USB_STATE_DISCONNECT,
57 PALMAS_USB_STATE_VBUS,
58 PALMAS_USB_STATE_ID,
59};
60
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]61struct palmas {
62 struct device *dev;
63
64 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
65 struct regmap *regmap[PALMAS_NUM_CLIENTS];
66
67 /* Stored chip id */
68 int id;
69
J Keerthy1ffb0be2013-06-19 11:27:48 +0530[diff] [blame]70 unsigned int features;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]71 /* IRQ Data */
72 int irq;
73 u32 irq_mask;
74 struct mutex irq_lock;
75 struct regmap_irq_chip_data *irq_data;
76
77 /* Child Devices */
78 struct palmas_pmic *pmic;
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]79 struct palmas_gpadc *gpadc;
80 struct palmas_resource *resource;
81 struct palmas_usb *usb;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]82
83 /* GPIO MUXing */
84 u8 gpio_muxed;
85 u8 led_muxed;
86 u8 pwm_muxed;
87};
88
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]89struct palmas_gpadc_platform_data {
90 /* Channel 3 current source is only enabled during conversion */
91 int ch3_current;
92
93 /* Channel 0 current source can be used for battery detection.
94 * If used for battery detection this will cause a permanent current
95 * consumption depending on current level set here.
96 */
97 int ch0_current;
98
99 /* default BAT_REMOVAL_DAT setting on device probe */
100 int bat_removal;
101
102 /* Sets the START_POLARITY bit in the RT_CTRL register */
103 int start_polarity;
104};
105
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]106struct palmas_reg_init {
107 /* warm_rest controls the voltage levels after a warm reset
108 *
109 * 0: reload default values from OTP on warm reset
110 * 1: maintain voltage from VSEL on warm reset
111 */
112 int warm_reset;
113
114 /* roof_floor controls whether the regulator uses the i2c style
115 * of DVS or uses the method where a GPIO or other control method is
116 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
117 *
118 * For SMPS
119 *
120 * 0: i2c selection of voltage
121 * 1: pin selection of voltage.
122 *
123 * For LDO unused
124 */
125 int roof_floor;
126
127 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
128 * the data sheet.
129 *
130 * For SMPS
131 *
132 * 0: Off
133 * 1: AUTO
134 * 2: ECO
135 * 3: Forced PWM
136 *
137 * For LDO
138 *
139 * 0: Off
140 * 1: On
141 */
142 int mode_sleep;
143
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]144 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
145 * register. Set this is the default voltage set in OTP needs
146 * to be overridden.
147 */
148 u8 vsel;
149
150};
151
Graeme Gregory7cc4c922012-08-28 13:47:39 +0200[diff] [blame]152enum palmas_regulators {
153 /* SMPS regulators */
154 PALMAS_REG_SMPS12,
155 PALMAS_REG_SMPS123,
156 PALMAS_REG_SMPS3,
157 PALMAS_REG_SMPS45,
158 PALMAS_REG_SMPS457,
159 PALMAS_REG_SMPS6,
160 PALMAS_REG_SMPS7,
161 PALMAS_REG_SMPS8,
162 PALMAS_REG_SMPS9,
163 PALMAS_REG_SMPS10,
164 /* LDO regulators */
165 PALMAS_REG_LDO1,
166 PALMAS_REG_LDO2,
167 PALMAS_REG_LDO3,
168 PALMAS_REG_LDO4,
169 PALMAS_REG_LDO5,
170 PALMAS_REG_LDO6,
171 PALMAS_REG_LDO7,
172 PALMAS_REG_LDO8,
173 PALMAS_REG_LDO9,
174 PALMAS_REG_LDOLN,
175 PALMAS_REG_LDOUSB,
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530[diff] [blame]176 /* External regulators */
177 PALMAS_REG_REGEN1,
178 PALMAS_REG_REGEN2,
179 PALMAS_REG_REGEN3,
180 PALMAS_REG_SYSEN1,
181 PALMAS_REG_SYSEN2,
Graeme Gregory7cc4c922012-08-28 13:47:39 +0200[diff] [blame]182 /* Total number of regulators */
183 PALMAS_NUM_REGS,
184};
185
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]186struct palmas_pmic_platform_data {
187 /* An array of pointers to regulator init data indexed by regulator
188 * ID
189 */
Graeme Gregory7cc4c922012-08-28 13:47:39 +0200[diff] [blame]190 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]191
192 /* An array of pointers to structures containing sleep mode and DVS
193 * configuration for regulators indexed by ID
194 */
Graeme Gregory7cc4c922012-08-28 13:47:39 +0200[diff] [blame]195 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]196
197 /* use LDO6 for vibrator control */
198 int ldo6_vibrator;
Laxman Dewangan17c11a72013-04-17 15:13:13 +0530[diff] [blame]199
200 /* Enable tracking mode of LDO8 */
201 bool enable_ldo8_tracking;
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]202};
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]203
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]204struct palmas_usb_platform_data {
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]205 /* Do we enable the wakeup comparator on probe */
206 int wakeup;
207};
208
209struct palmas_resource_platform_data {
210 int regen1_mode_sleep;
211 int regen2_mode_sleep;
212 int sysen1_mode_sleep;
213 int sysen2_mode_sleep;
214
215 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
216 u8 nsleep_res;
217 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
218 u8 nsleep_smps;
219 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
220 u8 nsleep_ldo1;
221 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
222 u8 nsleep_ldo2;
223
224 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
225 u8 enable1_res;
226 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
227 u8 enable1_smps;
228 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
229 u8 enable1_ldo1;
230 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
231 u8 enable1_ldo2;
232
233 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
234 u8 enable2_res;
235 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
236 u8 enable2_smps;
237 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
238 u8 enable2_ldo1;
239 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
240 u8 enable2_ldo2;
241};
242
243struct palmas_clk_platform_data {
244 int clk32kg_mode_sleep;
245 int clk32kgaudio_mode_sleep;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]246};
247
248struct palmas_platform_data {
Laxman Dewangandf545d12013-03-01 20:13:46 +0530[diff] [blame]249 int irq_flags;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]250 int gpio_base;
251
252 /* bit value to be loaded to the POWER_CTRL register */
253 u8 power_ctrl;
254
255 /*
256 * boolean to select if we want to configure muxing here
257 * then the two value to load into the registers if true
258 */
259 int mux_from_pdata;
260 u8 pad1, pad2;
Bill Huangb81eec02013-08-08 04:45:05 -0700[diff] [blame^]261 bool pm_off;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]262
263 struct palmas_pmic_platform_data *pmic_pdata;
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]264 struct palmas_gpadc_platform_data *gpadc_pdata;
265 struct palmas_usb_platform_data *usb_pdata;
266 struct palmas_resource_platform_data *resource_pdata;
267 struct palmas_clk_platform_data *clk_pdata;
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]268};
269
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]270struct palmas_gpadc_calibration {
271 s32 gain;
272 s32 gain_error;
273 s32 offset_error;
274};
275
276struct palmas_gpadc {
277 struct device *dev;
278 struct palmas *palmas;
279
280 int ch3_current;
281 int ch0_current;
282
283 int gpadc_force;
284
285 int bat_removal;
286
287 struct mutex reading_lock;
288 struct completion irq_complete;
289
290 int eoc_sw_irq;
291
292 struct palmas_gpadc_calibration *palmas_cal_tbl;
293
294 int conv0_channel;
295 int conv1_channel;
296 int rt_channel;
297};
298
299struct palmas_gpadc_result {
300 s32 raw_code;
301 s32 corrected_code;
302 s32 result;
303};
304
305#define PALMAS_MAX_CHANNELS 16
306
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]307/* Define the palmas IRQ numbers */
308enum palmas_irqs {
309 /* INT1 registers */
310 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
311 PALMAS_PWRON_IRQ,
312 PALMAS_LONG_PRESS_KEY_IRQ,
313 PALMAS_RPWRON_IRQ,
314 PALMAS_PWRDOWN_IRQ,
315 PALMAS_HOTDIE_IRQ,
316 PALMAS_VSYS_MON_IRQ,
317 PALMAS_VBAT_MON_IRQ,
318 /* INT2 registers */
319 PALMAS_RTC_ALARM_IRQ,
320 PALMAS_RTC_TIMER_IRQ,
321 PALMAS_WDT_IRQ,
322 PALMAS_BATREMOVAL_IRQ,
323 PALMAS_RESET_IN_IRQ,
324 PALMAS_FBI_BB_IRQ,
325 PALMAS_SHORT_IRQ,
326 PALMAS_VAC_ACOK_IRQ,
327 /* INT3 registers */
328 PALMAS_GPADC_AUTO_0_IRQ,
329 PALMAS_GPADC_AUTO_1_IRQ,
330 PALMAS_GPADC_EOC_SW_IRQ,
331 PALMAS_GPADC_EOC_RT_IRQ,
332 PALMAS_ID_OTG_IRQ,
333 PALMAS_ID_IRQ,
334 PALMAS_VBUS_OTG_IRQ,
335 PALMAS_VBUS_IRQ,
336 /* INT4 registers */
337 PALMAS_GPIO_0_IRQ,
338 PALMAS_GPIO_1_IRQ,
339 PALMAS_GPIO_2_IRQ,
340 PALMAS_GPIO_3_IRQ,
341 PALMAS_GPIO_4_IRQ,
342 PALMAS_GPIO_5_IRQ,
343 PALMAS_GPIO_6_IRQ,
344 PALMAS_GPIO_7_IRQ,
345 /* Total Number IRQs */
346 PALMAS_NUM_IRQ,
347};
348
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]349struct palmas_pmic {
350 struct palmas *palmas;
351 struct device *dev;
352 struct regulator_desc desc[PALMAS_NUM_REGS];
353 struct regulator_dev *rdev[PALMAS_NUM_REGS];
354 struct mutex mutex;
355
356 int smps123;
357 int smps457;
358
359 int range[PALMAS_REG_SMPS10];
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530[diff] [blame]360 unsigned int ramp_delay[PALMAS_REG_SMPS10];
Laxman Dewangan51d3a0c2013-04-18 18:32:48 +0530[diff] [blame]361 unsigned int current_reg_mode[PALMAS_REG_SMPS10];
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]362};
363
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]364struct palmas_resource {
365 struct palmas *palmas;
366 struct device *dev;
367};
368
369struct palmas_usb {
370 struct palmas *palmas;
371 struct device *dev;
372
Graeme Gregoryb1f254e2013-05-28 10:50:11 +0900[diff] [blame]373 struct extcon_dev edev;
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]374
375 /* used to set vbus, in atomic path */
376 struct work_struct set_vbus_work;
377
Graeme Gregoryb1f254e2013-05-28 10:50:11 +0900[diff] [blame]378 int id_otg_irq;
379 int id_irq;
380 int vbus_otg_irq;
381 int vbus_irq;
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]382
383 int vbus_enable;
384
Graeme Gregoryb1f254e2013-05-28 10:50:11 +0900[diff] [blame]385 enum palmas_usb_state linkstat;
Graeme Gregory190ef1a2012-08-28 13:47:37 +0200[diff] [blame]386};
387
388#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
389
390enum usb_irq_events {
391 /* Wakeup events from INT3 */
392 PALMAS_USB_ID_WAKEPUP,
393 PALMAS_USB_VBUS_WAKEUP,
394
395 /* ID_OTG_EVENTS */
396 PALMAS_USB_ID_GND,
397 N_PALMAS_USB_ID_GND,
398 PALMAS_USB_ID_C,
399 N_PALMAS_USB_ID_C,
400 PALMAS_USB_ID_B,
401 N_PALMAS_USB_ID_B,
402 PALMAS_USB_ID_A,
403 N_PALMAS_USB_ID_A,
404 PALMAS_USB_ID_FLOAT,
405 N_PALMAS_USB_ID_FLOAT,
406
407 /* VBUS_OTG_EVENTS */
408 PALMAS_USB_VB_SESS_END,
409 N_PALMAS_USB_VB_SESS_END,
410 PALMAS_USB_VB_SESS_VLD,
411 N_PALMAS_USB_VB_SESS_VLD,
412 PALMAS_USB_VA_SESS_VLD,
413 N_PALMAS_USB_VA_SESS_VLD,
414 PALMAS_USB_VA_VBUS_VLD,
415 N_PALMAS_USB_VA_VBUS_VLD,
416 PALMAS_USB_VADP_SNS,
417 N_PALMAS_USB_VADP_SNS,
418 PALMAS_USB_VADP_PRB,
419 N_PALMAS_USB_VADP_PRB,
420 PALMAS_USB_VOTG_SESS_VLD,
421 N_PALMAS_USB_VOTG_SESS_VLD,
422};
423
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]424/* defines so we can store the mux settings */
425#define PALMAS_GPIO_0_MUXED (1 << 0)
426#define PALMAS_GPIO_1_MUXED (1 << 1)
427#define PALMAS_GPIO_2_MUXED (1 << 2)
428#define PALMAS_GPIO_3_MUXED (1 << 3)
429#define PALMAS_GPIO_4_MUXED (1 << 4)
430#define PALMAS_GPIO_5_MUXED (1 << 5)
431#define PALMAS_GPIO_6_MUXED (1 << 6)
432#define PALMAS_GPIO_7_MUXED (1 << 7)
433
434#define PALMAS_LED1_MUXED (1 << 0)
435#define PALMAS_LED2_MUXED (1 << 1)
436
437#define PALMAS_PWM1_MUXED (1 << 0)
438#define PALMAS_PWM2_MUXED (1 << 1)
439
440/* helper macro to get correct slave number */
441#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
442#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y)
443
444/* Base addresses of IP blocks in Palmas */
445#define PALMAS_SMPS_DVS_BASE 0x20
446#define PALMAS_RTC_BASE 0x100
447#define PALMAS_VALIDITY_BASE 0x118
448#define PALMAS_SMPS_BASE 0x120
449#define PALMAS_LDO_BASE 0x150
450#define PALMAS_DVFS_BASE 0x180
451#define PALMAS_PMU_CONTROL_BASE 0x1A0
452#define PALMAS_RESOURCE_BASE 0x1D4
453#define PALMAS_PU_PD_OD_BASE 0x1F4
454#define PALMAS_LED_BASE 0x200
455#define PALMAS_INTERRUPT_BASE 0x210
456#define PALMAS_USB_OTG_BASE 0x250
457#define PALMAS_VIBRATOR_BASE 0x270
458#define PALMAS_GPIO_BASE 0x280
459#define PALMAS_USB_BASE 0x290
460#define PALMAS_GPADC_BASE 0x2C0
461#define PALMAS_TRIM_GPADC_BASE 0x3CD
462
463/* Registers for function RTC */
464#define PALMAS_SECONDS_REG 0x0
465#define PALMAS_MINUTES_REG 0x1
466#define PALMAS_HOURS_REG 0x2
467#define PALMAS_DAYS_REG 0x3
468#define PALMAS_MONTHS_REG 0x4
469#define PALMAS_YEARS_REG 0x5
470#define PALMAS_WEEKS_REG 0x6
471#define PALMAS_ALARM_SECONDS_REG 0x8
472#define PALMAS_ALARM_MINUTES_REG 0x9
473#define PALMAS_ALARM_HOURS_REG 0xA
474#define PALMAS_ALARM_DAYS_REG 0xB
475#define PALMAS_ALARM_MONTHS_REG 0xC
476#define PALMAS_ALARM_YEARS_REG 0xD
477#define PALMAS_RTC_CTRL_REG 0x10
478#define PALMAS_RTC_STATUS_REG 0x11
479#define PALMAS_RTC_INTERRUPTS_REG 0x12
480#define PALMAS_RTC_COMP_LSB_REG 0x13
481#define PALMAS_RTC_COMP_MSB_REG 0x14
482#define PALMAS_RTC_RES_PROG_REG 0x15
483#define PALMAS_RTC_RESET_STATUS_REG 0x16
484
485/* Bit definitions for SECONDS_REG */
486#define PALMAS_SECONDS_REG_SEC1_MASK 0x70
487#define PALMAS_SECONDS_REG_SEC1_SHIFT 4
488#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f
489#define PALMAS_SECONDS_REG_SEC0_SHIFT 0
490
491/* Bit definitions for MINUTES_REG */
492#define PALMAS_MINUTES_REG_MIN1_MASK 0x70
493#define PALMAS_MINUTES_REG_MIN1_SHIFT 4
494#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f
495#define PALMAS_MINUTES_REG_MIN0_SHIFT 0
496
497/* Bit definitions for HOURS_REG */
498#define PALMAS_HOURS_REG_PM_NAM 0x80
499#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7
500#define PALMAS_HOURS_REG_HOUR1_MASK 0x30
501#define PALMAS_HOURS_REG_HOUR1_SHIFT 4
502#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f
503#define PALMAS_HOURS_REG_HOUR0_SHIFT 0
504
505/* Bit definitions for DAYS_REG */
506#define PALMAS_DAYS_REG_DAY1_MASK 0x30
507#define PALMAS_DAYS_REG_DAY1_SHIFT 4
508#define PALMAS_DAYS_REG_DAY0_MASK 0x0f
509#define PALMAS_DAYS_REG_DAY0_SHIFT 0
510
511/* Bit definitions for MONTHS_REG */
512#define PALMAS_MONTHS_REG_MONTH1 0x10
513#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4
514#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f
515#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0
516
517/* Bit definitions for YEARS_REG */
518#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
519#define PALMAS_YEARS_REG_YEAR1_SHIFT 4
520#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f
521#define PALMAS_YEARS_REG_YEAR0_SHIFT 0
522
523/* Bit definitions for WEEKS_REG */
524#define PALMAS_WEEKS_REG_WEEK_MASK 0x07
525#define PALMAS_WEEKS_REG_WEEK_SHIFT 0
526
527/* Bit definitions for ALARM_SECONDS_REG */
528#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
529#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4
530#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f
531#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0
532
533/* Bit definitions for ALARM_MINUTES_REG */
534#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
535#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4
536#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f
537#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0
538
539/* Bit definitions for ALARM_HOURS_REG */
540#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
541#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7
542#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
543#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4
544#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f
545#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0
546
547/* Bit definitions for ALARM_DAYS_REG */
548#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
549#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4
550#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f
551#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0
552
553/* Bit definitions for ALARM_MONTHS_REG */
554#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
555#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4
556#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f
557#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0
558
559/* Bit definitions for ALARM_YEARS_REG */
560#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
561#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4
562#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f
563#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0
564
565/* Bit definitions for RTC_CTRL_REG */
566#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
567#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7
568#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
569#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6
570#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
571#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5
572#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
573#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4
574#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
575#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3
576#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
577#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2
578#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
579#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1
580#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
581#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0
582
583/* Bit definitions for RTC_STATUS_REG */
584#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
585#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7
586#define PALMAS_RTC_STATUS_REG_ALARM 0x40
587#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6
588#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
589#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5
590#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
591#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4
592#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
593#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3
594#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
595#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2
596#define PALMAS_RTC_STATUS_REG_RUN 0x02
597#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1
598
599/* Bit definitions for RTC_INTERRUPTS_REG */
600#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
601#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4
602#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
603#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3
604#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
605#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2
606#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
607#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0
608
609/* Bit definitions for RTC_COMP_LSB_REG */
610#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff
611#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0
612
613/* Bit definitions for RTC_COMP_MSB_REG */
614#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff
615#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0
616
617/* Bit definitions for RTC_RES_PROG_REG */
618#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f
619#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0
620
621/* Bit definitions for RTC_RESET_STATUS_REG */
622#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
623#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0
624
625/* Registers for function BACKUP */
626#define PALMAS_BACKUP0 0x0
627#define PALMAS_BACKUP1 0x1
628#define PALMAS_BACKUP2 0x2
629#define PALMAS_BACKUP3 0x3
630#define PALMAS_BACKUP4 0x4
631#define PALMAS_BACKUP5 0x5
632#define PALMAS_BACKUP6 0x6
633#define PALMAS_BACKUP7 0x7
634
635/* Bit definitions for BACKUP0 */
636#define PALMAS_BACKUP0_BACKUP_MASK 0xff
637#define PALMAS_BACKUP0_BACKUP_SHIFT 0
638
639/* Bit definitions for BACKUP1 */
640#define PALMAS_BACKUP1_BACKUP_MASK 0xff
641#define PALMAS_BACKUP1_BACKUP_SHIFT 0
642
643/* Bit definitions for BACKUP2 */
644#define PALMAS_BACKUP2_BACKUP_MASK 0xff
645#define PALMAS_BACKUP2_BACKUP_SHIFT 0
646
647/* Bit definitions for BACKUP3 */
648#define PALMAS_BACKUP3_BACKUP_MASK 0xff
649#define PALMAS_BACKUP3_BACKUP_SHIFT 0
650
651/* Bit definitions for BACKUP4 */
652#define PALMAS_BACKUP4_BACKUP_MASK 0xff
653#define PALMAS_BACKUP4_BACKUP_SHIFT 0
654
655/* Bit definitions for BACKUP5 */
656#define PALMAS_BACKUP5_BACKUP_MASK 0xff
657#define PALMAS_BACKUP5_BACKUP_SHIFT 0
658
659/* Bit definitions for BACKUP6 */
660#define PALMAS_BACKUP6_BACKUP_MASK 0xff
661#define PALMAS_BACKUP6_BACKUP_SHIFT 0
662
663/* Bit definitions for BACKUP7 */
664#define PALMAS_BACKUP7_BACKUP_MASK 0xff
665#define PALMAS_BACKUP7_BACKUP_SHIFT 0
666
667/* Registers for function SMPS */
668#define PALMAS_SMPS12_CTRL 0x0
669#define PALMAS_SMPS12_TSTEP 0x1
670#define PALMAS_SMPS12_FORCE 0x2
671#define PALMAS_SMPS12_VOLTAGE 0x3
672#define PALMAS_SMPS3_CTRL 0x4
673#define PALMAS_SMPS3_VOLTAGE 0x7
674#define PALMAS_SMPS45_CTRL 0x8
675#define PALMAS_SMPS45_TSTEP 0x9
676#define PALMAS_SMPS45_FORCE 0xA
677#define PALMAS_SMPS45_VOLTAGE 0xB
678#define PALMAS_SMPS6_CTRL 0xC
679#define PALMAS_SMPS6_TSTEP 0xD
680#define PALMAS_SMPS6_FORCE 0xE
681#define PALMAS_SMPS6_VOLTAGE 0xF
682#define PALMAS_SMPS7_CTRL 0x10
683#define PALMAS_SMPS7_VOLTAGE 0x13
684#define PALMAS_SMPS8_CTRL 0x14
685#define PALMAS_SMPS8_TSTEP 0x15
686#define PALMAS_SMPS8_FORCE 0x16
687#define PALMAS_SMPS8_VOLTAGE 0x17
688#define PALMAS_SMPS9_CTRL 0x18
689#define PALMAS_SMPS9_VOLTAGE 0x1B
690#define PALMAS_SMPS10_CTRL 0x1C
691#define PALMAS_SMPS10_STATUS 0x1F
692#define PALMAS_SMPS_CTRL 0x24
693#define PALMAS_SMPS_PD_CTRL 0x25
694#define PALMAS_SMPS_DITHER_EN 0x26
695#define PALMAS_SMPS_THERMAL_EN 0x27
696#define PALMAS_SMPS_THERMAL_STATUS 0x28
697#define PALMAS_SMPS_SHORT_STATUS 0x29
698#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
699#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
700#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
701
702/* Bit definitions for SMPS12_CTRL */
703#define PALMAS_SMPS12_CTRL_WR_S 0x80
704#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7
705#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
706#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6
707#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
708#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4
709#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
710#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2
711#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
712#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0
713
714/* Bit definitions for SMPS12_TSTEP */
715#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
716#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0
717
718/* Bit definitions for SMPS12_FORCE */
719#define PALMAS_SMPS12_FORCE_CMD 0x80
720#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7
721#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f
722#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0
723
724/* Bit definitions for SMPS12_VOLTAGE */
725#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
726#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7
727#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f
728#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0
729
730/* Bit definitions for SMPS3_CTRL */
731#define PALMAS_SMPS3_CTRL_WR_S 0x80
732#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7
733#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
734#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4
735#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
736#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2
737#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
738#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0
739
740/* Bit definitions for SMPS3_VOLTAGE */
741#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
742#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7
743#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f
744#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0
745
746/* Bit definitions for SMPS45_CTRL */
747#define PALMAS_SMPS45_CTRL_WR_S 0x80
748#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7
749#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
750#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6
751#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
752#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4
753#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
754#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2
755#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
756#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0
757
758/* Bit definitions for SMPS45_TSTEP */
759#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
760#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0
761
762/* Bit definitions for SMPS45_FORCE */
763#define PALMAS_SMPS45_FORCE_CMD 0x80
764#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7
765#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f
766#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0
767
768/* Bit definitions for SMPS45_VOLTAGE */
769#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
770#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7
771#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f
772#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0
773
774/* Bit definitions for SMPS6_CTRL */
775#define PALMAS_SMPS6_CTRL_WR_S 0x80
776#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7
777#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
778#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6
779#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
780#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4
781#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
782#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2
783#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
784#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0
785
786/* Bit definitions for SMPS6_TSTEP */
787#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
788#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0
789
790/* Bit definitions for SMPS6_FORCE */
791#define PALMAS_SMPS6_FORCE_CMD 0x80
792#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7
793#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f
794#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0
795
796/* Bit definitions for SMPS6_VOLTAGE */
797#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
798#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7
799#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f
800#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0
801
802/* Bit definitions for SMPS7_CTRL */
803#define PALMAS_SMPS7_CTRL_WR_S 0x80
804#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7
805#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
806#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4
807#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
808#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2
809#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
810#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0
811
812/* Bit definitions for SMPS7_VOLTAGE */
813#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
814#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7
815#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f
816#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0
817
818/* Bit definitions for SMPS8_CTRL */
819#define PALMAS_SMPS8_CTRL_WR_S 0x80
820#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7
821#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
822#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6
823#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
824#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4
825#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
826#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2
827#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
828#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0
829
830/* Bit definitions for SMPS8_TSTEP */
831#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
832#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0
833
834/* Bit definitions for SMPS8_FORCE */
835#define PALMAS_SMPS8_FORCE_CMD 0x80
836#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7
837#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f
838#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0
839
840/* Bit definitions for SMPS8_VOLTAGE */
841#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
842#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7
843#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f
844#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0
845
846/* Bit definitions for SMPS9_CTRL */
847#define PALMAS_SMPS9_CTRL_WR_S 0x80
848#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7
849#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
850#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4
851#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
852#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2
853#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
854#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0
855
856/* Bit definitions for SMPS9_VOLTAGE */
857#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
858#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7
859#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f
860#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0
861
862/* Bit definitions for SMPS10_CTRL */
863#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
864#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4
865#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f
866#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0
867
868/* Bit definitions for SMPS10_STATUS */
869#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f
870#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0
871
872/* Bit definitions for SMPS_CTRL */
873#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
874#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5
875#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
876#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4
877#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
878#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2
879#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
880#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0
881
882/* Bit definitions for SMPS_PD_CTRL */
883#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
884#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6
885#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
886#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5
887#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
888#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4
889#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
890#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3
891#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
892#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2
893#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
894#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1
895#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
896#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0
897
898/* Bit definitions for SMPS_THERMAL_EN */
899#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
900#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6
901#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
902#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5
903#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
904#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3
905#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
906#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2
907#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
908#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0
909
910/* Bit definitions for SMPS_THERMAL_STATUS */
911#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
912#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6
913#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
914#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5
915#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
916#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3
917#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
918#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2
919#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
920#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0
921
922/* Bit definitions for SMPS_SHORT_STATUS */
923#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
924#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7
925#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
926#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6
927#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
928#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5
929#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
930#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4
931#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
932#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3
933#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
934#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2
935#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
936#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1
937#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
938#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0
939
940/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
941#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
942#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6
943#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
944#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5
945#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
946#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4
947#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
948#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3
949#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
950#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2
951#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
952#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1
953#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
954#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0
955
956/* Bit definitions for SMPS_POWERGOOD_MASK1 */
957#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
958#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7
959#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
960#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6
961#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
962#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5
963#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
964#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4
965#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
966#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3
967#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
968#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2
969#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
970#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1
971#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
972#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0
973
974/* Bit definitions for SMPS_POWERGOOD_MASK2 */
975#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
976#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
977#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
978#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2
979#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
980#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1
981#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
982#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0
983
984/* Registers for function LDO */
985#define PALMAS_LDO1_CTRL 0x0
986#define PALMAS_LDO1_VOLTAGE 0x1
987#define PALMAS_LDO2_CTRL 0x2
988#define PALMAS_LDO2_VOLTAGE 0x3
989#define PALMAS_LDO3_CTRL 0x4
990#define PALMAS_LDO3_VOLTAGE 0x5
991#define PALMAS_LDO4_CTRL 0x6
992#define PALMAS_LDO4_VOLTAGE 0x7
993#define PALMAS_LDO5_CTRL 0x8
994#define PALMAS_LDO5_VOLTAGE 0x9
995#define PALMAS_LDO6_CTRL 0xA
996#define PALMAS_LDO6_VOLTAGE 0xB
997#define PALMAS_LDO7_CTRL 0xC
998#define PALMAS_LDO7_VOLTAGE 0xD
999#define PALMAS_LDO8_CTRL 0xE
1000#define PALMAS_LDO8_VOLTAGE 0xF
1001#define PALMAS_LDO9_CTRL 0x10
1002#define PALMAS_LDO9_VOLTAGE 0x11
1003#define PALMAS_LDOLN_CTRL 0x12
1004#define PALMAS_LDOLN_VOLTAGE 0x13
1005#define PALMAS_LDOUSB_CTRL 0x14
1006#define PALMAS_LDOUSB_VOLTAGE 0x15
1007#define PALMAS_LDO_CTRL 0x1A
1008#define PALMAS_LDO_PD_CTRL1 0x1B
1009#define PALMAS_LDO_PD_CTRL2 0x1C
1010#define PALMAS_LDO_SHORT_STATUS1 0x1D
1011#define PALMAS_LDO_SHORT_STATUS2 0x1E
1012
1013/* Bit definitions for LDO1_CTRL */
1014#define PALMAS_LDO1_CTRL_WR_S 0x80
1015#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7
1016#define PALMAS_LDO1_CTRL_STATUS 0x10
1017#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4
1018#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
1019#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2
1020#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
1021#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0
1022
1023/* Bit definitions for LDO1_VOLTAGE */
1024#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f
1025#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0
1026
1027/* Bit definitions for LDO2_CTRL */
1028#define PALMAS_LDO2_CTRL_WR_S 0x80
1029#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7
1030#define PALMAS_LDO2_CTRL_STATUS 0x10
1031#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4
1032#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1033#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2
1034#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1035#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0
1036
1037/* Bit definitions for LDO2_VOLTAGE */
1038#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f
1039#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0
1040
1041/* Bit definitions for LDO3_CTRL */
1042#define PALMAS_LDO3_CTRL_WR_S 0x80
1043#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7
1044#define PALMAS_LDO3_CTRL_STATUS 0x10
1045#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4
1046#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1047#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2
1048#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1049#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0
1050
1051/* Bit definitions for LDO3_VOLTAGE */
1052#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f
1053#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0
1054
1055/* Bit definitions for LDO4_CTRL */
1056#define PALMAS_LDO4_CTRL_WR_S 0x80
1057#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7
1058#define PALMAS_LDO4_CTRL_STATUS 0x10
1059#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4
1060#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1061#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2
1062#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1063#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0
1064
1065/* Bit definitions for LDO4_VOLTAGE */
1066#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f
1067#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0
1068
1069/* Bit definitions for LDO5_CTRL */
1070#define PALMAS_LDO5_CTRL_WR_S 0x80
1071#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7
1072#define PALMAS_LDO5_CTRL_STATUS 0x10
1073#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4
1074#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1075#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2
1076#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1077#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0
1078
1079/* Bit definitions for LDO5_VOLTAGE */
1080#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f
1081#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0
1082
1083/* Bit definitions for LDO6_CTRL */
1084#define PALMAS_LDO6_CTRL_WR_S 0x80
1085#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7
1086#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1087#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6
1088#define PALMAS_LDO6_CTRL_STATUS 0x10
1089#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4
1090#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1091#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2
1092#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1093#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0
1094
1095/* Bit definitions for LDO6_VOLTAGE */
1096#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f
1097#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0
1098
1099/* Bit definitions for LDO7_CTRL */
1100#define PALMAS_LDO7_CTRL_WR_S 0x80
1101#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7
1102#define PALMAS_LDO7_CTRL_STATUS 0x10
1103#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4
1104#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1105#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2
1106#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1107#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0
1108
1109/* Bit definitions for LDO7_VOLTAGE */
1110#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f
1111#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0
1112
1113/* Bit definitions for LDO8_CTRL */
1114#define PALMAS_LDO8_CTRL_WR_S 0x80
1115#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7
1116#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1117#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6
1118#define PALMAS_LDO8_CTRL_STATUS 0x10
1119#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4
1120#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1121#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2
1122#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1123#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0
1124
1125/* Bit definitions for LDO8_VOLTAGE */
1126#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f
1127#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0
1128
1129/* Bit definitions for LDO9_CTRL */
1130#define PALMAS_LDO9_CTRL_WR_S 0x80
1131#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7
1132#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1133#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6
1134#define PALMAS_LDO9_CTRL_STATUS 0x10
1135#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4
1136#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1137#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2
1138#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1139#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0
1140
1141/* Bit definitions for LDO9_VOLTAGE */
1142#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f
1143#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0
1144
1145/* Bit definitions for LDOLN_CTRL */
1146#define PALMAS_LDOLN_CTRL_WR_S 0x80
1147#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7
1148#define PALMAS_LDOLN_CTRL_STATUS 0x10
1149#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4
1150#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1151#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2
1152#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1153#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0
1154
1155/* Bit definitions for LDOLN_VOLTAGE */
1156#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f
1157#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0
1158
1159/* Bit definitions for LDOUSB_CTRL */
1160#define PALMAS_LDOUSB_CTRL_WR_S 0x80
1161#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7
1162#define PALMAS_LDOUSB_CTRL_STATUS 0x10
1163#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4
1164#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1165#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2
1166#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1167#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0
1168
1169/* Bit definitions for LDOUSB_VOLTAGE */
1170#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f
1171#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0
1172
1173/* Bit definitions for LDO_CTRL */
1174#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1175#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0
1176
1177/* Bit definitions for LDO_PD_CTRL1 */
1178#define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1179#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7
1180#define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1181#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6
1182#define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1183#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5
1184#define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1185#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4
1186#define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1187#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3
1188#define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1189#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2
1190#define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1191#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1
1192#define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1193#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0
1194
1195/* Bit definitions for LDO_PD_CTRL2 */
1196#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1197#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2
1198#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1199#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1
1200#define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1201#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0
1202
1203/* Bit definitions for LDO_SHORT_STATUS1 */
1204#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1205#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7
1206#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1207#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6
1208#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1209#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5
1210#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1211#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4
1212#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1213#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3
1214#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1215#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2
1216#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1217#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1
1218#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1219#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0
1220
1221/* Bit definitions for LDO_SHORT_STATUS2 */
1222#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1223#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3
1224#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1225#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2
1226#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1227#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1
1228#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1229#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0
1230
1231/* Registers for function PMU_CONTROL */
1232#define PALMAS_DEV_CTRL 0x0
1233#define PALMAS_POWER_CTRL 0x1
1234#define PALMAS_VSYS_LO 0x2
1235#define PALMAS_VSYS_MON 0x3
1236#define PALMAS_VBAT_MON 0x4
1237#define PALMAS_WATCHDOG 0x5
1238#define PALMAS_BOOT_STATUS 0x6
1239#define PALMAS_BATTERY_BOUNCE 0x7
1240#define PALMAS_BACKUP_BATTERY_CTRL 0x8
1241#define PALMAS_LONG_PRESS_KEY 0x9
1242#define PALMAS_OSC_THERM_CTRL 0xA
1243#define PALMAS_BATDEBOUNCING 0xB
1244#define PALMAS_SWOFF_HWRST 0xF
1245#define PALMAS_SWOFF_COLDRST 0x10
1246#define PALMAS_SWOFF_STATUS 0x11
1247#define PALMAS_PMU_CONFIG 0x12
1248#define PALMAS_SPARE 0x14
1249#define PALMAS_PMU_SECONDARY_INT 0x15
1250#define PALMAS_SW_REVISION 0x17
1251#define PALMAS_EXT_CHRG_CTRL 0x18
1252#define PALMAS_PMU_SECONDARY_INT2 0x19
1253
1254/* Bit definitions for DEV_CTRL */
1255#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1256#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2
1257#define PALMAS_DEV_CTRL_SW_RST 0x02
1258#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1
1259#define PALMAS_DEV_CTRL_DEV_ON 0x01
1260#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0
1261
1262/* Bit definitions for POWER_CTRL */
1263#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1264#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2
1265#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1266#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1
1267#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1268#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0
1269
1270/* Bit definitions for VSYS_LO */
1271#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f
1272#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0
1273
1274/* Bit definitions for VSYS_MON */
1275#define PALMAS_VSYS_MON_ENABLE 0x80
1276#define PALMAS_VSYS_MON_ENABLE_SHIFT 7
1277#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f
1278#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0
1279
1280/* Bit definitions for VBAT_MON */
1281#define PALMAS_VBAT_MON_ENABLE 0x80
1282#define PALMAS_VBAT_MON_ENABLE_SHIFT 7
1283#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f
1284#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0
1285
1286/* Bit definitions for WATCHDOG */
1287#define PALMAS_WATCHDOG_LOCK 0x20
1288#define PALMAS_WATCHDOG_LOCK_SHIFT 5
1289#define PALMAS_WATCHDOG_ENABLE 0x10
1290#define PALMAS_WATCHDOG_ENABLE_SHIFT 4
1291#define PALMAS_WATCHDOG_MODE 0x08
1292#define PALMAS_WATCHDOG_MODE_SHIFT 3
1293#define PALMAS_WATCHDOG_TIMER_MASK 0x07
1294#define PALMAS_WATCHDOG_TIMER_SHIFT 0
1295
1296/* Bit definitions for BOOT_STATUS */
1297#define PALMAS_BOOT_STATUS_BOOT1 0x02
1298#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1
1299#define PALMAS_BOOT_STATUS_BOOT0 0x01
1300#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0
1301
1302/* Bit definitions for BATTERY_BOUNCE */
1303#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f
1304#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0
1305
1306/* Bit definitions for BACKUP_BATTERY_CTRL */
1307#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1308#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7
1309#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1310#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6
1311#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1312#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5
1313#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1314#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4
1315#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1316#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3
1317#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1318#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1
1319#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1320#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0
1321
1322/* Bit definitions for LONG_PRESS_KEY */
1323#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1324#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7
1325#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1326#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4
1327#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1328#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2
1329#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1330#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0
1331
1332/* Bit definitions for OSC_THERM_CTRL */
1333#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1334#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7
1335#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1336#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6
1337#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1338#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5
1339#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1340#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4
1341#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1342#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2
1343#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1344#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1
1345#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1346#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0
1347
1348/* Bit definitions for BATDEBOUNCING */
1349#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1350#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7
1351#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1352#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3
1353#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1354#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0
1355
1356/* Bit definitions for SWOFF_HWRST */
1357#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1358#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7
1359#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1360#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6
1361#define PALMAS_SWOFF_HWRST_WTD 0x20
1362#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5
1363#define PALMAS_SWOFF_HWRST_TSHUT 0x10
1364#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4
1365#define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1366#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3
1367#define PALMAS_SWOFF_HWRST_SW_RST 0x04
1368#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2
1369#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1370#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1
1371#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1372#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0
1373
1374/* Bit definitions for SWOFF_COLDRST */
1375#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1376#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7
1377#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1378#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6
1379#define PALMAS_SWOFF_COLDRST_WTD 0x20
1380#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5
1381#define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1382#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4
1383#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1384#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3
1385#define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1386#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2
1387#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1388#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1
1389#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1390#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0
1391
1392/* Bit definitions for SWOFF_STATUS */
1393#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1394#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7
1395#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1396#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6
1397#define PALMAS_SWOFF_STATUS_WTD 0x20
1398#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5
1399#define PALMAS_SWOFF_STATUS_TSHUT 0x10
1400#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4
1401#define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1402#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3
1403#define PALMAS_SWOFF_STATUS_SW_RST 0x04
1404#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2
1405#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1406#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1
1407#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1408#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0
1409
1410/* Bit definitions for PMU_CONFIG */
1411#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1412#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6
1413#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1414#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4
1415#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1416#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2
1417#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1418#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1
1419#define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1420#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0
1421
1422/* Bit definitions for SPARE */
1423#define PALMAS_SPARE_SPARE_MASK 0xf8
1424#define PALMAS_SPARE_SPARE_SHIFT 3
1425#define PALMAS_SPARE_REGEN3_OD 0x04
1426#define PALMAS_SPARE_REGEN3_OD_SHIFT 2
1427#define PALMAS_SPARE_REGEN2_OD 0x02
1428#define PALMAS_SPARE_REGEN2_OD_SHIFT 1
1429#define PALMAS_SPARE_REGEN1_OD 0x01
1430#define PALMAS_SPARE_REGEN1_OD_SHIFT 0
1431
1432/* Bit definitions for PMU_SECONDARY_INT */
1433#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1434#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7
1435#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1436#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6
1437#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1438#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5
1439#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1440#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4
1441#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1442#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3
1443#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1444#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2
1445#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1446#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1
1447#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1448#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0
1449
1450/* Bit definitions for SW_REVISION */
1451#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff
1452#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0
1453
1454/* Bit definitions for EXT_CHRG_CTRL */
1455#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1456#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7
1457#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1458#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6
1459#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1460#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3
1461#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1462#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2
1463#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1464#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1
1465#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1466#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0
1467
1468/* Bit definitions for PMU_SECONDARY_INT2 */
1469#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1470#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5
1471#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1472#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4
1473#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1474#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1
1475#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1476#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0
1477
1478/* Registers for function RESOURCE */
1479#define PALMAS_CLK32KG_CTRL 0x0
1480#define PALMAS_CLK32KGAUDIO_CTRL 0x1
1481#define PALMAS_REGEN1_CTRL 0x2
1482#define PALMAS_REGEN2_CTRL 0x3
1483#define PALMAS_SYSEN1_CTRL 0x4
1484#define PALMAS_SYSEN2_CTRL 0x5
1485#define PALMAS_NSLEEP_RES_ASSIGN 0x6
1486#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7
1487#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8
1488#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9
1489#define PALMAS_ENABLE1_RES_ASSIGN 0xA
1490#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB
1491#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC
1492#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD
1493#define PALMAS_ENABLE2_RES_ASSIGN 0xE
1494#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF
1495#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1496#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1497#define PALMAS_REGEN3_CTRL 0x12
1498
1499/* Bit definitions for CLK32KG_CTRL */
1500#define PALMAS_CLK32KG_CTRL_STATUS 0x10
1501#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4
1502#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1503#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2
1504#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1505#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0
1506
1507/* Bit definitions for CLK32KGAUDIO_CTRL */
1508#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1509#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4
1510#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1511#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3
1512#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1513#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2
1514#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1515#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0
1516
1517/* Bit definitions for REGEN1_CTRL */
1518#define PALMAS_REGEN1_CTRL_STATUS 0x10
1519#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4
1520#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1521#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2
1522#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1523#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0
1524
1525/* Bit definitions for REGEN2_CTRL */
1526#define PALMAS_REGEN2_CTRL_STATUS 0x10
1527#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4
1528#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1529#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2
1530#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1531#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0
1532
1533/* Bit definitions for SYSEN1_CTRL */
1534#define PALMAS_SYSEN1_CTRL_STATUS 0x10
1535#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4
1536#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1537#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2
1538#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1539#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0
1540
1541/* Bit definitions for SYSEN2_CTRL */
1542#define PALMAS_SYSEN2_CTRL_STATUS 0x10
1543#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4
1544#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1545#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2
1546#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1547#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0
1548
1549/* Bit definitions for NSLEEP_RES_ASSIGN */
1550#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1551#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6
1552#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1553#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1554#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1555#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4
1556#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1557#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3
1558#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1559#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2
1560#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1561#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1
1562#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1563#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0
1564
1565/* Bit definitions for NSLEEP_SMPS_ASSIGN */
1566#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1567#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7
1568#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1569#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6
1570#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1571#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5
1572#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1573#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4
1574#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1575#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3
1576#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1577#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2
1578#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1579#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1
1580#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1581#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0
1582
1583/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1584#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1585#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7
1586#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1587#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6
1588#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1589#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5
1590#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1591#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4
1592#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1593#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3
1594#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1595#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2
1596#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1597#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1
1598#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1599#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0
1600
1601/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1602#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1603#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2
1604#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1605#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1
1606#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1607#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0
1608
1609/* Bit definitions for ENABLE1_RES_ASSIGN */
1610#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1611#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6
1612#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1613#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1614#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1615#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4
1616#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1617#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3
1618#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1619#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2
1620#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1621#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1
1622#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1623#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0
1624
1625/* Bit definitions for ENABLE1_SMPS_ASSIGN */
1626#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1627#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7
1628#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1629#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6
1630#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1631#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5
1632#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1633#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4
1634#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1635#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3
1636#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1637#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2
1638#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1639#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1
1640#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1641#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0
1642
1643/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1644#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1645#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7
1646#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1647#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6
1648#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1649#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5
1650#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1651#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4
1652#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1653#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3
1654#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1655#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2
1656#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1657#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1
1658#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1659#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0
1660
1661/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1662#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1663#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2
1664#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1665#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1
1666#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1667#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0
1668
1669/* Bit definitions for ENABLE2_RES_ASSIGN */
1670#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1671#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6
1672#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1673#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1674#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1675#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4
1676#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1677#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3
1678#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1679#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2
1680#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1681#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1
1682#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1683#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0
1684
1685/* Bit definitions for ENABLE2_SMPS_ASSIGN */
1686#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1687#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7
1688#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1689#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6
1690#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1691#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5
1692#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1693#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4
1694#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1695#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3
1696#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1697#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2
1698#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1699#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1
1700#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1701#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0
1702
1703/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1704#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1705#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7
1706#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1707#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6
1708#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1709#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5
1710#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1711#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4
1712#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1713#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3
1714#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1715#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2
1716#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1717#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1
1718#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1719#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0
1720
1721/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1722#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1723#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2
1724#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1725#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1
1726#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1727#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0
1728
1729/* Bit definitions for REGEN3_CTRL */
1730#define PALMAS_REGEN3_CTRL_STATUS 0x10
1731#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4
1732#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1733#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2
1734#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1735#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0
1736
1737/* Registers for function PAD_CONTROL */
1738#define PALMAS_PU_PD_INPUT_CTRL1 0x0
1739#define PALMAS_PU_PD_INPUT_CTRL2 0x1
1740#define PALMAS_PU_PD_INPUT_CTRL3 0x2
1741#define PALMAS_OD_OUTPUT_CTRL 0x4
1742#define PALMAS_POLARITY_CTRL 0x5
1743#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6
1744#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7
1745#define PALMAS_I2C_SPI 0x8
1746#define PALMAS_PU_PD_INPUT_CTRL4 0x9
1747#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA
1748
1749/* Bit definitions for PU_PD_INPUT_CTRL1 */
1750#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1751#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6
1752#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1753#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5
1754#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1755#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4
1756#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1757#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2
1758#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1759#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1
1760
1761/* Bit definitions for PU_PD_INPUT_CTRL2 */
1762#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1763#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5
1764#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1765#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4
1766#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1767#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3
1768#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1769#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2
1770#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1771#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1
1772#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1773#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0
1774
1775/* Bit definitions for PU_PD_INPUT_CTRL3 */
1776#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1777#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6
1778#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1779#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4
1780#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1781#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2
1782#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1783#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0
1784
1785/* Bit definitions for OD_OUTPUT_CTRL */
1786#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1787#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7
1788#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1789#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6
1790#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1791#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5
1792#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1793#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3
1794
1795/* Bit definitions for POLARITY_CTRL */
1796#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1797#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7
1798#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1799#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6
1800#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
1801#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5
1802#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
1803#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4
1804#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
1805#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3
1806#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
1807#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2
1808#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
1809#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1
1810#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
1811#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0
1812
1813/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1814#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
1815#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7
1816#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
1817#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5
1818#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
1819#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3
1820#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
1821#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2
1822#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
1823#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1
1824#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
1825#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0
1826
1827/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1828#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
1829#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4
1830#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
1831#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3
1832#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
1833#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1
1834#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
1835#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0
1836
1837/* Bit definitions for I2C_SPI */
1838#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
1839#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7
1840#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
1841#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6
1842#define PALMAS_I2C_SPI_ID_I2C2 0x20
1843#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5
1844#define PALMAS_I2C_SPI_I2C_SPI 0x10
1845#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4
1846#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f
1847#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0
1848
1849/* Bit definitions for PU_PD_INPUT_CTRL4 */
1850#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
1851#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6
1852#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
1853#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4
1854#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
1855#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2
1856#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
1857#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0
1858
1859/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1860#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
1861#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1
1862#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
1863#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0
1864
1865/* Registers for function LED_PWM */
1866#define PALMAS_LED_PERIOD_CTRL 0x0
1867#define PALMAS_LED_CTRL 0x1
1868#define PALMAS_PWM_CTRL1 0x2
1869#define PALMAS_PWM_CTRL2 0x3
1870
1871/* Bit definitions for LED_PERIOD_CTRL */
1872#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
1873#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3
1874#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
1875#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0
1876
1877/* Bit definitions for LED_CTRL */
1878#define PALMAS_LED_CTRL_LED_2_SEQ 0x20
1879#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5
1880#define PALMAS_LED_CTRL_LED_1_SEQ 0x10
1881#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4
1882#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
1883#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2
1884#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
1885#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0
1886
1887/* Bit definitions for PWM_CTRL1 */
1888#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
1889#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1
1890#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
1891#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0
1892
1893/* Bit definitions for PWM_CTRL2 */
1894#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff
1895#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0
1896
1897/* Registers for function INTERRUPT */
1898#define PALMAS_INT1_STATUS 0x0
1899#define PALMAS_INT1_MASK 0x1
1900#define PALMAS_INT1_LINE_STATE 0x2
1901#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3
1902#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4
1903#define PALMAS_INT2_STATUS 0x5
1904#define PALMAS_INT2_MASK 0x6
1905#define PALMAS_INT2_LINE_STATE 0x7
1906#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8
1907#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9
1908#define PALMAS_INT3_STATUS 0xA
1909#define PALMAS_INT3_MASK 0xB
1910#define PALMAS_INT3_LINE_STATE 0xC
1911#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD
1912#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE
1913#define PALMAS_INT4_STATUS 0xF
1914#define PALMAS_INT4_MASK 0x10
1915#define PALMAS_INT4_LINE_STATE 0x11
1916#define PALMAS_INT4_EDGE_DETECT1 0x12
1917#define PALMAS_INT4_EDGE_DETECT2 0x13
1918#define PALMAS_INT_CTRL 0x14
1919
1920/* Bit definitions for INT1_STATUS */
1921#define PALMAS_INT1_STATUS_VBAT_MON 0x80
1922#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7
1923#define PALMAS_INT1_STATUS_VSYS_MON 0x40
1924#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6
1925#define PALMAS_INT1_STATUS_HOTDIE 0x20
1926#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5
1927#define PALMAS_INT1_STATUS_PWRDOWN 0x10
1928#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4
1929#define PALMAS_INT1_STATUS_RPWRON 0x08
1930#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3
1931#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
1932#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2
1933#define PALMAS_INT1_STATUS_PWRON 0x02
1934#define PALMAS_INT1_STATUS_PWRON_SHIFT 1
1935#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
1936#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0
1937
1938/* Bit definitions for INT1_MASK */
1939#define PALMAS_INT1_MASK_VBAT_MON 0x80
1940#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7
1941#define PALMAS_INT1_MASK_VSYS_MON 0x40
1942#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6
1943#define PALMAS_INT1_MASK_HOTDIE 0x20
1944#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5
1945#define PALMAS_INT1_MASK_PWRDOWN 0x10
1946#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4
1947#define PALMAS_INT1_MASK_RPWRON 0x08
1948#define PALMAS_INT1_MASK_RPWRON_SHIFT 3
1949#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
1950#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2
1951#define PALMAS_INT1_MASK_PWRON 0x02
1952#define PALMAS_INT1_MASK_PWRON_SHIFT 1
1953#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
1954#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0
1955
1956/* Bit definitions for INT1_LINE_STATE */
1957#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
1958#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7
1959#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
1960#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6
1961#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
1962#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5
1963#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
1964#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4
1965#define PALMAS_INT1_LINE_STATE_RPWRON 0x08
1966#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3
1967#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
1968#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2
1969#define PALMAS_INT1_LINE_STATE_PWRON 0x02
1970#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1
1971#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
1972#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0
1973
1974/* Bit definitions for INT2_STATUS */
1975#define PALMAS_INT2_STATUS_VAC_ACOK 0x80
1976#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7
1977#define PALMAS_INT2_STATUS_SHORT 0x40
1978#define PALMAS_INT2_STATUS_SHORT_SHIFT 6
1979#define PALMAS_INT2_STATUS_FBI_BB 0x20
1980#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5
1981#define PALMAS_INT2_STATUS_RESET_IN 0x10
1982#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4
1983#define PALMAS_INT2_STATUS_BATREMOVAL 0x08
1984#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3
1985#define PALMAS_INT2_STATUS_WDT 0x04
1986#define PALMAS_INT2_STATUS_WDT_SHIFT 2
1987#define PALMAS_INT2_STATUS_RTC_TIMER 0x02
1988#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1
1989#define PALMAS_INT2_STATUS_RTC_ALARM 0x01
1990#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0
1991
1992/* Bit definitions for INT2_MASK */
1993#define PALMAS_INT2_MASK_VAC_ACOK 0x80
1994#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7
1995#define PALMAS_INT2_MASK_SHORT 0x40
1996#define PALMAS_INT2_MASK_SHORT_SHIFT 6
1997#define PALMAS_INT2_MASK_FBI_BB 0x20
1998#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5
1999#define PALMAS_INT2_MASK_RESET_IN 0x10
2000#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4
2001#define PALMAS_INT2_MASK_BATREMOVAL 0x08
2002#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3
2003#define PALMAS_INT2_MASK_WDT 0x04
2004#define PALMAS_INT2_MASK_WDT_SHIFT 2
2005#define PALMAS_INT2_MASK_RTC_TIMER 0x02
2006#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1
2007#define PALMAS_INT2_MASK_RTC_ALARM 0x01
2008#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0
2009
2010/* Bit definitions for INT2_LINE_STATE */
2011#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
2012#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7
2013#define PALMAS_INT2_LINE_STATE_SHORT 0x40
2014#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6
2015#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
2016#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5
2017#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
2018#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4
2019#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
2020#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3
2021#define PALMAS_INT2_LINE_STATE_WDT 0x04
2022#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2
2023#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
2024#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1
2025#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
2026#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0
2027
2028/* Bit definitions for INT3_STATUS */
2029#define PALMAS_INT3_STATUS_VBUS 0x80
2030#define PALMAS_INT3_STATUS_VBUS_SHIFT 7
2031#define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2032#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6
2033#define PALMAS_INT3_STATUS_ID 0x20
2034#define PALMAS_INT3_STATUS_ID_SHIFT 5
2035#define PALMAS_INT3_STATUS_ID_OTG 0x10
2036#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4
2037#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2038#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3
2039#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2040#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2
2041#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2042#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1
2043#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2044#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0
2045
2046/* Bit definitions for INT3_MASK */
2047#define PALMAS_INT3_MASK_VBUS 0x80
2048#define PALMAS_INT3_MASK_VBUS_SHIFT 7
2049#define PALMAS_INT3_MASK_VBUS_OTG 0x40
2050#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6
2051#define PALMAS_INT3_MASK_ID 0x20
2052#define PALMAS_INT3_MASK_ID_SHIFT 5
2053#define PALMAS_INT3_MASK_ID_OTG 0x10
2054#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4
2055#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2056#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3
2057#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2058#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2
2059#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2060#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1
2061#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2062#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0
2063
2064/* Bit definitions for INT3_LINE_STATE */
2065#define PALMAS_INT3_LINE_STATE_VBUS 0x80
2066#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7
2067#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2068#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6
2069#define PALMAS_INT3_LINE_STATE_ID 0x20
2070#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5
2071#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2072#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4
2073#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2074#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3
2075#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2076#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2
2077#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2078#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1
2079#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2080#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0
2081
2082/* Bit definitions for INT4_STATUS */
2083#define PALMAS_INT4_STATUS_GPIO_7 0x80
2084#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7
2085#define PALMAS_INT4_STATUS_GPIO_6 0x40
2086#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6
2087#define PALMAS_INT4_STATUS_GPIO_5 0x20
2088#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5
2089#define PALMAS_INT4_STATUS_GPIO_4 0x10
2090#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4
2091#define PALMAS_INT4_STATUS_GPIO_3 0x08
2092#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3
2093#define PALMAS_INT4_STATUS_GPIO_2 0x04
2094#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2
2095#define PALMAS_INT4_STATUS_GPIO_1 0x02
2096#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1
2097#define PALMAS_INT4_STATUS_GPIO_0 0x01
2098#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0
2099
2100/* Bit definitions for INT4_MASK */
2101#define PALMAS_INT4_MASK_GPIO_7 0x80
2102#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7
2103#define PALMAS_INT4_MASK_GPIO_6 0x40
2104#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6
2105#define PALMAS_INT4_MASK_GPIO_5 0x20
2106#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5
2107#define PALMAS_INT4_MASK_GPIO_4 0x10
2108#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4
2109#define PALMAS_INT4_MASK_GPIO_3 0x08
2110#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3
2111#define PALMAS_INT4_MASK_GPIO_2 0x04
2112#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2
2113#define PALMAS_INT4_MASK_GPIO_1 0x02
2114#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1
2115#define PALMAS_INT4_MASK_GPIO_0 0x01
2116#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0
2117
2118/* Bit definitions for INT4_LINE_STATE */
2119#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2120#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7
2121#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2122#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6
2123#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2124#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5
2125#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2126#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4
2127#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2128#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3
2129#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2130#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2
2131#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2132#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1
2133#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2134#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0
2135
2136/* Bit definitions for INT4_EDGE_DETECT1 */
2137#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2138#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7
2139#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2140#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6
2141#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2142#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5
2143#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2144#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4
2145#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2146#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3
2147#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2148#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2
2149#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2150#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1
2151#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2152#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0
2153
2154/* Bit definitions for INT4_EDGE_DETECT2 */
2155#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2156#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7
2157#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2158#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6
2159#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2160#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5
2161#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2162#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4
2163#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2164#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3
2165#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2166#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2
2167#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2168#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1
2169#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2170#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0
2171
2172/* Bit definitions for INT_CTRL */
2173#define PALMAS_INT_CTRL_INT_PENDING 0x04
2174#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2
2175#define PALMAS_INT_CTRL_INT_CLEAR 0x01
2176#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0
2177
2178/* Registers for function USB_OTG */
2179#define PALMAS_USB_WAKEUP 0x3
2180#define PALMAS_USB_VBUS_CTRL_SET 0x4
2181#define PALMAS_USB_VBUS_CTRL_CLR 0x5
2182#define PALMAS_USB_ID_CTRL_SET 0x6
2183#define PALMAS_USB_ID_CTRL_CLEAR 0x7
2184#define PALMAS_USB_VBUS_INT_SRC 0x8
2185#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9
2186#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA
2187#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB
2188#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC
2189#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD
2190#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE
2191#define PALMAS_USB_ID_INT_SRC 0xF
2192#define PALMAS_USB_ID_INT_LATCH_SET 0x10
2193#define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2194#define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2195#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2196#define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2197#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2198#define PALMAS_USB_OTG_ADP_CTRL 0x16
2199#define PALMAS_USB_OTG_ADP_HIGH 0x17
2200#define PALMAS_USB_OTG_ADP_LOW 0x18
2201#define PALMAS_USB_OTG_ADP_RISE 0x19
2202#define PALMAS_USB_OTG_REVISION 0x1A
2203
2204/* Bit definitions for USB_WAKEUP */
2205#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2206#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0
2207
2208/* Bit definitions for USB_VBUS_CTRL_SET */
2209#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2210#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7
2211#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2212#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5
2213#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2214#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4
2215#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2216#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3
2217#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2218#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2
2219
2220/* Bit definitions for USB_VBUS_CTRL_CLR */
2221#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2222#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7
2223#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2224#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5
2225#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2226#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4
2227#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2228#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3
2229#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2230#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2
2231
2232/* Bit definitions for USB_ID_CTRL_SET */
2233#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2234#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7
2235#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2236#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6
2237#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2238#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5
2239#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2240#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4
2241#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2242#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3
2243#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2244#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2
2245
2246/* Bit definitions for USB_ID_CTRL_CLEAR */
2247#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2248#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7
2249#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2250#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6
2251#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2252#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5
2253#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2254#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4
2255#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2256#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3
2257#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2258#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2
2259
2260/* Bit definitions for USB_VBUS_INT_SRC */
2261#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2262#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7
2263#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2264#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6
2265#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2266#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5
2267#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2268#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3
2269#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2270#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2
2271#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2272#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1
2273#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2274#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0
2275
2276/* Bit definitions for USB_VBUS_INT_LATCH_SET */
2277#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2278#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7
2279#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2280#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6
2281#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2282#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5
2283#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2284#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4
2285#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2286#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3
2287#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2288#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2
2289#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2290#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1
2291#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2292#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0
2293
2294/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2295#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2296#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7
2297#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2298#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6
2299#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2300#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5
2301#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2302#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4
2303#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2304#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3
2305#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2306#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2
2307#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2308#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1
2309#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2310#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0
2311
2312/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2313#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2314#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7
2315#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2316#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6
2317#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2318#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5
2319#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2320#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3
2321#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2322#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2
2323#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2324#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1
2325#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2326#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0
2327
2328/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2329#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2330#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7
2331#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2332#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6
2333#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2334#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5
2335#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2336#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3
2337#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2338#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2
2339#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2340#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1
2341#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2342#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0
2343
2344/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2345#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2346#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7
2347#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2348#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6
2349#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2350#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5
2351#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2352#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4
2353#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2354#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3
2355#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2356#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2
2357#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2358#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1
2359#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2360#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0
2361
2362/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2363#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2364#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7
2365#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2366#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6
2367#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2368#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5
2369#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2370#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4
2371#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2372#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3
2373#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2374#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2
2375#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2376#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1
2377#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2378#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0
2379
2380/* Bit definitions for USB_ID_INT_SRC */
2381#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2382#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4
2383#define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2384#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3
2385#define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2386#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2
2387#define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2388#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1
2389#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2390#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0
2391
2392/* Bit definitions for USB_ID_INT_LATCH_SET */
2393#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2394#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4
2395#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2396#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3
2397#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2398#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2
2399#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2400#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1
2401#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2402#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0
2403
2404/* Bit definitions for USB_ID_INT_LATCH_CLR */
2405#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2406#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4
2407#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2408#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3
2409#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2410#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2
2411#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2412#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1
2413#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2414#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0
2415
2416/* Bit definitions for USB_ID_INT_EN_LO_SET */
2417#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2418#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4
2419#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2420#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3
2421#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2422#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2
2423#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2424#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1
2425#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2426#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0
2427
2428/* Bit definitions for USB_ID_INT_EN_LO_CLR */
2429#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2430#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4
2431#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2432#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3
2433#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2434#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2
2435#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2436#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1
2437#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2438#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0
2439
2440/* Bit definitions for USB_ID_INT_EN_HI_SET */
2441#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2442#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4
2443#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2444#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3
2445#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2446#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2
2447#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2448#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1
2449#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2450#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0
2451
2452/* Bit definitions for USB_ID_INT_EN_HI_CLR */
2453#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2454#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4
2455#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2456#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3
2457#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2458#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2
2459#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2460#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1
2461#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2462#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0
2463
2464/* Bit definitions for USB_OTG_ADP_CTRL */
2465#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2466#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2
2467#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2468#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0
2469
2470/* Bit definitions for USB_OTG_ADP_HIGH */
2471#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff
2472#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0
2473
2474/* Bit definitions for USB_OTG_ADP_LOW */
2475#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff
2476#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0
2477
2478/* Bit definitions for USB_OTG_ADP_RISE */
2479#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff
2480#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0
2481
2482/* Bit definitions for USB_OTG_REVISION */
2483#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2484#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0
2485
2486/* Registers for function VIBRATOR */
2487#define PALMAS_VIBRA_CTRL 0x0
2488
2489/* Bit definitions for VIBRA_CTRL */
2490#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2491#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1
2492#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2493#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0
2494
2495/* Registers for function GPIO */
2496#define PALMAS_GPIO_DATA_IN 0x0
2497#define PALMAS_GPIO_DATA_DIR 0x1
2498#define PALMAS_GPIO_DATA_OUT 0x2
2499#define PALMAS_GPIO_DEBOUNCE_EN 0x3
2500#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4
2501#define PALMAS_GPIO_SET_DATA_OUT 0x5
2502#define PALMAS_PU_PD_GPIO_CTRL1 0x6
2503#define PALMAS_PU_PD_GPIO_CTRL2 0x7
2504#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8
2505
2506/* Bit definitions for GPIO_DATA_IN */
2507#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2508#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7
2509#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2510#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6
2511#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2512#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5
2513#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2514#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4
2515#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2516#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3
2517#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2518#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2
2519#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2520#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1
2521#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2522#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0
2523
2524/* Bit definitions for GPIO_DATA_DIR */
2525#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2526#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7
2527#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2528#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6
2529#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2530#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5
2531#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2532#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4
2533#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2534#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3
2535#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2536#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2
2537#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2538#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1
2539#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2540#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0
2541
2542/* Bit definitions for GPIO_DATA_OUT */
2543#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2544#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7
2545#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2546#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6
2547#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2548#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5
2549#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2550#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4
2551#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2552#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3
2553#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2554#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2
2555#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2556#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1
2557#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2558#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0
2559
2560/* Bit definitions for GPIO_DEBOUNCE_EN */
2561#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2562#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7
2563#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2564#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6
2565#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2566#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5
2567#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2568#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4
2569#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2570#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3
2571#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2572#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2
2573#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2574#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1
2575#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2576#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0
2577
2578/* Bit definitions for GPIO_CLEAR_DATA_OUT */
2579#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2580#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7
2581#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2582#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6
2583#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2584#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5
2585#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2586#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4
2587#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2588#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3
2589#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2590#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2
2591#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2592#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1
2593#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2594#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0
2595
2596/* Bit definitions for GPIO_SET_DATA_OUT */
2597#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2598#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7
2599#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2600#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6
2601#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2602#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5
2603#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2604#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4
2605#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2606#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3
2607#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2608#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2
2609#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2610#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1
2611#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2612#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0
2613
2614/* Bit definitions for PU_PD_GPIO_CTRL1 */
2615#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2616#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6
2617#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2618#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5
2619#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2620#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4
2621#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2622#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3
2623#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2624#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2
2625#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2626#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0
2627
2628/* Bit definitions for PU_PD_GPIO_CTRL2 */
2629#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2630#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6
2631#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2632#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5
2633#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2634#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4
2635#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2636#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3
2637#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2638#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2
2639#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2640#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1
2641#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2642#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0
2643
2644/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2645#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2646#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5
2647#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2648#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2
2649#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2650#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1
2651
2652/* Registers for function GPADC */
2653#define PALMAS_GPADC_CTRL1 0x0
2654#define PALMAS_GPADC_CTRL2 0x1
2655#define PALMAS_GPADC_RT_CTRL 0x2
2656#define PALMAS_GPADC_AUTO_CTRL 0x3
2657#define PALMAS_GPADC_STATUS 0x4
2658#define PALMAS_GPADC_RT_SELECT 0x5
2659#define PALMAS_GPADC_RT_CONV0_LSB 0x6
2660#define PALMAS_GPADC_RT_CONV0_MSB 0x7
2661#define PALMAS_GPADC_AUTO_SELECT 0x8
2662#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9
2663#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA
2664#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB
2665#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC
2666#define PALMAS_GPADC_SW_SELECT 0xD
2667#define PALMAS_GPADC_SW_CONV0_LSB 0xE
2668#define PALMAS_GPADC_SW_CONV0_MSB 0xF
2669#define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2670#define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2671#define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2672#define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2673#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2674#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2675
2676/* Bit definitions for GPADC_CTRL1 */
2677#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2678#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6
2679#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2680#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4
2681#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2682#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2
2683#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2684#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1
2685#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2686#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0
2687
2688/* Bit definitions for GPADC_CTRL2 */
2689#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2690#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1
2691
2692/* Bit definitions for GPADC_RT_CTRL */
2693#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2694#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1
2695#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2696#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0
2697
2698/* Bit definitions for GPADC_AUTO_CTRL */
2699#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2700#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7
2701#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2702#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6
2703#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2704#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5
2705#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2706#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4
2707#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f
2708#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0
2709
2710/* Bit definitions for GPADC_STATUS */
2711#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2712#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4
2713
2714/* Bit definitions for GPADC_RT_SELECT */
2715#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2716#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7
2717#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f
2718#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0
2719
2720/* Bit definitions for GPADC_RT_CONV0_LSB */
2721#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff
2722#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0
2723
2724/* Bit definitions for GPADC_RT_CONV0_MSB */
2725#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f
2726#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0
2727
2728/* Bit definitions for GPADC_AUTO_SELECT */
2729#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0
2730#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4
2731#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f
2732#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0
2733
2734/* Bit definitions for GPADC_AUTO_CONV0_LSB */
2735#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff
2736#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0
2737
2738/* Bit definitions for GPADC_AUTO_CONV0_MSB */
2739#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f
2740#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0
2741
2742/* Bit definitions for GPADC_AUTO_CONV1_LSB */
2743#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff
2744#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0
2745
2746/* Bit definitions for GPADC_AUTO_CONV1_MSB */
2747#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f
2748#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0
2749
2750/* Bit definitions for GPADC_SW_SELECT */
2751#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2752#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7
2753#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2754#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4
2755#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f
2756#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0
2757
2758/* Bit definitions for GPADC_SW_CONV0_LSB */
2759#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff
2760#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0
2761
2762/* Bit definitions for GPADC_SW_CONV0_MSB */
2763#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f
2764#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0
2765
2766/* Bit definitions for GPADC_THRES_CONV0_LSB */
2767#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff
2768#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0
2769
2770/* Bit definitions for GPADC_THRES_CONV0_MSB */
2771#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2772#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7
2773#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f
2774#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0
2775
2776/* Bit definitions for GPADC_THRES_CONV1_LSB */
2777#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff
2778#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0
2779
2780/* Bit definitions for GPADC_THRES_CONV1_MSB */
2781#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2782#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7
2783#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f
2784#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0
2785
2786/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2787#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2788#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5
2789#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2790#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4
2791#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f
2792#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0
2793
2794/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2795#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
2796#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7
2797#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f
2798#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0
2799
2800/* Registers for function GPADC */
2801#define PALMAS_GPADC_TRIM1 0x0
2802#define PALMAS_GPADC_TRIM2 0x1
2803#define PALMAS_GPADC_TRIM3 0x2
2804#define PALMAS_GPADC_TRIM4 0x3
2805#define PALMAS_GPADC_TRIM5 0x4
2806#define PALMAS_GPADC_TRIM6 0x5
2807#define PALMAS_GPADC_TRIM7 0x6
2808#define PALMAS_GPADC_TRIM8 0x7
2809#define PALMAS_GPADC_TRIM9 0x8
2810#define PALMAS_GPADC_TRIM10 0x9
2811#define PALMAS_GPADC_TRIM11 0xA
2812#define PALMAS_GPADC_TRIM12 0xB
2813#define PALMAS_GPADC_TRIM13 0xC
2814#define PALMAS_GPADC_TRIM14 0xD
2815#define PALMAS_GPADC_TRIM15 0xE
2816#define PALMAS_GPADC_TRIM16 0xF
2817
Laxman Dewangan60c185f2013-01-03 16:16:58 +0530[diff] [blame]2818static inline int palmas_read(struct palmas *palmas, unsigned int base,
2819 unsigned int reg, unsigned int *val)
2820{
2821 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2822 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2823
2824 return regmap_read(palmas->regmap[slave_id], addr, val);
2825}
2826
2827static inline int palmas_write(struct palmas *palmas, unsigned int base,
2828 unsigned int reg, unsigned int value)
2829{
2830 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2831 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2832
2833 return regmap_write(palmas->regmap[slave_id], addr, value);
2834}
2835
2836static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2837 unsigned int reg, const void *val, size_t val_count)
2838{
2839 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2840 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2841
2842 return regmap_bulk_write(palmas->regmap[slave_id], addr,
2843 val, val_count);
2844}
2845
2846static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2847 unsigned int reg, void *val, size_t val_count)
2848{
2849 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2850 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2851
2852 return regmap_bulk_read(palmas->regmap[slave_id], addr,
2853 val, val_count);
2854}
2855
2856static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2857 unsigned int reg, unsigned int mask, unsigned int val)
2858{
2859 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2860 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2861
2862 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2863}
2864
2865static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2866{
2867 return regmap_irq_get_virq(palmas->irq_data, irq);
2868}
2869
Graeme Gregory2945fbc2012-05-15 15:48:56 +0900[diff] [blame]2870#endif /* __LINUX_MFD_PALMAS_H */