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gerrit-public.fairphone.software / kernel / msm-4.19 / b821d298f8864dc3c3d42643812df43289159507 / . / arch / arm / boot / dts / imx6qdl-zii-rdu2.dtsi
blob: 5d94b5ee6aa0c992cdfc09bc0a4fe1a3a7a9aa2a [file] [log] [blame]
Lucas Stachd7637622017-03-23 15:24:29 +0100[diff] [blame]1/*
2 * Copyright (C) 2016-2017 Zodiac Inflight Innovations
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/sound/fsl-imx-audmux.h>
44
45/ {
46 chosen {
47 stdout-path = &uart1;
48 };
49
50 aliases {
51 mdio-gpio0 = &mdio1;
52 };
53
54 mdio1: mdio {
55 compatible = "virtual,mdio-gpio";
56 #address-cells = <1>;
57 #size-cells = <0>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_mdio1>;
60 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
61 &gpio6 4 GPIO_ACTIVE_HIGH>;
62 };
63
64 reg_28p0v: regulator-28p0v {
65 compatible = "regulator-fixed";
66 regulator-name = "28V_IN";
67 regulator-min-microvolt = <28000000>;
68 regulator-max-microvolt = <28000000>;
69 regulator-always-on;
70 };
71
72 reg_12p0v: regulator-12p0v {
73 compatible = "regulator-fixed";
74 vin-supply = <&reg_28p0v>;
75 regulator-name = "12V_MAIN";
76 regulator-min-microvolt = <12000000>;
77 regulator-max-microvolt = <12000000>;
78 regulator-always-on;
79 };
80
81 reg_5p0v_main: regulator-5p0v-main {
82 compatible = "regulator-fixed";
83 vin-supply = <&reg_12p0v>;
84 regulator-name = "5V_MAIN";
85 regulator-min-microvolt = <5000000>;
86 regulator-max-microvolt = <5000000>;
87 regulator-always-on;
88 };
89
90 reg_5p0v_user_usb: regulator-5p0v-user-usb {
91 compatible = "regulator-fixed";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_reg_user_usb>;
94 vin-supply = <&reg_5p0v_main>;
95 regulator-name = "5V_USER_USB";
96 regulator-min-microvolt = <5000000>;
97 regulator-max-microvolt = <5000000>;
98 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
99 startup-delay-us = <1000>;
100 };
101
102 reg_3p3v_pmic: regulator-3p3v-pmic {
103 compatible = "regulator-fixed";
104 vin-supply = <&reg_12p0v>;
105 regulator-name = "PMIC_3V3";
106 regulator-min-microvolt = <3300000>;
107 regulator-max-microvolt = <3300000>;
108 regulator-always-on;
109 };
110
111 reg_3p3v: regulator-3p3v {
112 compatible = "regulator-fixed";
113 vin-supply = <&reg_3p3v_pmic>;
114 regulator-name = "GEN_3V3";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 regulator-always-on;
118 };
119
120 reg_3p3v_sd: regulator-3p3v-sd {
121 compatible = "regulator-fixed";
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
124 vin-supply = <&reg_3p3v>;
125 regulator-name = "3V3_SD";
126 regulator-min-microvolt = <3300000>;
127 regulator-max-microvolt = <3300000>;
128 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
129 startup-delay-us = <1000>;
130 enable-active-high;
131 regulator-always-on;
132 };
133
134 reg_3p3v_display: regulator-3p3v-display {
135 compatible = "regulator-fixed";
136 vin-supply = <&reg_12p0v>;
137 regulator-name = "3V3_DISPLAY";
138 regulator-min-microvolt = <3300000>;
139 regulator-max-microvolt = <3300000>;
140 regulator-always-on;
141 };
142
143 reg_3p3v_ssd: regulator-3p3v-ssd {
144 compatible = "regulator-fixed";
145 vin-supply = <&reg_12p0v>;
146 regulator-name = "3V3_SSD";
147 regulator-min-microvolt = <3300000>;
148 regulator-max-microvolt = <3300000>;
149 regulator-always-on;
150 };
151
152 sound1 {
153 compatible = "simple-audio-card";
154 simple-audio-card,name = "Front";
155 simple-audio-card,format = "i2s";
156 simple-audio-card,bitclock-master = <&sound1_codec>;
157 simple-audio-card,frame-master = <&sound1_codec>;
158 simple-audio-card,widgets =
159 "Headphone", "Headphone Jack";
160 simple-audio-card,routing =
161 "Headphone Jack", "HPLEFT",
162 "Headphone Jack", "HPRIGHT",
163 "LEFTIN", "HPL",
164 "RIGHTIN", "HPR";
165 simple-audio-card,aux-devs = <&hpa1>;
166
167 sound1_cpu: simple-audio-card,cpu {
168 sound-dai = <&ssi2>;
169 };
170
171 sound1_codec: simple-audio-card,codec {
172 sound-dai = <&codec1>;
173 clocks = <&cs2000>;
174 };
175 };
176
177 sound2 {
178 compatible = "simple-audio-card";
179 simple-audio-card,name = "Back";
180 simple-audio-card,format = "i2s";
181 simple-audio-card,bitclock-master = <&sound2_codec>;
182 simple-audio-card,frame-master = <&sound2_codec>;
183 simple-audio-card,widgets =
184 "Headphone", "Headphone Jack";
185 simple-audio-card,routing =
186 "Headphone Jack", "HPLEFT",
187 "Headphone Jack", "HPRIGHT",
188 "LEFTIN", "HPL",
189 "RIGHTIN", "HPR";
190 simple-audio-card,aux-devs = <&hpa2>;
191
192 sound2_cpu: simple-audio-card,cpu {
193 sound-dai = <&ssi1>;
194 };
195
196 sound2_codec: simple-audio-card,codec {
197 sound-dai = <&codec2>;
198 clocks = <&cs2000>;
199 };
200 };
201
202 panel {
203 power-supply = <&reg_3p3v_display>;
204 status = "disabled";
205
206 port {
207 panel_in: endpoint {
208 remote-endpoint = <&lvds0_out>;
209 };
210 };
211 };
212
213 disp0: disp0 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "fsl,imx-parallel-display";
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_disp0>;
219 status = "disabled";
220
221 port@0 {
222 reg = <0>;
223
224 disp0_in_0: endpoint {
225 remote-endpoint = <&ipu1_di0_disp0>;
226 };
227 };
228
229 port@1 {
230 reg = <1>;
231
232 disp0_out: endpoint {
233 remote-endpoint = <&tc358767_in>;
234 };
235 };
236 };
237
238 cs2000_ref: cs2000-ref {
239 compatible = "fixed-clock";
240 #clock-cells = <0>;
241 clock-frequency = <24576000>;
242 };
243
244 cs2000_in_dummy: cs2000-in-dummy {
245 compatible = "fixed-clock";
246 #clock-cells = <0>;
247 clock-frequency = <0>;
248 };
249
250 edp_refclk: edp-refclk {
251 compatible = "fixed-clock";
252 #clock-cells = <0>;
253 clock-frequency = <19200000>;
254 };
255};
256
257&reg_arm {
258 vin-supply = <&sw1a_reg>;
259};
260
261&reg_pu {
262 vin-supply = <&sw1c_reg>;
263};
264
265&reg_soc {
266 vin-supply = <&sw1c_reg>;
267};
268
269&ldb {
270 lvds-channel@0 {
271 port@4 {
272 reg = <4>;
273
274 lvds0_out: endpoint {
275 remote-endpoint = <&panel_in>;
276 };
277 };
278 };
279};
280
281&uart1 {
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_uart1>;
284 status = "okay";
285};
286
287&uart3 {
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_uart3>;
290 uart-has-rtscts;
291 linux,rs485-enabled-at-boot-time;
292 status = "okay";
293};
294
295&uart4 {
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_uart4>;
298 status = "okay";
299};
300
301&ecspi1 {
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_ecspi1>;
304 cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
305 status = "okay";
306
307 flash@0 {
308 compatible = "st,m25p128", "jedec,spi-nor";
309 spi-max-frequency = <20000000>;
310 reg = <0>;
311 };
312};
313
314&i2c1 {
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_i2c1>;
317 clock-frequency = <100000>;
318 status = "okay";
319
320 codec2: codec@18 {
321 compatible = "ti,tlv320dac3100";
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_codec2>;
324 reg = <0x18>;
325 #sound-dai-cells = <0>;
326 HPVDD-supply = <&reg_3p3v>;
327 SPRVDD-supply = <&reg_3p3v>;
328 SPLVDD-supply = <&reg_3p3v>;
329 AVDD-supply = <&reg_3p3v>;
330 IOVDD-supply = <&reg_3p3v>;
331 DVDD-supply = <&vgen4_reg>;
332 gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>;
333 };
334
335 accel@1c {
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_accel>;
338 compatible = "fsl,mma8451";
339 reg = <0x1c>;
340 interrupt-parent = <&gpio1>;
341 interrupt-names = "int1", "int2";
342 interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>;
343 };
344
345 hpa2: amp@60 {
346 compatible = "ti,tpa6130a2";
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_tpa2>;
349 reg = <0x60>;
350 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
351 Vdd-supply = <&reg_5p0v_main>;
352 };
353
354 edp-bridge@68 {
355 compatible = "toshiba,tc358767";
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_tc358767>;
358 reg = <0x68>;
359 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
360 clock-names = "ref";
361 clocks = <&edp_refclk>;
362 status = "disabled";
363
364 ports {
365 #address-cells = <1>;
366 #size-cells = <0>;
367
368 port@1 {
369 reg = <1>;
370
371 tc358767_in: endpoint {
372 remote-endpoint = <&disp0_out>;
373 };
374 };
375 };
376 };
377};
378
379&i2c2 {
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_i2c2>;
382 clock-frequency = <100000>;
383 status = "okay";
384
385 pmic@08 {
386 compatible = "fsl,pfuze100";
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_pfuze100_irq>;
389 reg = <0x08>;
390 interrupt-parent = <&gpio7>;
391 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
392
393 regulators {
394 sw1a_reg: sw1ab {
395 regulator-min-microvolt = <300000>;
396 regulator-max-microvolt = <1875000>;
397 regulator-boot-on;
398 regulator-always-on;
399 regulator-ramp-delay = <6250>;
400 };
401
402 sw1c_reg: sw1c {
403 regulator-min-microvolt = <300000>;
404 regulator-max-microvolt = <1875000>;
405 regulator-boot-on;
406 regulator-always-on;
407 regulator-ramp-delay = <6250>;
408 };
409
410 sw2_reg: sw2 {
411 regulator-min-microvolt = <800000>;
412 regulator-max-microvolt = <3000000>;
413 regulator-boot-on;
414 regulator-always-on;
415 };
416
417 sw3a_reg: sw3a {
418 regulator-min-microvolt = <400000>;
419 regulator-max-microvolt = <1500000>;
420 regulator-boot-on;
421 regulator-always-on;
422 };
423
424 sw3b_reg: sw3b {
425 regulator-min-microvolt = <400000>;
426 regulator-max-microvolt = <1500000>;
427 regulator-boot-on;
428 regulator-always-on;
429 };
430
431 sw4_reg: sw4 {
432 regulator-min-microvolt = <800000>;
433 regulator-max-microvolt = <1800000>;
434 regulator-boot-on;
435 regulator-always-on;
436 };
437
438 snvs_reg: vsnvs {
439 regulator-min-microvolt = <1000000>;
440 regulator-max-microvolt = <3000000>;
441 regulator-boot-on;
442 regulator-always-on;
443 };
444
445 vref_reg: vrefddr {
446 regulator-boot-on;
447 regulator-always-on;
448 };
449
450 vgen2_reg: vgen2 {
451 regulator-min-microvolt = <1000000>;
452 regulator-max-microvolt = <1500000>;
453 regulator-always-on;
454 };
455
456 vgen4_reg: vgen4 {
457 regulator-min-microvolt = <1200000>;
458 regulator-max-microvolt = <1800000>;
459 regulator-always-on;
460 };
461
462 vgen5_reg: vgen5 {
463 regulator-min-microvolt = <1800000>;
464 regulator-max-microvolt = <2500000>;
465 regulator-always-on;
466 };
467
468 vgen6_reg: vgen6 {
469 regulator-min-microvolt = <1800000>;
470 regulator-max-microvolt = <2800000>;
471 regulator-always-on;
472 };
473 };
474 };
475
476 temp-sense@48 {
477 compatible = "national,lm75";
478 reg = <0x48>;
479 };
480
481 cs2000: clkgen@4e {
482 compatible = "cirrus,cs2000-cp";
483 reg = <0x4e>;
484 #clock-cells = <0>;
485 clock-names = "clk_in", "ref_clk";
486 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
487 assigned-clocks = <&cs2000>;
488 assigned-clock-rates = <24000000>;
489 };
490
491 eeprom@54 {
492 compatible = "at,24c128";
493 reg = <0x54>;
494 };
495
496 rtc@68 {
497 compatible = "dallas,ds1341";
498 reg = <0x68>;
499 };
500};
501
502&i2c3 {
503 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_i2c3>;
505 clock-frequency = <400000>;
506 status = "okay";
507
508 codec1: codec@18 {
509 compatible = "ti,tlv320dac3100";
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_codec1>;
512 reg = <0x18>;
513 #sound-dai-cells = <0>;
514 HPVDD-supply = <&reg_3p3v>;
515 SPRVDD-supply = <&reg_3p3v>;
516 SPLVDD-supply = <&reg_3p3v>;
517 AVDD-supply = <&reg_3p3v>;
518 IOVDD-supply = <&reg_3p3v>;
519 DVDD-supply = <&vgen4_reg>;
520 gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>;
521 };
522
523 touchscreen@20 {
524 compatible = "syna,rmi4-i2c";
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_ts>;
527 reg = <0x20>;
528 interrupt-parent = <&gpio1>;
529 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
530 vdd-supply = <&reg_5p0v_main>;
531 vio-supply = <&reg_3p3v>;
532
533 #address-cells = <1>;
534 #size-cells = <0>;
535
536 rmi4-f01@1 {
537 reg = <0x1>;
538 syna,nosleep-mode = <1>;
539 };
540
541 rmi4-f11@11 {
542 reg = <0x11>;
543 touchscreen-inverted-y;
544 touchscreen-swapped-x-y;
545 syna,sensor-type = <1>;
546 };
547
548 rmi4-f12@12 {
549 reg = <0x12>;
550 touchscreen-inverted-y;
551 touchscreen-swapped-x-y;
552 syna,sensor-type = <1>;
553 };
554 };
555
556 hpa1: amp@60 {
557 compatible = "ti,tpa6130a2";
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_tpa1>;
560 reg = <0x60>;
561 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
562 Vdd-supply = <&reg_5p0v_main>;
563 };
564};
565
566&ipu1_di0_disp0 {
567 remote-endpoint = <&disp0_in_0>;
568};
569
570&pcie {
571 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_pcie>;
573 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
574 status = "okay";
575};
576
577&usdhc2 {
578 pinctrl-names = "default";
579 pinctrl-0 = <&pinctrl_usdhc2>;
580 bus-width = <4>;
581 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
582 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
583 vmmc-supply = <&reg_3p3v_sd>;
584 vqmmc-supply = <&reg_3p3v>;
585 status = "okay";
586};
587
588&usdhc3 {
589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_usdhc3>;
591 bus-width = <4>;
592 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
593 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
594 vmmc-supply = <&reg_3p3v_sd>;
595 vqmmc-supply = <&reg_3p3v>;
596 status = "okay";
597};
598
599&usdhc4 {
600 pinctrl-names = "default";
601 pinctrl-0 = <&pinctrl_usdhc4>;
602 bus-width = <8>;
603 vmmc-supply = <&reg_3p3v>;
604 vqmmc-supply = <&reg_3p3v>;
605 non-removable;
606 status = "okay";
607};
608
609&sata {
610 target-supply = <&reg_3p3v_ssd>;
611 status = "okay";
612};
613
614&fec {
615 pinctrl-names = "default";
616 pinctrl-0 = <&pinctrl_enet>;
617 phy-mode = "rmii";
618 phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
619 phy-reset-duration = <100>;
620 phy-supply = <&reg_3p3v>;
621 status = "okay";
622
623 fixed-link {
624 speed = <100>;
625 full-duplex;
626 };
627};
628
629&usbh1 {
630 vbus-supply = <&reg_5p0v_main>;
631 status = "okay";
632};
633
634&usbotg {
635 vbus-supply = <&reg_5p0v_user_usb>;
636 disable-over-current;
637 dr_mode = "host";
638 status = "okay";
639};
640
641&ssi1 {
642 status = "okay";
643};
644
645&ssi2 {
646 status = "okay";
647};
648
649&audmux {
650 pinctrl-names = "default";
651 pinctrl-0 = <&pinctrl_audmux>;
652 status = "okay";
653
654 ssi1 {
655 fsl,audmux-port = <0>;
656 fsl,port-config = <
657 (IMX_AUDMUX_V2_PTCR_SYN |
658 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
659 IMX_AUDMUX_V2_PTCR_TCSEL(2) |
660 IMX_AUDMUX_V2_PTCR_TFSDIR |
661 IMX_AUDMUX_V2_PTCR_TCLKDIR)
662 IMX_AUDMUX_V2_PDCR_RXDSEL(2)
663 >;
664 };
665
666 aud3 {
667 fsl,audmux-port = <2>;
668 fsl,port-config = <
669 IMX_AUDMUX_V2_PTCR_SYN
670 IMX_AUDMUX_V2_PDCR_RXDSEL(0)
671 >;
672 };
673
674 ssi2 {
675 fsl,audmux-port = <1>;
676 fsl,port-config = <
677 (IMX_AUDMUX_V2_PTCR_SYN |
678 IMX_AUDMUX_V2_PTCR_TFSEL(4) |
679 IMX_AUDMUX_V2_PTCR_TCSEL(4) |
680 IMX_AUDMUX_V2_PTCR_TFSDIR |
681 IMX_AUDMUX_V2_PTCR_TCLKDIR)
682 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
683 >;
684 };
685
686 aud5 {
687 fsl,audmux-port = <4>;
688 fsl,port-config = <
689 IMX_AUDMUX_V2_PTCR_SYN
690 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
691 >;
692 };
693};
694
695&iomuxc {
696 pinctrl_accel: accelgrp {
697 fsl,pins = <
698 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x4001b000
699 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000
700 >;
701 };
702
703 pinctrl_audmux: audmuxgrp {
704 fsl,pins = <
705 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
706 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
707 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
708 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
709 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0
710 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
711 >;
712 };
713
714 pinctrl_codec1: dac1grp {
715 fsl,pins = <
716 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x40000038
717 >;
718 };
719
720 pinctrl_codec2: dac2grp {
721 fsl,pins = <
722 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x40000038
723 >;
724 };
725
726 pinctrl_disp0: disp0grp {
727 fsl,pins = <
728 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
729 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f9
730 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f9
731 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f9
732 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f9
733 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f9
734 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f9
735 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f9
736 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f9
737 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f9
738 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f9
739 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f9
740 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f9
741 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f9
742 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f9
743 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f9
744 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f9
745 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f9
746 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f9
747 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f9
748 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f9
749 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f9
750 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f9
751 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f9
752 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f9
753 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f9
754 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f9
755 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f9
756 >;
757 };
758
759 pinctrl_ecspi1: ecspi1grp {
760 fsl,pins = <
761 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
762 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
763 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
764 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b1
765 >;
766 };
767
768 pinctrl_enet: enetgrp {
769 fsl,pins = <
770 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x000b1
771 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b1
772 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5
773 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5
774 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0
775 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0
776 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5
777 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5
778 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x40010040
779 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x100b0
780 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
781 >;
782 };
783
784 pinctrl_i2c1: i2c1grp {
785 fsl,pins = <
786 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
787 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
788 >;
789 };
790
791 pinctrl_i2c2: i2c2grp {
792 fsl,pins = <
793 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
794 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
795 >;
796 };
797
798 pinctrl_i2c3: i2c3grp {
799 fsl,pins = <
800 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
801 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
802 >;
803 };
804
805 pinctrl_mdio1: bitbangmdiogrp {
806 fsl,pins = <
807 /* Bitbang MDIO for DEB Switch */
808 MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x4001b030
809 MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40018830
810 >;
811 };
812
813 pinctrl_pcie: pciegrp {
814 fsl,pins = <
815 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x10038
816 >;
817 };
818
819 pinctrl_pfuze100_irq: pfuze100grp {
820 fsl,pins = <
821 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40010000
822 >;
823 };
824
825 pinctrl_reg_3p3v_sd: mmcsupply1grp {
826 fsl,pins = <
827 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x858
828 >;
829 };
830
831 pinctrl_reg_user_usb: usbotggrp {
832 fsl,pins = <
833 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x40000038
834 >;
835 };
836
837 pinctrl_rmii_phy_irq: phygrp {
838 fsl,pins = <
839 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000
840 >;
841 };
842
843 pinctrl_tc358767: tc358767grp {
844 fsl,pins = <
845 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10
846 >;
847 };
848
849 pinctrl_tpa1: tpa6130-1grp {
850 fsl,pins = <
851 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x40000038
852 >;
853 };
854
855 pinctrl_tpa2: tpa6130-2grp {
856 fsl,pins = <
857 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x40000038
858 >;
859 };
860
861 pinctrl_ts: tsgrp {
862 fsl,pins = <
863 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
864 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
865 >;
866 };
867
868 pinctrl_uart1: uart1grp {
869 fsl,pins = <
870 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
871 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
872 >;
873 };
874
875 pinctrl_uart3: uart3grp {
876 fsl,pins = <
877 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
878 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
879 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
880 >;
881 };
882
883 pinctrl_uart4: uart4grp {
884 fsl,pins = <
885 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
886 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
887 >;
888 };
889
890 pinctrl_usdhc2: usdhc2grp {
891 fsl,pins = <
892 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059
893 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
894 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
895 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
896 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
897 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
898 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x40010040
899 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040
900 >;
901 };
902
903 pinctrl_usdhc3: usdhc3grp {
904 fsl,pins = <
905 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x10059
906 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069
907 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
908 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
909 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
910 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
911 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x40010040
912 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040
913
914 >;
915 };
916
917 pinctrl_usdhc4: usdhc4grp {
918 fsl,pins = <
919 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
920 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
921 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
922 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
923 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
924 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
925 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
926 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
927 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
928 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
929 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x1b0b1
930 >;
931 };
932};