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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/sh/drivers/pci/fixups-rts7751r2d.c
3 *
4 * RTS7751R2D PCI fixups
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 Paul Mundt
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
Magnus Dammb8b47bf2009-03-11 15:41:51 +090013#include <linux/pci.h>
Paul Mundt959f85f2006-09-27 16:43:28 +090014#include "pci-sh4.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070015
16#define PCIMCR_MRSET_OFF 0xBFFFFFFF
17#define PCIMCR_RFSH_OFF 0xFFFFFFFB
18
Magnus Dammb8b47bf2009-03-11 15:41:51 +090019int pci_fixup_pcic(struct pci_channel *chan)
Linus Torvalds1da177e2005-04-16 15:20:36 -070020{
21 unsigned long bcr1, mcr;
22
Magnus Damme036eaa2008-02-14 13:52:43 +090023 bcr1 = ctrl_inl(SH7751_BCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070024 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
Magnus Dammb8b47bf2009-03-11 15:41:51 +090025 pci_write_reg(chan, bcr1, SH4_PCIBCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
27 /* Enable all interrupts, so we known what to fix */
Magnus Dammb8b47bf2009-03-11 15:41:51 +090028 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
29 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Magnus Dammb8b47bf2009-03-11 15:41:51 +090031 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
32 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
Magnus Damme036eaa2008-02-14 13:52:43 +090034 mcr = ctrl_inl(SH7751_MCR);
Linus Torvalds1da177e2005-04-16 15:20:36 -070035 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
Magnus Dammb8b47bf2009-03-11 15:41:51 +090036 pci_write_reg(chan, mcr, SH4_PCIMCR);
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Magnus Dammb8b47bf2009-03-11 15:41:51 +090038 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
39 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
40 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
41 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
Paul Mundt959f85f2006-09-27 16:43:28 +090042
Linus Torvalds1da177e2005-04-16 15:20:36 -070043 return 0;
44}