blob: 86854f1abd586cdee975a57081384a62d99518e9 [file] [log] [blame]
Peter De Schrijveradd29e62011-10-12 14:53:05 +03001/dts-v1/;
2
Peter De Schrijveradd29e62011-10-12 14:53:05 +03003/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Ventana evaluation board";
7 compatible = "nvidia,ventana", "nvidia,tegra20";
8
Peter De Schrijveradd29e62011-10-12 14:53:05 +03009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Peter De Schrijveradd29e62011-10-12 14:53:05 +030011 };
12
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060013 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060014 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "spia",
32 "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp", "lm1";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi";
75 };
76 dtf {
77 nvidia,pins = "dtf";
78 nvidia,function = "i2c3";
79 };
80 gmc {
81 nvidia,pins = "gmc";
82 nvidia,function = "uartd";
83 };
84 gmd {
85 nvidia,pins = "gmd";
86 nvidia,function = "sflash";
87 };
88 gpu {
89 nvidia,pins = "gpu";
90 nvidia,function = "pwm";
91 };
92 gpu7 {
93 nvidia,pins = "gpu7";
94 nvidia,function = "rtck";
95 };
96 gpv {
97 nvidia,pins = "gpv", "slxa", "slxk";
98 nvidia,function = "pcie";
99 };
100 hdint {
101 nvidia,pins = "hdint", "pta";
102 nvidia,function = "hdmi";
103 };
104 i2cp {
105 nvidia,pins = "i2cp";
106 nvidia,function = "i2cp";
107 };
108 irrx {
109 nvidia,pins = "irrx", "irtx";
110 nvidia,function = "uartb";
111 };
112 kbca {
113 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
114 "kbce", "kbcf";
115 nvidia,function = "kbc";
116 };
117 lcsn {
118 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
119 "lsdi", "lvp0";
120 nvidia,function = "rsvd4";
121 };
122 ld0 {
123 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
124 "ld5", "ld6", "ld7", "ld8", "ld9",
125 "ld10", "ld11", "ld12", "ld13", "ld14",
126 "ld15", "ld16", "ld17", "ldi", "lhp0",
127 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
128 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
129 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya";
131 };
132 pmc {
133 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on";
135 };
136 rm {
137 nvidia,pins = "rm";
138 nvidia,function = "i2c1";
139 };
140 sdb {
141 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
142 nvidia,function = "sdio3";
143 };
144 sdio1 {
145 nvidia,pins = "sdio1";
146 nvidia,function = "sdio1";
147 };
148 slxd {
149 nvidia,pins = "slxd";
150 nvidia,function = "spdif";
151 };
152 spid {
153 nvidia,pins = "spid", "spie", "spif";
154 nvidia,function = "spi1";
155 };
156 spig {
157 nvidia,pins = "spig", "spih";
158 nvidia,function = "spi2_alt";
159 };
160 uaa {
161 nvidia,pins = "uaa", "uab", "uda";
162 nvidia,function = "ulpi";
163 };
164 uad {
165 nvidia,pins = "uad";
166 nvidia,function = "irda";
167 };
168 uca {
169 nvidia,pins = "uca", "ucb";
170 nvidia,function = "uartc";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "atd",
174 "cdev1", "cdev2", "dap1", "dap2",
175 "dap4", "ddc", "dtf", "gma", "gmc",
176 "gme", "gpu", "gpu7", "i2cp", "irrx",
177 "irtx", "pta", "rm", "sdc", "sdd",
178 "slxc", "slxd", "slxk", "spdi", "spdo",
179 "uac", "uad", "uca", "ucb", "uda";
180 nvidia,pull = <0>;
181 nvidia,tristate = <0>;
182 };
183 conf_ate {
184 nvidia,pins = "ate", "csus", "dap3", "gmd",
185 "gpv", "owc", "spia", "spib", "spic",
186 "spid", "spie", "spig";
187 nvidia,pull = <0>;
188 nvidia,tristate = <1>;
189 };
190 conf_ck32 {
191 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
192 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
193 nvidia,pull = <0>;
194 };
195 conf_crtp {
196 nvidia,pins = "crtp", "gmb", "slxa", "spih";
197 nvidia,pull = <2>;
198 nvidia,tristate = <1>;
199 };
200 conf_dta {
201 nvidia,pins = "dta", "dtb", "dtc", "dtd";
202 nvidia,pull = <1>;
203 nvidia,tristate = <0>;
204 };
205 conf_dte {
206 nvidia,pins = "dte", "spif";
207 nvidia,pull = <1>;
208 nvidia,tristate = <1>;
209 };
210 conf_hdint {
211 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
212 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
213 nvidia,tristate = <1>;
214 };
215 conf_kbca {
216 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
217 "kbce", "kbcf", "sdio1", "uaa", "uab";
218 nvidia,pull = <2>;
219 nvidia,tristate = <0>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
232 "lvp1", "lvs", "pmc", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
240 };
241 };
242
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600243 i2s@70002800 {
244 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600245 };
246
247 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600248 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600249 clock-frequency = <216000000>;
250 };
251
Stephen Warren88950f3b2011-11-21 14:44:09 -0700252 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600253 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700254 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700255
256 wm8903: wm8903@1a {
257 compatible = "wlf,wm8903";
258 reg = <0x1a>;
259 interrupt-parent = <&gpio>;
Stephen Warren95decf82012-05-11 16:11:38 -0600260 interrupts = <187 0x04>;
Stephen Warren797acf72012-01-11 16:09:57 -0700261
262 gpio-controller;
263 #gpio-cells = <2>;
264
265 micdet-cfg = <0>;
266 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600267 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700268 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530269
270 /* ALS and proximity sensor */
271 isl29018@44 {
272 compatible = "isil,isl29018";
273 reg = <0x44>;
274 interrupt-parent = <&gpio>;
275 interrupts = <202 0x04>; /*gpio PZ2 */
276 };
Stephen Warren88950f3b2011-11-21 14:44:09 -0700277 };
278
279 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600280 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700281 clock-frequency = <400000>;
282 };
283
284 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600285 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700286 clock-frequency = <400000>;
287 };
288
289 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600290 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700291 clock-frequency = <400000>;
Stephen Warren017a0102012-06-20 16:53:41 -0600292
293 pmic: tps6586x@34 {
294 compatible = "ti,tps6586x";
295 reg = <0x34>;
296 interrupts = <0 86 0x4>;
297
Stephen Warren44b12ef2012-09-11 11:42:26 -0600298 ti,system-power-controller;
299
Stephen Warren017a0102012-06-20 16:53:41 -0600300 #gpio-cells = <2>;
301 gpio-controller;
302
303 sys-supply = <&vdd_5v0_reg>;
304 vin-sm0-supply = <&sys_reg>;
305 vin-sm1-supply = <&sys_reg>;
306 vin-sm2-supply = <&sys_reg>;
307 vinldo01-supply = <&sm2_reg>;
308 vinldo23-supply = <&sm2_reg>;
309 vinldo4-supply = <&sm2_reg>;
310 vinldo678-supply = <&sm2_reg>;
311 vinldo9-supply = <&sm2_reg>;
312
313 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600314 sys_reg: sys {
Stephen Warren017a0102012-06-20 16:53:41 -0600315 regulator-name = "vdd_sys";
316 regulator-always-on;
317 };
318
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600319 sm0 {
Stephen Warren017a0102012-06-20 16:53:41 -0600320 regulator-name = "vdd_sm0,vdd_core";
321 regulator-min-microvolt = <1200000>;
322 regulator-max-microvolt = <1200000>;
323 regulator-always-on;
324 };
325
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600326 sm1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600327 regulator-name = "vdd_sm1,vdd_cpu";
328 regulator-min-microvolt = <1000000>;
329 regulator-max-microvolt = <1000000>;
330 regulator-always-on;
331 };
332
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600333 sm2_reg: sm2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600334 regulator-name = "vdd_sm2,vin_ldo*";
335 regulator-min-microvolt = <3700000>;
336 regulator-max-microvolt = <3700000>;
337 regulator-always-on;
338 };
339
340 /* LDO0 is not connected to anything */
341
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600342 ldo1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600343 regulator-name = "vdd_ldo1,avdd_pll*";
344 regulator-min-microvolt = <1100000>;
345 regulator-max-microvolt = <1100000>;
346 regulator-always-on;
347 };
348
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600349 ldo2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600350 regulator-name = "vdd_ldo2,vdd_rtc";
351 regulator-min-microvolt = <1200000>;
352 regulator-max-microvolt = <1200000>;
353 };
354
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600355 ldo3 {
Stephen Warren017a0102012-06-20 16:53:41 -0600356 regulator-name = "vdd_ldo3,avdd_usb*";
357 regulator-min-microvolt = <3300000>;
358 regulator-max-microvolt = <3300000>;
359 regulator-always-on;
360 };
361
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600362 ldo4 {
Stephen Warren017a0102012-06-20 16:53:41 -0600363 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
364 regulator-min-microvolt = <1800000>;
365 regulator-max-microvolt = <1800000>;
366 regulator-always-on;
367 };
368
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600369 ldo5 {
Stephen Warren017a0102012-06-20 16:53:41 -0600370 regulator-name = "vdd_ldo5,vcore_mmc";
371 regulator-min-microvolt = <2850000>;
372 regulator-max-microvolt = <2850000>;
373 regulator-always-on;
374 };
375
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600376 ldo6 {
Stephen Warren017a0102012-06-20 16:53:41 -0600377 regulator-name = "vdd_ldo6,avdd_vdac";
378 regulator-min-microvolt = <1800000>;
379 regulator-max-microvolt = <1800000>;
380 };
381
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600382 ldo7 {
Stephen Warren017a0102012-06-20 16:53:41 -0600383 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
384 regulator-min-microvolt = <3300000>;
385 regulator-max-microvolt = <3300000>;
386 };
387
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600388 ldo8 {
Stephen Warren017a0102012-06-20 16:53:41 -0600389 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
390 regulator-min-microvolt = <1800000>;
391 regulator-max-microvolt = <1800000>;
392 };
393
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600394 ldo9 {
Stephen Warren017a0102012-06-20 16:53:41 -0600395 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
396 regulator-min-microvolt = <2850000>;
397 regulator-max-microvolt = <2850000>;
398 regulator-always-on;
399 };
400
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600401 ldo_rtc {
Stephen Warren017a0102012-06-20 16:53:41 -0600402 regulator-name = "vdd_rtc_out,vdd_cell";
403 regulator-min-microvolt = <3300000>;
404 regulator-max-microvolt = <3300000>;
405 regulator-always-on;
406 };
407 };
408 };
409 };
410
411 pmc {
412 nvidia,invert-interrupt;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700413 };
414
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600415 usb@c5000000 {
416 status = "okay";
417 };
418
Stephen Warrenc04abb32012-05-11 17:03:26 -0600419 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600420 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600421 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
422 };
423
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600424 usb@c5008000 {
425 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600426 };
427
428 sdhci@c8000400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600429 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600430 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
431 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
432 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200433 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600434 };
435
436 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600437 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200438 bus-width = <8>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600439 };
440
Stephen Warren017a0102012-06-20 16:53:41 -0600441 regulators {
442 compatible = "simple-bus";
443 #address-cells = <1>;
444 #size-cells = <0>;
445
446 vdd_5v0_reg: regulator@0 {
447 compatible = "regulator-fixed";
448 reg = <0>;
449 regulator-name = "vdd_5v0";
450 regulator-min-microvolt = <5000000>;
451 regulator-max-microvolt = <5000000>;
452 regulator-always-on;
453 };
454
455 regulator@1 {
456 compatible = "regulator-fixed";
457 reg = <1>;
458 regulator-name = "vdd_1v5";
459 regulator-min-microvolt = <1500000>;
460 regulator-max-microvolt = <1500000>;
461 gpio = <&pmic 0 0>;
462 };
463
464 regulator@2 {
465 compatible = "regulator-fixed";
466 reg = <2>;
467 regulator-name = "vdd_1v2";
468 regulator-min-microvolt = <1200000>;
469 regulator-max-microvolt = <1200000>;
470 gpio = <&pmic 1 0>;
471 enable-active-high;
472 };
473
474 regulator@3 {
475 compatible = "regulator-fixed";
476 reg = <3>;
477 regulator-name = "vdd_pnl";
478 regulator-min-microvolt = <2800000>;
479 regulator-max-microvolt = <2800000>;
480 gpio = <&gpio 22 0>; /* gpio PC6 */
481 enable-active-high;
482 };
483
484 regulator@4 {
485 compatible = "regulator-fixed";
486 reg = <4>;
487 regulator-name = "vdd_bl";
488 regulator-min-microvolt = <2800000>;
489 regulator-max-microvolt = <2800000>;
490 gpio = <&gpio 176 0>; /* gpio PW0 */
491 enable-active-high;
492 };
493 };
494
Stephen Warren797acf72012-01-11 16:09:57 -0700495 sound {
496 compatible = "nvidia,tegra-audio-wm8903-ventana",
497 "nvidia,tegra-audio-wm8903";
498 nvidia,model = "NVIDIA Tegra Ventana";
499
500 nvidia,audio-routing =
501 "Headphone Jack", "HPOUTR",
502 "Headphone Jack", "HPOUTL",
503 "Int Spk", "ROP",
504 "Int Spk", "RON",
505 "Int Spk", "LOP",
506 "Int Spk", "LON",
507 "Mic Jack", "MICBIAS",
508 "IN1L", "Mic Jack";
509
510 nvidia,i2s-controller = <&tegra_i2s1>;
511 nvidia,audio-codec = <&wm8903>;
512
513 nvidia,spkr-en-gpios = <&wm8903 2 0>;
514 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
Stephen Warrenc44e4382012-05-11 16:21:10 -0600515 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
Stephen Warren797acf72012-01-11 16:09:57 -0700516 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
517 };
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300518};