| Kukjin Kim | dc98e41 | 2011-09-28 20:48:52 +0900 | [diff] [blame] | 1 | /* arch/arm/plat-samsung/include/plat/regs-dma.h |
| 2 | * |
| 3 | * Copyright (C) 2003-2006 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * |
| 6 | * Samsung S3C24XX DMA support |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __ASM_PLAT_REGS_DMA_H |
| 14 | #define __ASM_PLAT_REGS_DMA_H __FILE__ |
| 15 | |
| 16 | #define S3C2410_DMA_DISRC (0x00) |
| 17 | #define S3C2410_DMA_DISRCC (0x04) |
| 18 | #define S3C2410_DMA_DIDST (0x08) |
| 19 | #define S3C2410_DMA_DIDSTC (0x0C) |
| 20 | #define S3C2410_DMA_DCON (0x10) |
| 21 | #define S3C2410_DMA_DSTAT (0x14) |
| 22 | #define S3C2410_DMA_DCSRC (0x18) |
| 23 | #define S3C2410_DMA_DCDST (0x1C) |
| 24 | #define S3C2410_DMA_DMASKTRIG (0x20) |
| 25 | #define S3C2412_DMA_DMAREQSEL (0x24) |
| 26 | #define S3C2443_DMA_DMAREQSEL (0x24) |
| 27 | |
| 28 | #define S3C2410_DISRCC_INC (1 << 0) |
| 29 | #define S3C2410_DISRCC_APB (1 << 1) |
| 30 | |
| 31 | #define S3C2410_DMASKTRIG_STOP (1 << 2) |
| 32 | #define S3C2410_DMASKTRIG_ON (1 << 1) |
| 33 | #define S3C2410_DMASKTRIG_SWTRIG (1 << 0) |
| 34 | |
| 35 | #define S3C2410_DCON_DEMAND (0 << 31) |
| 36 | #define S3C2410_DCON_HANDSHAKE (1 << 31) |
| 37 | #define S3C2410_DCON_SYNC_PCLK (0 << 30) |
| 38 | #define S3C2410_DCON_SYNC_HCLK (1 << 30) |
| 39 | |
| 40 | #define S3C2410_DCON_INTREQ (1 << 29) |
| 41 | |
| 42 | #define S3C2410_DCON_CH0_XDREQ0 (0 << 24) |
| 43 | #define S3C2410_DCON_CH0_UART0 (1 << 24) |
| 44 | #define S3C2410_DCON_CH0_SDI (2 << 24) |
| 45 | #define S3C2410_DCON_CH0_TIMER (3 << 24) |
| 46 | #define S3C2410_DCON_CH0_USBEP1 (4 << 24) |
| 47 | |
| 48 | #define S3C2410_DCON_CH1_XDREQ1 (0 << 24) |
| 49 | #define S3C2410_DCON_CH1_UART1 (1 << 24) |
| 50 | #define S3C2410_DCON_CH1_I2SSDI (2 << 24) |
| 51 | #define S3C2410_DCON_CH1_SPI (3 << 24) |
| 52 | #define S3C2410_DCON_CH1_USBEP2 (4 << 24) |
| 53 | |
| 54 | #define S3C2410_DCON_CH2_I2SSDO (0 << 24) |
| 55 | #define S3C2410_DCON_CH2_I2SSDI (1 << 24) |
| 56 | #define S3C2410_DCON_CH2_SDI (2 << 24) |
| 57 | #define S3C2410_DCON_CH2_TIMER (3 << 24) |
| 58 | #define S3C2410_DCON_CH2_USBEP3 (4 << 24) |
| 59 | |
| 60 | #define S3C2410_DCON_CH3_UART2 (0 << 24) |
| 61 | #define S3C2410_DCON_CH3_SDI (1 << 24) |
| 62 | #define S3C2410_DCON_CH3_SPI (2 << 24) |
| 63 | #define S3C2410_DCON_CH3_TIMER (3 << 24) |
| 64 | #define S3C2410_DCON_CH3_USBEP4 (4 << 24) |
| 65 | |
| 66 | #define S3C2410_DCON_SRCSHIFT (24) |
| 67 | #define S3C2410_DCON_SRCMASK (7 << 24) |
| 68 | |
| 69 | #define S3C2410_DCON_BYTE (0 << 20) |
| 70 | #define S3C2410_DCON_HALFWORD (1 << 20) |
| 71 | #define S3C2410_DCON_WORD (2 << 20) |
| 72 | |
| 73 | #define S3C2410_DCON_AUTORELOAD (0 << 22) |
| 74 | #define S3C2410_DCON_NORELOAD (1 << 22) |
| 75 | #define S3C2410_DCON_HWTRIG (1 << 23) |
| 76 | |
| 77 | #ifdef CONFIG_CPU_S3C2440 |
| 78 | |
| 79 | #define S3C2440_DIDSTC_CHKINT (1 << 2) |
| 80 | |
| 81 | #define S3C2440_DCON_CH0_I2SSDO (5 << 24) |
| 82 | #define S3C2440_DCON_CH0_PCMIN (6 << 24) |
| 83 | |
| 84 | #define S3C2440_DCON_CH1_PCMOUT (5 << 24) |
| 85 | #define S3C2440_DCON_CH1_SDI (6 << 24) |
| 86 | |
| 87 | #define S3C2440_DCON_CH2_PCMIN (5 << 24) |
| 88 | #define S3C2440_DCON_CH2_MICIN (6 << 24) |
| 89 | |
| 90 | #define S3C2440_DCON_CH3_MICIN (5 << 24) |
| 91 | #define S3C2440_DCON_CH3_PCMOUT (6 << 24) |
| 92 | #endif /* CONFIG_CPU_S3C2440 */ |
| 93 | |
| 94 | #ifdef CONFIG_CPU_S3C2412 |
| 95 | |
| 96 | #define S3C2412_DMAREQSEL_SRC(x) ((x) << 1) |
| 97 | |
| 98 | #define S3C2412_DMAREQSEL_HW (1) |
| 99 | |
| 100 | #define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0) |
| 101 | #define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1) |
| 102 | #define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2) |
| 103 | #define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3) |
| 104 | #define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4) |
| 105 | #define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5) |
| 106 | #define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9) |
| 107 | #define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10) |
| 108 | #define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13) |
| 109 | #define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14) |
| 110 | #define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15) |
| 111 | #define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16) |
| 112 | #define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17) |
| 113 | #define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18) |
| 114 | #define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19) |
| 115 | #define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20) |
| 116 | #define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21) |
| 117 | #define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22) |
| 118 | #define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23) |
| 119 | #define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) |
| 120 | #endif /* CONFIG_CPU_S3C2412 */ |
| 121 | |
| Heiko Stuebner | 46cdaba | 2012-03-07 01:53:17 -0800 | [diff] [blame] | 122 | #if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443) |
| Kukjin Kim | dc98e41 | 2011-09-28 20:48:52 +0900 | [diff] [blame] | 123 | |
| 124 | #define S3C2443_DMAREQSEL_SRC(x) ((x) << 1) |
| 125 | |
| 126 | #define S3C2443_DMAREQSEL_HW (1) |
| 127 | |
| 128 | #define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0) |
| 129 | #define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1) |
| 130 | #define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2) |
| 131 | #define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3) |
| 132 | #define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4) |
| 133 | #define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5) |
| 134 | #define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9) |
| 135 | #define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10) |
| 136 | #define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17) |
| 137 | #define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18) |
| 138 | #define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19) |
| 139 | #define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20) |
| 140 | #define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21) |
| 141 | #define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22) |
| 142 | #define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23) |
| 143 | #define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24) |
| 144 | #define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25) |
| 145 | #define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26) |
| 146 | #define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27) |
| 147 | #define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) |
| 148 | #define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29) |
| 149 | #endif /* CONFIG_CPU_S3C2443 */ |
| 150 | |
| 151 | #endif /* __ASM_PLAT_REGS_DMA_H */ |