| Alexander Shishkin | 39f4034 | 2015-09-22 15:47:14 +0300 | [diff] [blame] | 1 | config INTEL_TH |
| 2 | tristate "Intel(R) Trace Hub controller" |
| 3 | help |
| 4 | Intel(R) Trace Hub (TH) is a set of hardware blocks (subdevices) that |
| 5 | produce, switch and output trace data from multiple hardware and |
| 6 | software sources over several types of trace output ports encoded |
| 7 | in System Trace Protocol (MIPI STPv2) and is intended to perform |
| 8 | full system debugging. |
| 9 | |
| 10 | This option enables intel_th bus and common code used by TH |
| 11 | subdevices to interact with each other and hardware and for |
| 12 | platform glue layers to drive Intel TH devices. |
| 13 | |
| 14 | Say Y here to enable Intel(R) Trace Hub controller support. |
| 15 | |
| 16 | if INTEL_TH |
| 17 | |
| Alexander Shishkin | 2b0b16d | 2015-09-22 15:47:15 +0300 | [diff] [blame] | 18 | config INTEL_TH_PCI |
| 19 | tristate "Intel(R) Trace Hub PCI controller" |
| 20 | depends on PCI |
| 21 | help |
| 22 | Intel(R) Trace Hub may exist as a PCI device. This option enables |
| 23 | support glue layer for PCI-based Intel TH. |
| 24 | |
| 25 | Say Y here to enable PCI Intel TH support. |
| 26 | |
| Alexander Shishkin | b27a6a3 | 2015-09-22 15:47:16 +0300 | [diff] [blame] | 27 | config INTEL_TH_GTH |
| 28 | tristate "Intel(R) Trace Hub Global Trace Hub" |
| 29 | help |
| 30 | Global Trace Hub (GTH) is the central component of the |
| 31 | Intel TH infrastructure and acts as a switch for source |
| 32 | and output devices. This driver is required for other |
| 33 | Intel TH subdevices to initialize. |
| 34 | |
| 35 | Say Y here to enable GTH subdevice of Intel(R) Trace Hub. |
| 36 | |
| Alexander Shishkin | f04e449 | 2015-09-22 15:47:17 +0300 | [diff] [blame] | 37 | config INTEL_TH_STH |
| 38 | tristate "Intel(R) Trace Hub Software Trace Hub support" |
| 39 | depends on STM |
| 40 | help |
| 41 | Software Trace Hub (STH) enables trace data from software |
| 42 | trace sources to be sent out via Intel(R) Trace Hub. It |
| 43 | uses stm class device to interface with its sources. |
| 44 | |
| 45 | Say Y here to enable STH subdevice of Intel(R) Trace Hub. |
| 46 | |
| Alexander Shishkin | ba82664 | 2015-09-22 15:47:18 +0300 | [diff] [blame^] | 47 | config INTEL_TH_MSU |
| 48 | tristate "Intel(R) Trace Hub Memory Storage Unit" |
| 49 | help |
| 50 | Memory Storage Unit (MSU) trace output device enables |
| 51 | storing STP traces to system memory. It supports single |
| 52 | and multiblock modes of operation and provides read() |
| 53 | and mmap() access to the collected data. |
| 54 | |
| 55 | Say Y here to enable MSU output device for Intel TH. |
| 56 | |
| Alexander Shishkin | 39f4034 | 2015-09-22 15:47:14 +0300 | [diff] [blame] | 57 | config INTEL_TH_DEBUG |
| 58 | bool "Intel(R) Trace Hub debugging" |
| 59 | depends on DEBUG_FS |
| 60 | help |
| 61 | Say Y here to enable debugging. |
| 62 | |
| 63 | endif |