blob: bed07d4aab0638c6065f1d1eb87350bf0f0fc428 [file] [log] [blame]
Matt Porter7ff71d62005-09-22 22:31:15 -07001/*
2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
3 *
4 * Copyright (c) 2000-2004 by David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef CONFIG_PCI
22#error "This file is PCI bus glue. CONFIG_PCI must be defined."
23#endif
24
Dirk Brandewie4f683842010-11-17 07:43:09 -080025/* defined here to avoid adding to pci_ids.h for single instance use */
26#define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
27
Matt Porter7ff71d62005-09-22 22:31:15 -070028/*-------------------------------------------------------------------------*/
29
David Brownell18807522005-11-23 15:45:37 -080030/* called after powerup, by probe or system-pm "wakeup" */
31static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
32{
David Brownell18807522005-11-23 15:45:37 -080033 int retval;
David Brownell18807522005-11-23 15:45:37 -080034
David Brownell401feaf2006-01-24 07:15:30 -080035 /* we expect static quirk code to handle the "extended capabilities"
36 * (currently just BIOS handoff) allowed starting with EHCI 0.96
37 */
David Brownell18807522005-11-23 15:45:37 -080038
39 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
40 retval = pci_set_mwi(pdev);
41 if (!retval)
42 ehci_dbg(ehci, "MWI active\n");
43
David Brownell18807522005-11-23 15:45:37 -080044 return 0;
45}
46
Alex Hebaab93a2010-12-21 17:45:46 +080047static int ehci_quirk_amd_hudson(struct ehci_hcd *ehci)
Alex He05570292010-12-07 10:10:08 +080048{
49 struct pci_dev *amd_smbus_dev;
50 u8 rev = 0;
51
52 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
Alex Hebaab93a2010-12-21 17:45:46 +080053 if (amd_smbus_dev) {
54 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
55 if (rev < 0x40) {
56 pci_dev_put(amd_smbus_dev);
57 amd_smbus_dev = NULL;
58 return 0;
59 }
60 } else {
61 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x780b, NULL);
62 if (!amd_smbus_dev)
63 return 0;
64 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
65 if (rev < 0x11 || rev > 0x18) {
66 pci_dev_put(amd_smbus_dev);
67 amd_smbus_dev = NULL;
68 return 0;
69 }
Alex He05570292010-12-07 10:10:08 +080070 }
71
72 if (!amd_nb_dev)
73 amd_nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
Alex He05570292010-12-07 10:10:08 +080074
Alex Hebaab93a2010-12-21 17:45:46 +080075 ehci_info(ehci, "QUIRK: Enable exception for AMD Hudson ASPM\n");
Alex He05570292010-12-07 10:10:08 +080076
77 pci_dev_put(amd_smbus_dev);
78 amd_smbus_dev = NULL;
79
80 return 1;
81}
82
David Brownell8926bfa2005-11-28 08:40:38 -080083/* called during probe() after chip reset completes */
84static int ehci_pci_setup(struct usb_hcd *hcd)
Matt Porter7ff71d62005-09-22 22:31:15 -070085{
David Brownellabcc944802005-11-23 15:45:32 -080086 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
87 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
Andiry Xub09bc6c2008-11-14 11:42:29 +080088 struct pci_dev *p_smbus;
89 u8 rev;
Matt Porter7ff71d62005-09-22 22:31:15 -070090 u32 temp;
David Brownell18807522005-11-23 15:45:37 -080091 int retval;
Matt Porter7ff71d62005-09-22 22:31:15 -070092
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +110093 switch (pdev->vendor) {
94 case PCI_VENDOR_ID_TOSHIBA_2:
95 /* celleb's companion chip */
96 if (pdev->device == 0x01b5) {
97#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
98 ehci->big_endian_mmio = 1;
99#else
100 ehci_warn(ehci,
101 "unsupported big endian Toshiba quirk\n");
102#endif
103 }
104 break;
105 }
106
Matt Porter7ff71d62005-09-22 22:31:15 -0700107 ehci->caps = hcd->regs;
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100108 ehci->regs = hcd->regs +
109 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
110
David Brownellabcc944802005-11-23 15:45:32 -0800111 dbg_hcs_params(ehci, "reset");
112 dbg_hcc_params(ehci, "reset");
Matt Porter7ff71d62005-09-22 22:31:15 -0700113
Paul Sericec32ba302006-06-07 10:23:38 -0700114 /* ehci_init() causes memory for DMA transfers to be
115 * allocated. Thus, any vendor-specific workarounds based on
116 * limiting the type of memory used for DMA transfers must
117 * happen before ehci_init() is called. */
118 switch (pdev->vendor) {
119 case PCI_VENDOR_ID_NVIDIA:
120 /* NVidia reports that certain chips don't handle
121 * QH, ITD, or SITD addresses above 2GB. (But TD,
122 * data buffer, and periodic schedule are normal.)
123 */
124 switch (pdev->device) {
125 case 0x003c: /* MCP04 */
126 case 0x005b: /* CK804 */
127 case 0x00d8: /* CK8 */
128 case 0x00e8: /* CK8S */
129 if (pci_set_consistent_dma_mask(pdev,
Yang Hongyang929a22a2009-04-06 19:01:16 -0700130 DMA_BIT_MASK(31)) < 0)
Paul Sericec32ba302006-06-07 10:23:38 -0700131 ehci_warn(ehci, "can't enable NVidia "
132 "workaround for >2GB RAM\n");
133 break;
134 }
135 break;
136 }
137
Matt Porter7ff71d62005-09-22 22:31:15 -0700138 /* cache this readonly data; minimize chip reads */
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100139 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
Matt Porter7ff71d62005-09-22 22:31:15 -0700140
Alex Hebaab93a2010-12-21 17:45:46 +0800141 if (ehci_quirk_amd_hudson(ehci))
Alex He05570292010-12-07 10:10:08 +0800142 ehci->amd_l1_fix = 1;
143
David Brownell18807522005-11-23 15:45:37 -0800144 retval = ehci_halt(ehci);
145 if (retval)
146 return retval;
147
Andiry Xu3d091a62010-11-08 17:58:35 +0800148 if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) ||
149 (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) {
150 /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
151 * read/write memory space which does not belong to it when
152 * there is NULL pointer with T-bit set to 1 in the frame list
153 * table. To avoid the issue, the frame list link pointer
154 * should always contain a valid pointer to a inactive qh.
155 */
156 ehci->use_dummy_qh = 1;
157 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI "
158 "dummy qh workaround\n");
159 }
160
David Brownell8926bfa2005-11-28 08:40:38 -0800161 /* data structure init */
162 retval = ehci_init(hcd);
163 if (retval)
164 return retval;
165
David Brownellabcc944802005-11-23 15:45:32 -0800166 switch (pdev->vendor) {
David Miller3681d8f2010-04-06 18:26:03 -0700167 case PCI_VENDOR_ID_NEC:
168 ehci->need_io_watchdog = 0;
169 break;
Alek Du403dbd32009-07-13 17:30:41 +0800170 case PCI_VENDOR_ID_INTEL:
171 ehci->need_io_watchdog = 0;
Alan Sternae68a832010-07-14 11:03:23 -0400172 ehci->fs_i_thresh = 1;
Oliver Neukumee4ecb82009-11-27 15:17:59 +0100173 if (pdev->device == 0x27cc) {
174 ehci->broken_periodic = 1;
175 ehci_info(ehci, "using broken periodic workaround\n");
176 }
Alek Dufc928252010-09-06 14:50:57 +0100177 if (pdev->device == 0x0806 || pdev->device == 0x0811
178 || pdev->device == 0x0829) {
179 ehci_info(ehci, "disable lpm for langwell/penwell\n");
180 ehci->has_lpm = 0;
181 }
Dirk Brandewie4f683842010-11-17 07:43:09 -0800182 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) {
183 hcd->has_tt = 1;
184 tdi_reset(ehci);
185 }
Alek Du403dbd32009-07-13 17:30:41 +0800186 break;
David Brownellabcc944802005-11-23 15:45:32 -0800187 case PCI_VENDOR_ID_TDI:
188 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
Alan Stern7329e212008-04-03 18:02:56 -0400189 hcd->has_tt = 1;
David Brownellabcc944802005-11-23 15:45:32 -0800190 tdi_reset(ehci);
191 }
192 break;
193 case PCI_VENDOR_ID_AMD:
194 /* AMD8111 EHCI doesn't work, according to AMD errata */
195 if (pdev->device == 0x7463) {
196 ehci_info(ehci, "ignoring AMD8111 (errata)\n");
David Brownell8926bfa2005-11-28 08:40:38 -0800197 retval = -EIO;
198 goto done;
David Brownellabcc944802005-11-23 15:45:32 -0800199 }
200 break;
201 case PCI_VENDOR_ID_NVIDIA:
David Brownellf8aeb3b2006-01-20 13:55:14 -0800202 switch (pdev->device) {
David Brownellf8aeb3b2006-01-20 13:55:14 -0800203 /* Some NForce2 chips have problems with selective suspend;
204 * fixed in newer silicon.
205 */
206 case 0x0068:
Auke Kok44c10132007-06-08 15:46:36 -0700207 if (pdev->revision < 0xa4)
David Brownellf8aeb3b2006-01-20 13:55:14 -0800208 ehci->no_selective_suspend = 1;
209 break;
Brian J. Tarriconea85b4e72010-11-21 21:15:52 -0800210
211 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
212 * fetching device descriptors unless LPM is disabled.
213 * There are also intermittent problems enumerating
214 * devices with PPCD enabled.
215 */
216 case 0x0d9d:
217 ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89");
218 ehci->has_lpm = 0;
219 ehci->has_ppcd = 0;
220 ehci->command &= ~CMD_PPCEE;
221 break;
Matt Porter7ff71d62005-09-22 22:31:15 -0700222 }
David Brownellabcc944802005-11-23 15:45:32 -0800223 break;
Rene Herman055b93c2008-03-20 00:58:16 -0700224 case PCI_VENDOR_ID_VIA:
225 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
226 u8 tmp;
227
228 /* The VT6212 defaults to a 1 usec EHCI sleep time which
229 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
230 * that sleep time use the conventional 10 usec.
231 */
232 pci_read_config_byte(pdev, 0x4b, &tmp);
233 if (tmp & 0x20)
234 break;
235 pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
236 }
237 break;
Andiry Xub09bc6c2008-11-14 11:42:29 +0800238 case PCI_VENDOR_ID_ATI:
Shane Huang0a99e8a2008-11-25 15:12:33 +0800239 /* SB600 and old version of SB700 have a bug in EHCI controller,
Andiry Xub09bc6c2008-11-14 11:42:29 +0800240 * which causes usb devices lose response in some cases.
241 */
Shane Huang0a99e8a2008-11-25 15:12:33 +0800242 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
Andiry Xub09bc6c2008-11-14 11:42:29 +0800243 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
244 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
245 NULL);
246 if (!p_smbus)
247 break;
248 rev = p_smbus->revision;
Shane Huang0a99e8a2008-11-25 15:12:33 +0800249 if ((pdev->device == 0x4386) || (rev == 0x3a)
250 || (rev == 0x3b)) {
Andiry Xub09bc6c2008-11-14 11:42:29 +0800251 u8 tmp;
Shane Huang0a99e8a2008-11-25 15:12:33 +0800252 ehci_info(ehci, "applying AMD SB600/SB700 USB "
253 "freeze workaround\n");
Andiry Xub09bc6c2008-11-14 11:42:29 +0800254 pci_read_config_byte(pdev, 0x53, &tmp);
255 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
256 }
257 pci_dev_put(p_smbus);
258 }
259 break;
David Brownellabcc944802005-11-23 15:45:32 -0800260 }
Matt Porter7ff71d62005-09-22 22:31:15 -0700261
Jason Wessel8d053c72009-08-20 15:39:54 -0500262 /* optional debug port, normally in the first BAR */
263 temp = pci_find_capability(pdev, 0x0a);
264 if (temp) {
265 pci_read_config_dword(pdev, temp, &temp);
266 temp >>= 16;
267 if ((temp & (3 << 13)) == (1 << 13)) {
268 temp &= 0x1fff;
269 ehci->debug = ehci_to_hcd(ehci)->regs + temp;
270 temp = ehci_readl(ehci, &ehci->debug->control);
271 ehci_info(ehci, "debug port %d%s\n",
272 HCS_DEBUG_PORT(ehci->hcs_params),
273 (temp & DBGP_ENABLED)
274 ? " IN USE"
275 : "");
276 if (!(temp & DBGP_ENABLED))
277 ehci->debug = NULL;
278 }
279 }
280
Marcelo Tosattiaf1c51f2007-08-20 18:13:27 -0700281 ehci_reset(ehci);
Matt Porter7ff71d62005-09-22 22:31:15 -0700282
Matt Porter7ff71d62005-09-22 22:31:15 -0700283 /* at least the Genesys GL880S needs fixup here */
284 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
285 temp &= 0x0f;
286 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
David Brownellabcc944802005-11-23 15:45:32 -0800287 ehci_dbg(ehci, "bogus port configuration: "
Matt Porter7ff71d62005-09-22 22:31:15 -0700288 "cc=%d x pcc=%d < ports=%d\n",
289 HCS_N_CC(ehci->hcs_params),
290 HCS_N_PCC(ehci->hcs_params),
291 HCS_N_PORTS(ehci->hcs_params));
292
David Brownellabcc944802005-11-23 15:45:32 -0800293 switch (pdev->vendor) {
294 case 0x17a0: /* GENESYS */
295 /* GL880S: should be PORTS=2 */
296 temp |= (ehci->hcs_params & ~0xf);
297 ehci->hcs_params = temp;
298 break;
299 case PCI_VENDOR_ID_NVIDIA:
300 /* NF4: should be PCC=10 */
301 break;
Matt Porter7ff71d62005-09-22 22:31:15 -0700302 }
303 }
304
David Brownellabcc944802005-11-23 15:45:32 -0800305 /* Serial Bus Release Number is at PCI 0x60 offset */
306 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
Matt Porter7ff71d62005-09-22 22:31:15 -0700307
Alan Stern6fd90862008-12-17 17:20:38 -0500308 /* Keep this around for a while just in case some EHCI
309 * implementation uses legacy PCI PM support. This test
310 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
311 * been triggered by then.
David Brownell2c1c3c42005-11-07 15:24:46 -0800312 */
313 if (!device_can_wakeup(&pdev->dev)) {
314 u16 port_wake;
315
316 pci_read_config_word(pdev, 0x62, &port_wake);
Alan Stern6fd90862008-12-17 17:20:38 -0500317 if (port_wake & 0x0001) {
318 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
Alan Sternbcca06e2009-01-13 11:35:54 -0500319 device_set_wakeup_capable(&pdev->dev, 1);
Alan Stern6fd90862008-12-17 17:20:38 -0500320 }
David Brownell2c1c3c42005-11-07 15:24:46 -0800321 }
Matt Porter7ff71d62005-09-22 22:31:15 -0700322
David Brownellf8aeb3b2006-01-20 13:55:14 -0800323#ifdef CONFIG_USB_SUSPEND
324 /* REVISIT: the controller works fine for wakeup iff the root hub
325 * itself is "globally" suspended, but usbcore currently doesn't
326 * understand such things.
327 *
328 * System suspend currently expects to be able to suspend the entire
329 * device tree, device-at-a-time. If we failed selective suspend
330 * reports, system suspend would fail; so the root hub code must claim
Anand Gadiyar411c9402009-07-07 15:24:23 +0530331 * success. That's lying to usbcore, and it matters for runtime
David Brownellf8aeb3b2006-01-20 13:55:14 -0800332 * PM scenarios with selective suspend and remote wakeup...
333 */
334 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
335 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
336#endif
337
Alan Sternaff6d182008-04-18 11:11:26 -0400338 ehci_port_power(ehci, 1);
David Brownell18807522005-11-23 15:45:37 -0800339 retval = ehci_pci_reinit(ehci, pdev);
David Brownell8926bfa2005-11-28 08:40:38 -0800340done:
341 return retval;
Matt Porter7ff71d62005-09-22 22:31:15 -0700342}
343
344/*-------------------------------------------------------------------------*/
345
346#ifdef CONFIG_PM
347
348/* suspend/resume, section 4.3 */
349
David Brownellf03c17f2005-11-23 15:45:28 -0800350/* These routines rely on the PCI bus glue
Matt Porter7ff71d62005-09-22 22:31:15 -0700351 * to handle powerdown and wakeup, and currently also on
352 * transceivers that don't need any software attention to set up
353 * the right sort of wakeup.
David Brownellf03c17f2005-11-23 15:45:28 -0800354 * Also they depend on separate root hub suspend/resume.
Matt Porter7ff71d62005-09-22 22:31:15 -0700355 */
356
Alan Stern41472002010-06-25 14:02:14 -0400357static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
Matt Porter7ff71d62005-09-22 22:31:15 -0700358{
David Brownellabcc944802005-11-23 15:45:32 -0800359 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
Benjamin Herrenschmidt8de98402005-11-25 09:59:46 +1100360 unsigned long flags;
361 int rc = 0;
Matt Porter7ff71d62005-09-22 22:31:15 -0700362
David Brownellabcc944802005-11-23 15:45:32 -0800363 if (time_before(jiffies, ehci->next_statechange))
364 msleep(10);
Matt Porter7ff71d62005-09-22 22:31:15 -0700365
Benjamin Herrenschmidt8de98402005-11-25 09:59:46 +1100366 /* Root hub was already suspended. Disable irq emission and
Alan Stern16032c42010-05-12 18:21:35 -0400367 * mark HW unaccessible. The PM and USB cores make sure that
368 * the root hub is either suspended or stopped.
Benjamin Herrenschmidt8de98402005-11-25 09:59:46 +1100369 */
370 spin_lock_irqsave (&ehci->lock, flags);
Alan Stern41472002010-06-25 14:02:14 -0400371 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100372 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
373 (void)ehci_readl(ehci, &ehci->regs->intr_enable);
Benjamin Herrenschmidt8de98402005-11-25 09:59:46 +1100374
375 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
Benjamin Herrenschmidt8de98402005-11-25 09:59:46 +1100376 spin_unlock_irqrestore (&ehci->lock, flags);
377
David Brownellf03c17f2005-11-23 15:45:28 -0800378 // could save FLADJ in case of Vaux power loss
Matt Porter7ff71d62005-09-22 22:31:15 -0700379 // ... we'd only use it to handle clock skew
380
Benjamin Herrenschmidt8de98402005-11-25 09:59:46 +1100381 return rc;
Matt Porter7ff71d62005-09-22 22:31:15 -0700382}
383
Alan Stern6ec4beb2009-04-27 13:33:41 -0400384static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
Matt Porter7ff71d62005-09-22 22:31:15 -0700385{
David Brownellabcc944802005-11-23 15:45:32 -0800386 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
David Brownell18807522005-11-23 15:45:37 -0800387 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
Matt Porter7ff71d62005-09-22 22:31:15 -0700388
David Brownellf03c17f2005-11-23 15:45:28 -0800389 // maybe restore FLADJ
Matt Porter7ff71d62005-09-22 22:31:15 -0700390
David Brownellabcc944802005-11-23 15:45:32 -0800391 if (time_before(jiffies, ehci->next_statechange))
392 msleep(100);
Matt Porter7ff71d62005-09-22 22:31:15 -0700393
Benjamin Herrenschmidt8de98402005-11-25 09:59:46 +1100394 /* Mark hardware accessible again as we are out of D3 state by now */
395 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
396
Alan Stern6ec4beb2009-04-27 13:33:41 -0400397 /* If CF is still set and we aren't resuming from hibernation
398 * then we maintained PCI Vaux power.
Alan Stern8c033562006-11-09 14:42:16 -0500399 * Just undo the effect of ehci_pci_suspend().
Matt Porter7ff71d62005-09-22 22:31:15 -0700400 */
Alan Stern6ec4beb2009-04-27 13:33:41 -0400401 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
402 !hibernated) {
Alan Stern8c033562006-11-09 14:42:16 -0500403 int mask = INTR_MASK;
404
Alan Stern16032c42010-05-12 18:21:35 -0400405 ehci_prepare_ports_for_controller_resume(ehci);
Alan Stern58a97ff2008-04-14 12:17:10 -0400406 if (!hcd->self.root_hub->do_remote_wakeup)
Alan Stern8c033562006-11-09 14:42:16 -0500407 mask &= ~STS_PCD;
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100408 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
409 ehci_readl(ehci, &ehci->regs->intr_enable);
Alan Stern8c033562006-11-09 14:42:16 -0500410 return 0;
David Brownellf03c17f2005-11-23 15:45:28 -0800411 }
412
Alan Stern1c50c312005-11-14 11:45:38 -0500413 usb_root_hub_lost_power(hcd->self.root_hub);
Matt Porter7ff71d62005-09-22 22:31:15 -0700414
415 /* Else reset, to cope with power loss or flush-to-storage
David Brownellf03c17f2005-11-23 15:45:28 -0800416 * style "resume" having let BIOS kick in during reboot.
Matt Porter7ff71d62005-09-22 22:31:15 -0700417 */
David Brownellabcc944802005-11-23 15:45:32 -0800418 (void) ehci_halt(ehci);
419 (void) ehci_reset(ehci);
David Brownell18807522005-11-23 15:45:37 -0800420 (void) ehci_pci_reinit(ehci, pdev);
Matt Porter7ff71d62005-09-22 22:31:15 -0700421
David Brownellf03c17f2005-11-23 15:45:28 -0800422 /* emptying the schedule aborts any urbs */
David Brownellabcc944802005-11-23 15:45:32 -0800423 spin_lock_irq(&ehci->lock);
David Brownellf03c17f2005-11-23 15:45:28 -0800424 if (ehci->reclaim)
Alan Stern07d29b62007-12-11 16:05:30 -0500425 end_unlink_async(ehci);
David Howells7d12e782006-10-05 14:55:46 +0100426 ehci_work(ehci);
David Brownellabcc944802005-11-23 15:45:32 -0800427 spin_unlock_irq(&ehci->lock);
Matt Porter7ff71d62005-09-22 22:31:15 -0700428
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100429 ehci_writel(ehci, ehci->command, &ehci->regs->command);
430 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
431 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
Alan Stern8c033562006-11-09 14:42:16 -0500432
Alan Stern383975d2007-05-04 11:52:40 -0400433 /* here we "know" root ports should always stay powered */
434 ehci_port_power(ehci, 1);
Alan Stern383975d2007-05-04 11:52:40 -0400435
Alan Stern8c033562006-11-09 14:42:16 -0500436 hcd->state = HC_STATE_SUSPENDED;
437 return 0;
Matt Porter7ff71d62005-09-22 22:31:15 -0700438}
439#endif
440
Alek Du48f24972010-06-04 15:47:55 +0800441static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
442{
443 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
444 int rc = 0;
445
446 if (!udev->parent) /* udev is root hub itself, impossible */
447 rc = -1;
448 /* we only support lpm device connected to root hub yet */
449 if (ehci->has_lpm && !udev->parent->parent) {
450 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
451 if (!rc)
452 rc = ehci_lpm_check(ehci, udev->portnum);
453 }
454 return rc;
455}
456
Matt Porter7ff71d62005-09-22 22:31:15 -0700457static const struct hc_driver ehci_pci_hc_driver = {
458 .description = hcd_name,
459 .product_desc = "EHCI Host Controller",
460 .hcd_priv_size = sizeof(struct ehci_hcd),
461
462 /*
463 * generic hardware linkage
464 */
465 .irq = ehci_irq,
466 .flags = HCD_MEMORY | HCD_USB2,
467
468 /*
469 * basic lifecycle operations
470 */
David Brownell8926bfa2005-11-28 08:40:38 -0800471 .reset = ehci_pci_setup,
David Brownell18807522005-11-23 15:45:37 -0800472 .start = ehci_run,
Matt Porter7ff71d62005-09-22 22:31:15 -0700473#ifdef CONFIG_PM
Alan Stern7be7d742008-04-03 18:03:06 -0400474 .pci_suspend = ehci_pci_suspend,
475 .pci_resume = ehci_pci_resume,
Matt Porter7ff71d62005-09-22 22:31:15 -0700476#endif
David Brownell18807522005-11-23 15:45:37 -0800477 .stop = ehci_stop,
Aleksey Gorelov64a21d02006-08-08 17:24:08 -0700478 .shutdown = ehci_shutdown,
Matt Porter7ff71d62005-09-22 22:31:15 -0700479
480 /*
481 * managing i/o requests and associated device resources
482 */
483 .urb_enqueue = ehci_urb_enqueue,
484 .urb_dequeue = ehci_urb_dequeue,
485 .endpoint_disable = ehci_endpoint_disable,
Alan Sternb18ffd42009-05-27 18:21:56 -0400486 .endpoint_reset = ehci_endpoint_reset,
Matt Porter7ff71d62005-09-22 22:31:15 -0700487
488 /*
489 * scheduling support
490 */
491 .get_frame_number = ehci_get_frame,
492
493 /*
494 * root hub support
495 */
496 .hub_status_data = ehci_hub_status_data,
497 .hub_control = ehci_hub_control,
Alan Stern0c0382e2005-10-13 17:08:02 -0400498 .bus_suspend = ehci_bus_suspend,
499 .bus_resume = ehci_bus_resume,
Alan Sterna8e51772008-05-20 16:58:11 -0400500 .relinquish_port = ehci_relinquish_port,
Alan Stern3a311552008-05-20 16:58:29 -0400501 .port_handed_over = ehci_port_handed_over,
Alan Stern914b7012009-06-29 10:47:30 -0400502
Alek Du48f24972010-06-04 15:47:55 +0800503 /*
504 * call back when device connected and addressed
505 */
506 .update_device = ehci_update_device,
507
Alan Stern914b7012009-06-29 10:47:30 -0400508 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
Matt Porter7ff71d62005-09-22 22:31:15 -0700509};
510
511/*-------------------------------------------------------------------------*/
512
513/* PCI driver selection metadata; PCI hotplugging uses this */
514static const struct pci_device_id pci_ids [] = { {
515 /* handle any USB 2.0 EHCI controller */
Jean Delvarec67808e2006-04-09 20:07:35 +0200516 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
Matt Porter7ff71d62005-09-22 22:31:15 -0700517 .driver_data = (unsigned long) &ehci_pci_hc_driver,
518 },
519 { /* end: all zeroes */ }
520};
David Brownellabcc944802005-11-23 15:45:32 -0800521MODULE_DEVICE_TABLE(pci, pci_ids);
Matt Porter7ff71d62005-09-22 22:31:15 -0700522
523/* pci driver glue; this is a "new style" PCI driver module */
524static struct pci_driver ehci_pci_driver = {
525 .name = (char *) hcd_name,
526 .id_table = pci_ids,
Matt Porter7ff71d62005-09-22 22:31:15 -0700527
528 .probe = usb_hcd_pci_probe,
529 .remove = usb_hcd_pci_remove,
Aleksey Gorelov64a21d02006-08-08 17:24:08 -0700530 .shutdown = usb_hcd_pci_shutdown,
Alan Sternabb30642009-04-27 13:33:24 -0400531
532#ifdef CONFIG_PM_SLEEP
533 .driver = {
534 .pm = &usb_hcd_pci_pm_ops
535 },
536#endif
Matt Porter7ff71d62005-09-22 22:31:15 -0700537};