Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 1 | #ifndef _LINUX_IRQDESC_H |
| 2 | #define _LINUX_IRQDESC_H |
| 3 | |
Thomas Gleixner | 425a507 | 2015-12-13 18:02:22 +0100 | [diff] [blame] | 4 | #include <linux/rcupdate.h> |
| 5 | |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 6 | /* |
| 7 | * Core internal functions to deal with irq descriptors |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
Ben Hutchings | cd7eab4 | 2011-01-19 21:01:44 +0000 | [diff] [blame] | 10 | struct irq_affinity_notify; |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 11 | struct proc_dir_entry; |
Paul Gortmaker | ec53cf2 | 2011-09-19 20:33:19 -0400 | [diff] [blame] | 12 | struct module; |
Thomas Gleixner | 293a7a0 | 2012-10-16 15:07:49 -0700 | [diff] [blame] | 13 | struct irq_desc; |
Marc Zyngier | 76ba59f | 2014-08-26 11:03:16 +0100 | [diff] [blame] | 14 | struct irq_domain; |
| 15 | struct pt_regs; |
Thomas Gleixner | 293a7a0 | 2012-10-16 15:07:49 -0700 | [diff] [blame] | 16 | |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 17 | /** |
| 18 | * struct irq_desc - interrupt descriptor |
Jiang Liu | 0d0b4c8 | 2015-06-01 16:05:12 +0800 | [diff] [blame] | 19 | * @irq_common_data: per irq and chip data passed down to chip functions |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 20 | * @kstat_irqs: irq stats per cpu |
Geert Uytterhoeven | 7707677 | 2011-04-10 11:01:52 +0200 | [diff] [blame] | 21 | * @handle_irq: highlevel irq-events handler |
| 22 | * @preflow_handler: handler called before the flow handler (currently used by sparc) |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 23 | * @action: the irq action chain |
| 24 | * @status: status information |
Thomas Gleixner | dbec07b | 2011-02-07 20:19:55 +0100 | [diff] [blame] | 25 | * @core_internal_state__do_not_mess_with_it: core internal status information |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 26 | * @depth: disable-depth, for nested irq_disable() calls |
Geert Uytterhoeven | 0911f12 | 2011-04-10 11:01:51 +0200 | [diff] [blame] | 27 | * @wake_depth: enable depth, for multiple irq_set_irq_wake() callers |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 28 | * @irq_count: stats field to detect stalled irqs |
| 29 | * @last_unhandled: aging timer for unhandled count |
| 30 | * @irqs_unhandled: stats field for spurious unhandled interrupts |
Thomas Gleixner | 1e77d0a | 2013-03-07 14:53:45 +0100 | [diff] [blame] | 31 | * @threads_handled: stats field for deferred spurious detection of threaded handlers |
| 32 | * @threads_handled_last: comparator field for deferred spurious detection of theraded handlers |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 33 | * @lock: locking for SMP |
Geert Uytterhoeven | 7707677 | 2011-04-10 11:01:52 +0200 | [diff] [blame] | 34 | * @affinity_hint: hint to user space for preferred irq affinity |
Ben Hutchings | cd7eab4 | 2011-01-19 21:01:44 +0000 | [diff] [blame] | 35 | * @affinity_notify: context for notification of affinity changes |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 36 | * @pending_mask: pending rebalanced interrupts |
Thomas Gleixner | b5faba2 | 2011-02-23 23:52:13 +0000 | [diff] [blame] | 37 | * @threads_oneshot: bitfield to handle shared oneshot threads |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 38 | * @threads_active: number of irqaction threads currently running |
| 39 | * @wait_for_threads: wait queue for sync_irq to wait for threaded handlers |
Thomas Gleixner | cab303b | 2014-08-28 11:44:31 +0200 | [diff] [blame] | 40 | * @nr_actions: number of installed actions on this descriptor |
| 41 | * @no_suspend_depth: number of irqactions on a irq descriptor with |
| 42 | * IRQF_NO_SUSPEND set |
| 43 | * @force_resume_depth: number of irqactions on a irq descriptor with |
| 44 | * IRQF_FORCE_RESUME set |
Thomas Gleixner | 425a507 | 2015-12-13 18:02:22 +0100 | [diff] [blame] | 45 | * @rcu: rcu head for delayed free |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 46 | * @dir: /proc/irq/ procfs entry |
| 47 | * @name: flow handler name for /proc/interrupts output |
| 48 | */ |
| 49 | struct irq_desc { |
Jiang Liu | 0d0b4c8 | 2015-06-01 16:05:12 +0800 | [diff] [blame] | 50 | struct irq_common_data irq_common_data; |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 51 | struct irq_data irq_data; |
Eric Dumazet | 6c9ae00 | 2011-01-13 15:45:38 -0800 | [diff] [blame] | 52 | unsigned int __percpu *kstat_irqs; |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 53 | irq_flow_handler_t handle_irq; |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 54 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
| 55 | irq_preflow_handler_t preflow_handler; |
| 56 | #endif |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 57 | struct irqaction *action; /* IRQ action list */ |
Thomas Gleixner | a6967ca | 2011-02-10 22:01:25 +0100 | [diff] [blame] | 58 | unsigned int status_use_accessors; |
Thomas Gleixner | dbec07b | 2011-02-07 20:19:55 +0100 | [diff] [blame] | 59 | unsigned int core_internal_state__do_not_mess_with_it; |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 60 | unsigned int depth; /* nested irq disables */ |
| 61 | unsigned int wake_depth; /* nested wake enables */ |
| 62 | unsigned int irq_count; /* For detecting broken IRQs */ |
| 63 | unsigned long last_unhandled; /* Aging timer for unhandled count */ |
| 64 | unsigned int irqs_unhandled; |
Thomas Gleixner | 1e77d0a | 2013-03-07 14:53:45 +0100 | [diff] [blame] | 65 | atomic_t threads_handled; |
| 66 | int threads_handled_last; |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 67 | raw_spinlock_t lock; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 68 | struct cpumask *percpu_enabled; |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 69 | #ifdef CONFIG_SMP |
| 70 | const struct cpumask *affinity_hint; |
Ben Hutchings | cd7eab4 | 2011-01-19 21:01:44 +0000 | [diff] [blame] | 71 | struct irq_affinity_notify *affinity_notify; |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 72 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
| 73 | cpumask_var_t pending_mask; |
| 74 | #endif |
| 75 | #endif |
Thomas Gleixner | b5faba2 | 2011-02-23 23:52:13 +0000 | [diff] [blame] | 76 | unsigned long threads_oneshot; |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 77 | atomic_t threads_active; |
| 78 | wait_queue_head_t wait_for_threads; |
Thomas Gleixner | cab303b | 2014-08-28 11:44:31 +0200 | [diff] [blame] | 79 | #ifdef CONFIG_PM_SLEEP |
| 80 | unsigned int nr_actions; |
| 81 | unsigned int no_suspend_depth; |
Rafael J. Wysocki | 17f4803 | 2015-02-27 00:07:55 +0100 | [diff] [blame] | 82 | unsigned int cond_suspend_depth; |
Thomas Gleixner | cab303b | 2014-08-28 11:44:31 +0200 | [diff] [blame] | 83 | unsigned int force_resume_depth; |
| 84 | #endif |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 85 | #ifdef CONFIG_PROC_FS |
| 86 | struct proc_dir_entry *dir; |
| 87 | #endif |
Thomas Gleixner | 425a507 | 2015-12-13 18:02:22 +0100 | [diff] [blame] | 88 | #ifdef CONFIG_SPARSE_IRQ |
| 89 | struct rcu_head rcu; |
| 90 | #endif |
Thomas Gleixner | 293a7a0 | 2012-10-16 15:07:49 -0700 | [diff] [blame] | 91 | int parent_irq; |
Sebastian Andrzej Siewior | b687380 | 2011-07-11 12:17:31 +0200 | [diff] [blame] | 92 | struct module *owner; |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 93 | const char *name; |
| 94 | } ____cacheline_internodealigned_in_smp; |
| 95 | |
Thomas Gleixner | a899418 | 2015-07-05 17:12:30 +0000 | [diff] [blame] | 96 | #ifdef CONFIG_SPARSE_IRQ |
| 97 | extern void irq_lock_sparse(void); |
| 98 | extern void irq_unlock_sparse(void); |
| 99 | #else |
| 100 | static inline void irq_lock_sparse(void) { } |
| 101 | static inline void irq_unlock_sparse(void) { } |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 102 | extern struct irq_desc irq_desc[NR_IRQS]; |
| 103 | #endif |
| 104 | |
Jiang Liu | 7bbf1dd | 2015-06-01 16:05:10 +0800 | [diff] [blame] | 105 | static inline struct irq_desc *irq_data_to_desc(struct irq_data *data) |
| 106 | { |
Thomas Gleixner | 755d119 | 2015-09-16 14:37:12 +0200 | [diff] [blame] | 107 | return container_of(data->common, struct irq_desc, irq_common_data); |
Jiang Liu | 7bbf1dd | 2015-06-01 16:05:10 +0800 | [diff] [blame] | 108 | } |
| 109 | |
Jiang Liu | 304adf8 | 2015-06-04 12:13:26 +0800 | [diff] [blame] | 110 | static inline unsigned int irq_desc_get_irq(struct irq_desc *desc) |
| 111 | { |
| 112 | return desc->irq_data.irq; |
| 113 | } |
| 114 | |
Thomas Gleixner | d9936bb | 2011-03-11 14:15:35 +0100 | [diff] [blame] | 115 | static inline struct irq_data *irq_desc_get_irq_data(struct irq_desc *desc) |
| 116 | { |
| 117 | return &desc->irq_data; |
| 118 | } |
| 119 | |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 120 | static inline struct irq_chip *irq_desc_get_chip(struct irq_desc *desc) |
| 121 | { |
| 122 | return desc->irq_data.chip; |
| 123 | } |
| 124 | |
| 125 | static inline void *irq_desc_get_chip_data(struct irq_desc *desc) |
| 126 | { |
| 127 | return desc->irq_data.chip_data; |
| 128 | } |
| 129 | |
| 130 | static inline void *irq_desc_get_handler_data(struct irq_desc *desc) |
| 131 | { |
Jiang Liu | af7080e | 2015-06-01 16:05:21 +0800 | [diff] [blame] | 132 | return desc->irq_common_data.handler_data; |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | static inline struct msi_desc *irq_desc_get_msi_desc(struct irq_desc *desc) |
| 136 | { |
Jiang Liu | b237721 | 2015-06-01 16:05:43 +0800 | [diff] [blame] | 137 | return desc->irq_common_data.msi_desc; |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 138 | } |
| 139 | |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 140 | /* |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 141 | * Architectures call this to let the generic IRQ layer |
Huang Shijie | 6584d84 | 2015-09-01 10:35:50 +0800 | [diff] [blame] | 142 | * handle an interrupt. |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 143 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 144 | static inline void generic_handle_irq_desc(struct irq_desc *desc) |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 145 | { |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 146 | desc->handle_irq(desc); |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 147 | } |
| 148 | |
Thomas Gleixner | fe12bc2 | 2011-05-18 12:48:00 +0200 | [diff] [blame] | 149 | int generic_handle_irq(unsigned int irq); |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 150 | |
Marc Zyngier | 76ba59f | 2014-08-26 11:03:16 +0100 | [diff] [blame] | 151 | #ifdef CONFIG_HANDLE_DOMAIN_IRQ |
| 152 | /* |
| 153 | * Convert a HW interrupt number to a logical one using a IRQ domain, |
| 154 | * and handle the result interrupt number. Return -EINVAL if |
| 155 | * conversion failed. Providing a NULL domain indicates that the |
| 156 | * conversion has already been done. |
| 157 | */ |
| 158 | int __handle_domain_irq(struct irq_domain *domain, unsigned int hwirq, |
| 159 | bool lookup, struct pt_regs *regs); |
| 160 | |
| 161 | static inline int handle_domain_irq(struct irq_domain *domain, |
| 162 | unsigned int hwirq, struct pt_regs *regs) |
| 163 | { |
| 164 | return __handle_domain_irq(domain, hwirq, true, regs); |
| 165 | } |
| 166 | #endif |
| 167 | |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 168 | /* Test to see if a driver has successfully requested an irq */ |
Thomas Gleixner | f61ae4f | 2015-08-02 20:38:26 +0000 | [diff] [blame] | 169 | static inline int irq_desc_has_action(struct irq_desc *desc) |
| 170 | { |
| 171 | return desc->action != NULL; |
| 172 | } |
| 173 | |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 174 | static inline int irq_has_action(unsigned int irq) |
| 175 | { |
Thomas Gleixner | f61ae4f | 2015-08-02 20:38:26 +0000 | [diff] [blame] | 176 | return irq_desc_has_action(irq_to_desc(irq)); |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 177 | } |
| 178 | |
Thomas Gleixner | bbc9d21 | 2015-06-23 15:01:30 +0200 | [diff] [blame] | 179 | /** |
| 180 | * irq_set_handler_locked - Set irq handler from a locked region |
| 181 | * @data: Pointer to the irq_data structure which identifies the irq |
| 182 | * @handler: Flow control handler function for this interrupt |
| 183 | * |
| 184 | * Sets the handler in the irq descriptor associated to @data. |
| 185 | * |
| 186 | * Must be called with irq_desc locked and valid parameters. Typical |
| 187 | * call site is the irq_set_type() callback. |
| 188 | */ |
| 189 | static inline void irq_set_handler_locked(struct irq_data *data, |
| 190 | irq_flow_handler_t handler) |
| 191 | { |
| 192 | struct irq_desc *desc = irq_data_to_desc(data); |
| 193 | |
| 194 | desc->handle_irq = handler; |
| 195 | } |
| 196 | |
| 197 | /** |
| 198 | * irq_set_chip_handler_name_locked - Set chip, handler and name from a locked region |
| 199 | * @data: Pointer to the irq_data structure for which the chip is set |
| 200 | * @chip: Pointer to the new irq chip |
| 201 | * @handler: Flow control handler function for this interrupt |
| 202 | * @name: Name of the interrupt |
| 203 | * |
| 204 | * Replace the irq chip at the proper hierarchy level in @data and |
| 205 | * sets the handler and name in the associated irq descriptor. |
| 206 | * |
| 207 | * Must be called with irq_desc locked and valid parameters. |
| 208 | */ |
| 209 | static inline void |
| 210 | irq_set_chip_handler_name_locked(struct irq_data *data, struct irq_chip *chip, |
| 211 | irq_flow_handler_t handler, const char *name) |
| 212 | { |
| 213 | struct irq_desc *desc = irq_data_to_desc(data); |
| 214 | |
| 215 | desc->handle_irq = handler; |
| 216 | desc->name = name; |
| 217 | data->chip = chip; |
| 218 | } |
| 219 | |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 220 | static inline int irq_balancing_disabled(unsigned int irq) |
| 221 | { |
| 222 | struct irq_desc *desc; |
| 223 | |
| 224 | desc = irq_to_desc(irq); |
Thomas Gleixner | 0c6f8a8 | 2011-03-28 13:32:20 +0200 | [diff] [blame] | 225 | return desc->status_use_accessors & IRQ_NO_BALANCING_MASK; |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 226 | } |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 227 | |
Vinayak Kale | 7f4a8e7 | 2013-12-04 10:09:50 +0000 | [diff] [blame] | 228 | static inline int irq_is_percpu(unsigned int irq) |
| 229 | { |
| 230 | struct irq_desc *desc; |
| 231 | |
| 232 | desc = irq_to_desc(irq); |
| 233 | return desc->status_use_accessors & IRQ_PER_CPU; |
| 234 | } |
| 235 | |
Thomas Gleixner | d3e17de | 2011-03-22 17:08:15 +0100 | [diff] [blame] | 236 | static inline void |
| 237 | irq_set_lockdep_class(unsigned int irq, struct lock_class_key *class) |
| 238 | { |
| 239 | struct irq_desc *desc = irq_to_desc(irq); |
| 240 | |
| 241 | if (desc) |
| 242 | lockdep_set_class(&desc->lock, class); |
| 243 | } |
| 244 | |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 245 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
| 246 | static inline void |
| 247 | __irq_set_preflow_handler(unsigned int irq, irq_preflow_handler_t handler) |
| 248 | { |
| 249 | struct irq_desc *desc; |
| 250 | |
| 251 | desc = irq_to_desc(irq); |
| 252 | desc->preflow_handler = handler; |
| 253 | } |
| 254 | #endif |
Thomas Gleixner | e144710 | 2010-10-01 16:03:45 +0200 | [diff] [blame] | 255 | |
| 256 | #endif |