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gerrit-public.fairphone.software / kernel / msm-4.19 / bc71c0961c61d6082472203bfae9596899c9c896 / . / arch / arm / mach-ux500 / include / mach / db8500-regs.h
blob: 1530d493879d534b647d67862fa4073ff2018e26 [file] [log] [blame]
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_DB8500_REGS_H
8#define __MACH_DB8500_REGS_H
9
Linus Walleij7b8ddb02010-05-27 15:21:26 -0700[diff] [blame]10/* Base address and bank offsets for ESRAM */
11#define U8500_ESRAM_BASE 0x40000000
12#define U8500_ESRAM_BANK_SIZE 0x00020000
13#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE
14#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
15#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
16#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
17#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
Linus Walleij32647402011-03-29 17:34:23 +0200[diff] [blame]18/*
19 * on V1 DMA uses 4KB for logical parameters position is right after the 64KB
20 * reserved for security
21 */
22#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
23
24#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
Linus Walleij7b8ddb02010-05-27 15:21:26 -0700[diff] [blame]25
Linus Walleijca2ea4e2011-12-15 11:56:23 +0100[diff] [blame]26/* This address fulfills the 256k alignment requirement of the lcla base */
27#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4
28
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]29#define U8500_PER3_BASE 0x80000000
30#define U8500_STM_BASE 0x80100000
31#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
32#define U8500_PER2_BASE 0x80110000
33#define U8500_PER1_BASE 0x80120000
34#define U8500_B2R2_BASE 0x80130000
35#define U8500_HSEM_BASE 0x80140000
36#define U8500_PER4_BASE 0x80150000
Linus Walleij32647402011-03-29 17:34:23 +0200[diff] [blame]37#define U8500_TPIU_BASE 0x80190000
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]38#define U8500_ICN_BASE 0x81000000
39
40#define U8500_BOOT_ROM_BASE 0x90000000
Linus Walleij32647402011-03-29 17:34:23 +0200[diff] [blame]41/* ASIC ID is at 0xbf4 offset within this region */
42#define U8500_ASIC_ID_BASE 0x9001D000
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]43
Linus Walleijbc71c092012-01-23 11:54:44 +0100[diff] [blame^]44#define U9540_BOOT_ROM_BASE 0xFFFE0000
45/* ASIC ID is at 0xbf4 offset within this region */
46#define U9540_ASIC_ID_BASE 0xFFFFD000
47
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]48#define U8500_PER6_BASE 0xa03c0000
Linus Walleijca2ea4e2011-12-15 11:56:23 +0100[diff] [blame]49#define U8500_PER7_BASE 0xa03d0000
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]50#define U8500_PER5_BASE 0xa03e0000
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]51
52#define U8500_SVA_BASE 0xa0100000
53#define U8500_SIA_BASE 0xa0200000
54
55#define U8500_SGA_BASE 0xa0300000
56#define U8500_MCDE_BASE 0xa0350000
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]57#define U8500_DMA_BASE 0x801C0000 /* v1 */
58
59#define U8500_SBAG_BASE 0xa0390000
60
61#define U8500_SCU_BASE 0xa0410000
62#define U8500_GIC_CPU_BASE 0xa0410100
63#define U8500_TWD_BASE 0xa0410600
64#define U8500_GIC_DIST_BASE 0xa0411000
65#define U8500_L2CC_BASE 0xa0412000
66
67#define U8500_MODEM_I2C 0xb7e02000
68
69#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
70#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000)
71#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
72#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
73
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]74#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
75#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
76
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]77/* per6 base addresses */
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]78#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
Linus Walleij32647402011-03-29 17:34:23 +0200[diff] [blame]79#define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000)
80#define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000)
81#define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000)
82#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100)
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]83#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
84#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
85#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
Linus Walleij32647402011-03-29 17:34:23 +0200[diff] [blame]86#define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000)
87#define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000)
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]88#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
89
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]90/* per5 base addresses */
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]91#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
92#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
93
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]94/* per4 base addresses */
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]95#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
96#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
97#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
98#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000)
99#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000)
100#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
101#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
102#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
Linus Walleijbc71c092012-01-23 11:54:44 +0100[diff] [blame^]103#define U9540_DMC1_BASE (U8500_PER4_BASE + 0x0A000)
Linus Walleij32647402011-03-29 17:34:23 +0200[diff] [blame]104#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
Linus Walleijbc71c092012-01-23 11:54:44 +0100[diff] [blame^]105#define U9540_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x6A000)
Linus Walleij32647402011-03-29 17:34:23 +0200[diff] [blame]106#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000)
Linus Walleijc15def12011-12-15 13:38:40 +0100[diff] [blame]107#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
108#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
Mattias Wallin7ed00af2011-05-27 10:30:34 +0200[diff] [blame]109
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]110/* per3 base addresses */
111#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
112#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
113#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
114#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
115#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
116#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
117#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
118#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
119#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
120
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]121/* per2 base addresses */
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]122#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
123#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
124#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
125#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
126#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
127#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
128#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
129#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
130#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
131#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
132#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
133#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
134
135/* per1 base addresses */
136#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
137#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
138#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
Linus Walleij32647402011-03-29 17:34:23 +0200[diff] [blame]139#define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000)
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]140#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
141#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
142#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
143#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000)
144#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000)
145#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
146
147#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040
148
149#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE
150#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80)
151#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE
152#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80)
153#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100)
154#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180)
155#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
156#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
157#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
158
Linus Walleij32647402011-03-29 17:34:23 +0200[diff] [blame]159#define U8500_MCDE_SIZE 0x1000
160#define U8500_DSI_LINK_SIZE 0x1000
161#define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE)
162#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
163#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
164#define U8500_DSI_LINK_COUNT 0x3
165
166/* Modem and APE physical addresses */
167#define U8500_MODEM_BASE 0xe000000
168#define U8500_APE_BASE 0x6000000
169
Lee Joneseda413c2012-02-06 11:22:24 -0800[diff] [blame]170/* SoC identification number information */
171#define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0)
172
Rabin Vincentc9c09572010-05-03 07:34:53 +0100[diff] [blame]173#endif