Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
Florian Vaussard | 6d624ea | 2013-05-31 14:32:56 +0200 | [diff] [blame] | 9 | #include <dt-bindings/gpio/gpio.h> |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame^] | 11 | #include <dt-bindings/pinctrl/omap.h> |
Florian Vaussard | 6d624ea | 2013-05-31 14:32:56 +0200 | [diff] [blame] | 12 | |
Florian Vaussard | 98ef7957 | 2013-05-31 14:32:55 +0200 | [diff] [blame] | 13 | #include "skeleton.dtsi" |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 14 | |
| 15 | / { |
| 16 | compatible = "ti,omap4430", "ti,omap4"; |
| 17 | interrupt-parent = <&gic>; |
| 18 | |
| 19 | aliases { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 20 | serial0 = &uart1; |
| 21 | serial1 = &uart2; |
| 22 | serial2 = &uart3; |
| 23 | serial3 = &uart4; |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 24 | }; |
| 25 | |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 26 | cpus { |
| 27 | cpu@0 { |
| 28 | compatible = "arm,cortex-a9"; |
Santosh Shilimkar | 926fd45 | 2012-07-04 17:57:34 +0530 | [diff] [blame] | 29 | next-level-cache = <&L2>; |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 30 | }; |
| 31 | cpu@1 { |
| 32 | compatible = "arm,cortex-a9"; |
Santosh Shilimkar | 926fd45 | 2012-07-04 17:57:34 +0530 | [diff] [blame] | 33 | next-level-cache = <&L2>; |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 34 | }; |
| 35 | }; |
| 36 | |
Benoit Cousson | 5635121 | 2012-09-03 17:56:32 +0200 | [diff] [blame] | 37 | gic: interrupt-controller@48241000 { |
| 38 | compatible = "arm,cortex-a9-gic"; |
| 39 | interrupt-controller; |
| 40 | #interrupt-cells = <3>; |
| 41 | reg = <0x48241000 0x1000>, |
| 42 | <0x48240100 0x0100>; |
| 43 | }; |
| 44 | |
Santosh Shilimkar | 926fd45 | 2012-07-04 17:57:34 +0530 | [diff] [blame] | 45 | L2: l2-cache-controller@48242000 { |
| 46 | compatible = "arm,pl310-cache"; |
| 47 | reg = <0x48242000 0x1000>; |
| 48 | cache-unified; |
| 49 | cache-level = <2>; |
| 50 | }; |
| 51 | |
Santosh Shilimkar | eed0de2 | 2012-07-04 18:32:32 +0530 | [diff] [blame] | 52 | local-timer@0x48240600 { |
| 53 | compatible = "arm,cortex-a9-twd-timer"; |
| 54 | reg = <0x48240600 0x20>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 55 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; |
Santosh Shilimkar | eed0de2 | 2012-07-04 18:32:32 +0530 | [diff] [blame] | 56 | }; |
| 57 | |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 58 | /* |
| 59 | * The soc node represents the soc top level view. It is uses for IPs |
| 60 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 61 | */ |
| 62 | soc { |
| 63 | compatible = "ti,omap-infra"; |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 64 | mpu { |
| 65 | compatible = "ti,omap4-mpu"; |
| 66 | ti,hwmods = "mpu"; |
| 67 | }; |
| 68 | |
| 69 | dsp { |
| 70 | compatible = "ti,omap3-c64"; |
| 71 | ti,hwmods = "dsp"; |
| 72 | }; |
| 73 | |
| 74 | iva { |
| 75 | compatible = "ti,ivahd"; |
| 76 | ti,hwmods = "iva"; |
| 77 | }; |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | /* |
| 81 | * XXX: Use a flat representation of the OMAP4 interconnect. |
| 82 | * The real OMAP interconnect network is quite complex. |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 83 | * Since that will not bring real advantage to represent that in DT for |
| 84 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 85 | * hierarchy. |
| 86 | */ |
| 87 | ocp { |
Benoit Cousson | ad8dfac | 2011-08-12 13:48:47 +0200 | [diff] [blame] | 88 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 89 | #address-cells = <1>; |
| 90 | #size-cells = <1>; |
| 91 | ranges; |
Benoit Cousson | ad8dfac | 2011-08-12 13:48:47 +0200 | [diff] [blame] | 92 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
Santosh Shilimkar | 20a60ea | 2013-02-26 17:36:14 +0530 | [diff] [blame] | 93 | reg = <0x44000000 0x1000>, |
| 94 | <0x44800000 0x2000>, |
| 95 | <0x45000000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 96 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 97 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 98 | |
Jon Hunter | 510c0ff | 2012-10-25 14:24:14 -0500 | [diff] [blame] | 99 | counter32k: counter@4a304000 { |
| 100 | compatible = "ti,omap-counter32k"; |
| 101 | reg = <0x4a304000 0x20>; |
| 102 | ti,hwmods = "counter_32k"; |
| 103 | }; |
| 104 | |
Tony Lindgren | 679e331 | 2012-09-10 10:34:51 -0700 | [diff] [blame] | 105 | omap4_pmx_core: pinmux@4a100040 { |
| 106 | compatible = "ti,omap4-padconf", "pinctrl-single"; |
| 107 | reg = <0x4a100040 0x0196>; |
| 108 | #address-cells = <1>; |
| 109 | #size-cells = <0>; |
| 110 | pinctrl-single,register-width = <16>; |
| 111 | pinctrl-single,function-mask = <0x7fff>; |
| 112 | }; |
| 113 | omap4_pmx_wkup: pinmux@4a31e040 { |
| 114 | compatible = "ti,omap4-padconf", "pinctrl-single"; |
| 115 | reg = <0x4a31e040 0x0038>; |
| 116 | #address-cells = <1>; |
| 117 | #size-cells = <0>; |
| 118 | pinctrl-single,register-width = <16>; |
| 119 | pinctrl-single,function-mask = <0x7fff>; |
| 120 | }; |
| 121 | |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 122 | sdma: dma-controller@4a056000 { |
| 123 | compatible = "ti,omap4430-sdma"; |
| 124 | reg = <0x4a056000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 125 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 126 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 127 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 128 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 129 | #dma-cells = <1>; |
| 130 | #dma-channels = <32>; |
| 131 | #dma-requests = <127>; |
| 132 | }; |
| 133 | |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 134 | gpio1: gpio@4a310000 { |
| 135 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 136 | reg = <0x4a310000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 137 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 138 | ti,hwmods = "gpio1"; |
Jon Hunter | e4b9b9f | 2013-04-04 15:16:16 -0500 | [diff] [blame] | 139 | ti,gpio-always-on; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 140 | gpio-controller; |
| 141 | #gpio-cells = <2>; |
| 142 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 143 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 144 | }; |
| 145 | |
| 146 | gpio2: gpio@48055000 { |
| 147 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 148 | reg = <0x48055000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 149 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 150 | ti,hwmods = "gpio2"; |
| 151 | gpio-controller; |
| 152 | #gpio-cells = <2>; |
| 153 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 154 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 155 | }; |
| 156 | |
| 157 | gpio3: gpio@48057000 { |
| 158 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 159 | reg = <0x48057000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 160 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 161 | ti,hwmods = "gpio3"; |
| 162 | gpio-controller; |
| 163 | #gpio-cells = <2>; |
| 164 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 165 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 166 | }; |
| 167 | |
| 168 | gpio4: gpio@48059000 { |
| 169 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 170 | reg = <0x48059000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 171 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 172 | ti,hwmods = "gpio4"; |
| 173 | gpio-controller; |
| 174 | #gpio-cells = <2>; |
| 175 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 176 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 177 | }; |
| 178 | |
| 179 | gpio5: gpio@4805b000 { |
| 180 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 181 | reg = <0x4805b000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 182 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 183 | ti,hwmods = "gpio5"; |
| 184 | gpio-controller; |
| 185 | #gpio-cells = <2>; |
| 186 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 187 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 188 | }; |
| 189 | |
| 190 | gpio6: gpio@4805d000 { |
| 191 | compatible = "ti,omap4-gpio"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 192 | reg = <0x4805d000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 193 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 194 | ti,hwmods = "gpio6"; |
| 195 | gpio-controller; |
| 196 | #gpio-cells = <2>; |
| 197 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 198 | #interrupt-cells = <2>; |
Benoit Cousson | e3e5a92 | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 199 | }; |
| 200 | |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 201 | gpmc: gpmc@50000000 { |
| 202 | compatible = "ti,omap4430-gpmc"; |
| 203 | reg = <0x50000000 0x1000>; |
| 204 | #address-cells = <2>; |
| 205 | #size-cells = <1>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 206 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 207 | gpmc,num-cs = <8>; |
| 208 | gpmc,num-waitpins = <4>; |
| 209 | ti,hwmods = "gpmc"; |
| 210 | }; |
| 211 | |
Benoit Cousson | 19bfb76 | 2012-02-16 11:55:27 +0100 | [diff] [blame] | 212 | uart1: serial@4806a000 { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 213 | compatible = "ti,omap4-uart"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 214 | reg = <0x4806a000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 215 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 216 | ti,hwmods = "uart1"; |
| 217 | clock-frequency = <48000000>; |
| 218 | }; |
| 219 | |
Benoit Cousson | 19bfb76 | 2012-02-16 11:55:27 +0100 | [diff] [blame] | 220 | uart2: serial@4806c000 { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 221 | compatible = "ti,omap4-uart"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 222 | reg = <0x4806c000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 223 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 224 | ti,hwmods = "uart2"; |
| 225 | clock-frequency = <48000000>; |
| 226 | }; |
| 227 | |
Benoit Cousson | 19bfb76 | 2012-02-16 11:55:27 +0100 | [diff] [blame] | 228 | uart3: serial@48020000 { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 229 | compatible = "ti,omap4-uart"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 230 | reg = <0x48020000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 231 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 232 | ti,hwmods = "uart3"; |
| 233 | clock-frequency = <48000000>; |
| 234 | }; |
| 235 | |
Benoit Cousson | 19bfb76 | 2012-02-16 11:55:27 +0100 | [diff] [blame] | 236 | uart4: serial@4806e000 { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 237 | compatible = "ti,omap4-uart"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 238 | reg = <0x4806e000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 239 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 240 | ti,hwmods = "uart4"; |
| 241 | clock-frequency = <48000000>; |
| 242 | }; |
Benoit Cousson | 58e778f | 2011-08-17 19:00:03 +0530 | [diff] [blame] | 243 | |
| 244 | i2c1: i2c@48070000 { |
| 245 | compatible = "ti,omap4-i2c"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 246 | reg = <0x48070000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 247 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | 58e778f | 2011-08-17 19:00:03 +0530 | [diff] [blame] | 248 | #address-cells = <1>; |
| 249 | #size-cells = <0>; |
| 250 | ti,hwmods = "i2c1"; |
| 251 | }; |
| 252 | |
| 253 | i2c2: i2c@48072000 { |
| 254 | compatible = "ti,omap4-i2c"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 255 | reg = <0x48072000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 256 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | 58e778f | 2011-08-17 19:00:03 +0530 | [diff] [blame] | 257 | #address-cells = <1>; |
| 258 | #size-cells = <0>; |
| 259 | ti,hwmods = "i2c2"; |
| 260 | }; |
| 261 | |
| 262 | i2c3: i2c@48060000 { |
| 263 | compatible = "ti,omap4-i2c"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 264 | reg = <0x48060000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 265 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | 58e778f | 2011-08-17 19:00:03 +0530 | [diff] [blame] | 266 | #address-cells = <1>; |
| 267 | #size-cells = <0>; |
| 268 | ti,hwmods = "i2c3"; |
| 269 | }; |
| 270 | |
| 271 | i2c4: i2c@48350000 { |
| 272 | compatible = "ti,omap4-i2c"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 273 | reg = <0x48350000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 274 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | 58e778f | 2011-08-17 19:00:03 +0530 | [diff] [blame] | 275 | #address-cells = <1>; |
| 276 | #size-cells = <0>; |
| 277 | ti,hwmods = "i2c4"; |
| 278 | }; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 279 | |
| 280 | mcspi1: spi@48098000 { |
| 281 | compatible = "ti,omap4-mcspi"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 282 | reg = <0x48098000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 283 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 284 | #address-cells = <1>; |
| 285 | #size-cells = <0>; |
| 286 | ti,hwmods = "mcspi1"; |
| 287 | ti,spi-num-cs = <4>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 288 | dmas = <&sdma 35>, |
| 289 | <&sdma 36>, |
| 290 | <&sdma 37>, |
| 291 | <&sdma 38>, |
| 292 | <&sdma 39>, |
| 293 | <&sdma 40>, |
| 294 | <&sdma 41>, |
| 295 | <&sdma 42>; |
| 296 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 297 | "tx2", "rx2", "tx3", "rx3"; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 298 | }; |
| 299 | |
| 300 | mcspi2: spi@4809a000 { |
| 301 | compatible = "ti,omap4-mcspi"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 302 | reg = <0x4809a000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 303 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 304 | #address-cells = <1>; |
| 305 | #size-cells = <0>; |
| 306 | ti,hwmods = "mcspi2"; |
| 307 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 308 | dmas = <&sdma 43>, |
| 309 | <&sdma 44>, |
| 310 | <&sdma 45>, |
| 311 | <&sdma 46>; |
| 312 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 313 | }; |
| 314 | |
| 315 | mcspi3: spi@480b8000 { |
| 316 | compatible = "ti,omap4-mcspi"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 317 | reg = <0x480b8000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 318 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 319 | #address-cells = <1>; |
| 320 | #size-cells = <0>; |
| 321 | ti,hwmods = "mcspi3"; |
| 322 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 323 | dmas = <&sdma 15>, <&sdma 16>; |
| 324 | dma-names = "tx0", "rx0"; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 325 | }; |
| 326 | |
| 327 | mcspi4: spi@480ba000 { |
| 328 | compatible = "ti,omap4-mcspi"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 329 | reg = <0x480ba000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 330 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 331 | #address-cells = <1>; |
| 332 | #size-cells = <0>; |
| 333 | ti,hwmods = "mcspi4"; |
| 334 | ti,spi-num-cs = <1>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 335 | dmas = <&sdma 70>, <&sdma 71>; |
| 336 | dma-names = "tx0", "rx0"; |
Benoit Cousson | efcf1e5 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 337 | }; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 338 | |
| 339 | mmc1: mmc@4809c000 { |
| 340 | compatible = "ti,omap4-hsmmc"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 341 | reg = <0x4809c000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 342 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 343 | ti,hwmods = "mmc1"; |
| 344 | ti,dual-volt; |
| 345 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 346 | dmas = <&sdma 61>, <&sdma 62>; |
| 347 | dma-names = "tx", "rx"; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 348 | }; |
| 349 | |
| 350 | mmc2: mmc@480b4000 { |
| 351 | compatible = "ti,omap4-hsmmc"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 352 | reg = <0x480b4000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 353 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 354 | ti,hwmods = "mmc2"; |
| 355 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 356 | dmas = <&sdma 47>, <&sdma 48>; |
| 357 | dma-names = "tx", "rx"; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 358 | }; |
| 359 | |
| 360 | mmc3: mmc@480ad000 { |
| 361 | compatible = "ti,omap4-hsmmc"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 362 | reg = <0x480ad000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 363 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 364 | ti,hwmods = "mmc3"; |
| 365 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 366 | dmas = <&sdma 77>, <&sdma 78>; |
| 367 | dma-names = "tx", "rx"; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 368 | }; |
| 369 | |
| 370 | mmc4: mmc@480d1000 { |
| 371 | compatible = "ti,omap4-hsmmc"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 372 | reg = <0x480d1000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 373 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 374 | ti,hwmods = "mmc4"; |
| 375 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 376 | dmas = <&sdma 57>, <&sdma 58>; |
| 377 | dma-names = "tx", "rx"; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 378 | }; |
| 379 | |
| 380 | mmc5: mmc@480d5000 { |
| 381 | compatible = "ti,omap4-hsmmc"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 382 | reg = <0x480d5000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 383 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 384 | ti,hwmods = "mmc5"; |
| 385 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 386 | dmas = <&sdma 59>, <&sdma 60>; |
| 387 | dma-names = "tx", "rx"; |
Rajendra Nayak | 7498176 | 2011-10-04 17:10:27 +0530 | [diff] [blame] | 388 | }; |
Xiao Jiang | 94c3073 | 2012-06-01 12:44:14 +0800 | [diff] [blame] | 389 | |
| 390 | wdt2: wdt@4a314000 { |
| 391 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 392 | reg = <0x4a314000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 393 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
Xiao Jiang | 94c3073 | 2012-06-01 12:44:14 +0800 | [diff] [blame] | 394 | ti,hwmods = "wd_timer2"; |
| 395 | }; |
Peter Ujfalusi | 4f4b5c7 | 2012-06-08 17:01:59 +0300 | [diff] [blame] | 396 | |
| 397 | mcpdm: mcpdm@40132000 { |
| 398 | compatible = "ti,omap4-mcpdm"; |
| 399 | reg = <0x40132000 0x7f>, /* MPU private access */ |
| 400 | <0x49032000 0x7f>; /* L3 Interconnect */ |
Peter Ujfalusi | 63467cf | 2012-08-29 16:31:06 +0300 | [diff] [blame] | 401 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 402 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | 4f4b5c7 | 2012-06-08 17:01:59 +0300 | [diff] [blame] | 403 | ti,hwmods = "mcpdm"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 404 | dmas = <&sdma 65>, |
| 405 | <&sdma 66>; |
| 406 | dma-names = "up_link", "dn_link"; |
Peter Ujfalusi | 4f4b5c7 | 2012-06-08 17:01:59 +0300 | [diff] [blame] | 407 | }; |
Peter Ujfalusi | a4c3831 | 2012-06-08 17:02:00 +0300 | [diff] [blame] | 408 | |
| 409 | dmic: dmic@4012e000 { |
| 410 | compatible = "ti,omap4-dmic"; |
| 411 | reg = <0x4012e000 0x7f>, /* MPU private access */ |
| 412 | <0x4902e000 0x7f>; /* L3 Interconnect */ |
Peter Ujfalusi | 63467cf | 2012-08-29 16:31:06 +0300 | [diff] [blame] | 413 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 414 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | a4c3831 | 2012-06-08 17:02:00 +0300 | [diff] [blame] | 415 | ti,hwmods = "dmic"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 416 | dmas = <&sdma 67>; |
| 417 | dma-names = "up_link"; |
Peter Ujfalusi | a4c3831 | 2012-06-08 17:02:00 +0300 | [diff] [blame] | 418 | }; |
Sourav Poddar | 61bc354 | 2012-08-14 16:45:37 +0530 | [diff] [blame] | 419 | |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 420 | mcbsp1: mcbsp@40122000 { |
| 421 | compatible = "ti,omap4-mcbsp"; |
| 422 | reg = <0x40122000 0xff>, /* MPU private access */ |
| 423 | <0x49022000 0xff>; /* L3 Interconnect */ |
| 424 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 425 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 426 | interrupt-names = "common"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 427 | ti,buffer-size = <128>; |
| 428 | ti,hwmods = "mcbsp1"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 429 | dmas = <&sdma 33>, |
| 430 | <&sdma 34>; |
| 431 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 432 | }; |
| 433 | |
| 434 | mcbsp2: mcbsp@40124000 { |
| 435 | compatible = "ti,omap4-mcbsp"; |
| 436 | reg = <0x40124000 0xff>, /* MPU private access */ |
| 437 | <0x49024000 0xff>; /* L3 Interconnect */ |
| 438 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 439 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 440 | interrupt-names = "common"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 441 | ti,buffer-size = <128>; |
| 442 | ti,hwmods = "mcbsp2"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 443 | dmas = <&sdma 17>, |
| 444 | <&sdma 18>; |
| 445 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 446 | }; |
| 447 | |
| 448 | mcbsp3: mcbsp@40126000 { |
| 449 | compatible = "ti,omap4-mcbsp"; |
| 450 | reg = <0x40126000 0xff>, /* MPU private access */ |
| 451 | <0x49026000 0xff>; /* L3 Interconnect */ |
| 452 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 453 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 454 | interrupt-names = "common"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 455 | ti,buffer-size = <128>; |
| 456 | ti,hwmods = "mcbsp3"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 457 | dmas = <&sdma 19>, |
| 458 | <&sdma 20>; |
| 459 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 460 | }; |
| 461 | |
| 462 | mcbsp4: mcbsp@48096000 { |
| 463 | compatible = "ti,omap4-mcbsp"; |
| 464 | reg = <0x48096000 0xff>; /* L4 Interconnect */ |
| 465 | reg-names = "mpu"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 466 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 467 | interrupt-names = "common"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 468 | ti,buffer-size = <128>; |
| 469 | ti,hwmods = "mcbsp4"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 470 | dmas = <&sdma 31>, |
| 471 | <&sdma 32>; |
| 472 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 2995a10 | 2012-07-26 17:13:21 +0300 | [diff] [blame] | 473 | }; |
| 474 | |
Sourav Poddar | 61bc354 | 2012-08-14 16:45:37 +0530 | [diff] [blame] | 475 | keypad: keypad@4a31c000 { |
| 476 | compatible = "ti,omap4-keypad"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 477 | reg = <0x4a31c000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 478 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 479 | reg-names = "mpu"; |
Sourav Poddar | 61bc354 | 2012-08-14 16:45:37 +0530 | [diff] [blame] | 480 | ti,hwmods = "kbd"; |
| 481 | }; |
Aneesh V | 11c2706 | 2012-01-20 20:35:26 +0530 | [diff] [blame] | 482 | |
| 483 | emif1: emif@4c000000 { |
| 484 | compatible = "ti,emif-4d"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 485 | reg = <0x4c000000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 486 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
Aneesh V | 11c2706 | 2012-01-20 20:35:26 +0530 | [diff] [blame] | 487 | ti,hwmods = "emif1"; |
| 488 | phy-type = <1>; |
| 489 | hw-caps-read-idle-ctrl; |
| 490 | hw-caps-ll-interface; |
| 491 | hw-caps-temp-alert; |
| 492 | }; |
| 493 | |
| 494 | emif2: emif@4d000000 { |
| 495 | compatible = "ti,emif-4d"; |
Benoit Cousson | 48420db | 2012-09-05 11:38:23 +0200 | [diff] [blame] | 496 | reg = <0x4d000000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 497 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
Aneesh V | 11c2706 | 2012-01-20 20:35:26 +0530 | [diff] [blame] | 498 | ti,hwmods = "emif2"; |
| 499 | phy-type = <1>; |
| 500 | hw-caps-read-idle-ctrl; |
| 501 | hw-caps-ll-interface; |
| 502 | hw-caps-temp-alert; |
| 503 | }; |
Linus Torvalds | 8f446a7 | 2012-10-01 18:46:13 -0700 | [diff] [blame] | 504 | |
Kishon Vijay Abraham I | 3ce0a99 | 2012-09-19 16:02:51 +0530 | [diff] [blame] | 505 | ocp2scp@4a0ad000 { |
Kishon Vijay Abraham I | 59bafcf | 2012-08-22 14:10:03 +0530 | [diff] [blame] | 506 | compatible = "ti,omap-ocp2scp"; |
Kishon Vijay Abraham I | 3ce0a99 | 2012-09-19 16:02:51 +0530 | [diff] [blame] | 507 | reg = <0x4a0ad000 0x1f>; |
Kishon Vijay Abraham I | 59bafcf | 2012-08-22 14:10:03 +0530 | [diff] [blame] | 508 | #address-cells = <1>; |
| 509 | #size-cells = <1>; |
| 510 | ranges; |
| 511 | ti,hwmods = "ocp2scp_usb_phy"; |
Kishon Vijay Abraham I | cf0d869 | 2013-03-07 19:05:15 +0530 | [diff] [blame] | 512 | usb2_phy: usb2phy@4a0ad080 { |
| 513 | compatible = "ti,omap-usb2"; |
| 514 | reg = <0x4a0ad080 0x58>; |
| 515 | ctrl-module = <&omap_control_usb>; |
| 516 | }; |
Kishon Vijay Abraham I | 59bafcf | 2012-08-22 14:10:03 +0530 | [diff] [blame] | 517 | }; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 518 | |
| 519 | timer1: timer@4a318000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 520 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 521 | reg = <0x4a318000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 522 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 523 | ti,hwmods = "timer1"; |
| 524 | ti,timer-alwon; |
| 525 | }; |
| 526 | |
| 527 | timer2: timer@48032000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 528 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 529 | reg = <0x48032000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 530 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 531 | ti,hwmods = "timer2"; |
| 532 | }; |
| 533 | |
| 534 | timer3: timer@48034000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 535 | compatible = "ti,omap4430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 536 | reg = <0x48034000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 537 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 538 | ti,hwmods = "timer3"; |
| 539 | }; |
| 540 | |
| 541 | timer4: timer@48036000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 542 | compatible = "ti,omap4430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 543 | reg = <0x48036000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 544 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 545 | ti,hwmods = "timer4"; |
| 546 | }; |
| 547 | |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 548 | timer5: timer@40138000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 549 | compatible = "ti,omap4430-timer"; |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 550 | reg = <0x40138000 0x80>, |
| 551 | <0x49038000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 552 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 553 | ti,hwmods = "timer5"; |
| 554 | ti,timer-dsp; |
| 555 | }; |
| 556 | |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 557 | timer6: timer@4013a000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 558 | compatible = "ti,omap4430-timer"; |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 559 | reg = <0x4013a000 0x80>, |
| 560 | <0x4903a000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 561 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 562 | ti,hwmods = "timer6"; |
| 563 | ti,timer-dsp; |
| 564 | }; |
| 565 | |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 566 | timer7: timer@4013c000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 567 | compatible = "ti,omap4430-timer"; |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 568 | reg = <0x4013c000 0x80>, |
| 569 | <0x4903c000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 570 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 571 | ti,hwmods = "timer7"; |
| 572 | ti,timer-dsp; |
| 573 | }; |
| 574 | |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 575 | timer8: timer@4013e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 576 | compatible = "ti,omap4430-timer"; |
Jon Hunter | d03a93b | 2012-11-01 08:57:08 -0500 | [diff] [blame] | 577 | reg = <0x4013e000 0x80>, |
| 578 | <0x4903e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 579 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 580 | ti,hwmods = "timer8"; |
| 581 | ti,timer-pwm; |
| 582 | ti,timer-dsp; |
| 583 | }; |
| 584 | |
| 585 | timer9: timer@4803e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 586 | compatible = "ti,omap4430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 587 | reg = <0x4803e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 588 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 589 | ti,hwmods = "timer9"; |
| 590 | ti,timer-pwm; |
| 591 | }; |
| 592 | |
| 593 | timer10: timer@48086000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 594 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 595 | reg = <0x48086000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 596 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 597 | ti,hwmods = "timer10"; |
| 598 | ti,timer-pwm; |
| 599 | }; |
| 600 | |
| 601 | timer11: timer@48088000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 602 | compatible = "ti,omap4430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 603 | reg = <0x48088000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 604 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 605 | ti,hwmods = "timer11"; |
| 606 | ti,timer-pwm; |
| 607 | }; |
Roger Quadros | f17c899 | 2013-03-20 17:44:58 +0200 | [diff] [blame] | 608 | |
| 609 | usbhstll: usbhstll@4a062000 { |
| 610 | compatible = "ti,usbhs-tll"; |
| 611 | reg = <0x4a062000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 612 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | f17c899 | 2013-03-20 17:44:58 +0200 | [diff] [blame] | 613 | ti,hwmods = "usb_tll_hs"; |
| 614 | }; |
| 615 | |
| 616 | usbhshost: usbhshost@4a064000 { |
| 617 | compatible = "ti,usbhs-host"; |
| 618 | reg = <0x4a064000 0x800>; |
| 619 | ti,hwmods = "usb_host_hs"; |
| 620 | #address-cells = <1>; |
| 621 | #size-cells = <1>; |
| 622 | ranges; |
| 623 | |
| 624 | usbhsohci: ohci@4a064800 { |
| 625 | compatible = "ti,ohci-omap3", "usb-ohci"; |
| 626 | reg = <0x4a064800 0x400>; |
| 627 | interrupt-parent = <&gic>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 628 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | f17c899 | 2013-03-20 17:44:58 +0200 | [diff] [blame] | 629 | }; |
| 630 | |
| 631 | usbhsehci: ehci@4a064c00 { |
| 632 | compatible = "ti,ehci-omap", "usb-ehci"; |
| 633 | reg = <0x4a064c00 0x400>; |
| 634 | interrupt-parent = <&gic>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 635 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | f17c899 | 2013-03-20 17:44:58 +0200 | [diff] [blame] | 636 | }; |
| 637 | }; |
Kishon Vijay Abraham I | 840e5fd | 2013-03-07 19:05:14 +0530 | [diff] [blame] | 638 | |
| 639 | omap_control_usb: omap-control-usb@4a002300 { |
| 640 | compatible = "ti,omap-control-usb"; |
| 641 | reg = <0x4a002300 0x4>, |
| 642 | <0x4a00233c 0x4>; |
| 643 | reg-names = "control_dev_conf", "otghs_control"; |
| 644 | ti,type = <1>; |
| 645 | }; |
Kishon Vijay Abraham I | ad871c1 | 2013-03-07 19:05:16 +0530 | [diff] [blame] | 646 | |
| 647 | usb_otg_hs: usb_otg_hs@4a0ab000 { |
| 648 | compatible = "ti,omap4-musb"; |
| 649 | reg = <0x4a0ab000 0x7ff>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 650 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Kishon Vijay Abraham I | ad871c1 | 2013-03-07 19:05:16 +0530 | [diff] [blame] | 651 | interrupt-names = "mc", "dma"; |
| 652 | ti,hwmods = "usb_otg_hs"; |
| 653 | usb-phy = <&usb2_phy>; |
| 654 | multipoint = <1>; |
| 655 | num-eps = <16>; |
| 656 | ram-bits = <12>; |
| 657 | ti,has-mailbox; |
| 658 | }; |
Benoit Cousson | d9fda07 | 2011-08-09 17:15:17 +0200 | [diff] [blame] | 659 | }; |
| 660 | }; |