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Srinivas Kandagatla15969b42013-06-25 12:15:23 +01001
2/*
3 * Copyright (C) 2013 STMicroelectronics Limited.
4 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 */
10#include "st-pincfg.h"
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000011#include <dt-bindings/interrupt-controller/arm-gic.h>
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010012/ {
13
14 aliases {
15 gpio0 = &PIO0;
16 gpio1 = &PIO1;
17 gpio2 = &PIO2;
18 gpio3 = &PIO3;
19 gpio4 = &PIO4;
20 gpio5 = &PIO40;
21 gpio6 = &PIO5;
22 gpio7 = &PIO6;
23 gpio8 = &PIO7;
24 gpio9 = &PIO8;
25 gpio10 = &PIO9;
26 gpio11 = &PIO10;
27 gpio12 = &PIO11;
28 gpio13 = &PIO12;
29 gpio14 = &PIO30;
30 gpio15 = &PIO31;
31 gpio16 = &PIO13;
32 gpio17 = &PIO14;
33 gpio18 = &PIO15;
34 gpio19 = &PIO16;
35 gpio20 = &PIO17;
36 gpio21 = &PIO18;
37 gpio22 = &PIO100;
38 gpio23 = &PIO101;
39 gpio24 = &PIO102;
40 gpio25 = &PIO103;
41 gpio26 = &PIO104;
42 gpio27 = &PIO105;
43 gpio28 = &PIO106;
44 gpio29 = &PIO107;
45 };
46
47 soc {
48 pin-controller-sbc {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "st,stih416-sbc-pinctrl";
52 st,syscfg = <&syscfg_sbc>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000053 reg = <0xfe61f080 0x4>;
54 reg-names = "irqmux";
55 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
56 interrupts-names = "irqmux";
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010057 ranges = <0 0xfe610000 0x6000>;
58
59 PIO0: gpio@fe610000 {
60 gpio-controller;
61 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000062 interrupt-controller;
63 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010064 reg = <0 0x100>;
65 st,bank-name = "PIO0";
66 };
67 PIO1: gpio@fe611000 {
68 gpio-controller;
69 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000070 interrupt-controller;
71 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010072 reg = <0x1000 0x100>;
73 st,bank-name = "PIO1";
74 };
75 PIO2: gpio@fe612000 {
76 gpio-controller;
77 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000078 interrupt-controller;
79 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010080 reg = <0x2000 0x100>;
81 st,bank-name = "PIO2";
82 };
83 PIO3: gpio@fe613000 {
84 gpio-controller;
85 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000086 interrupt-controller;
87 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010088 reg = <0x3000 0x100>;
89 st,bank-name = "PIO3";
90 };
91 PIO4: gpio@fe614000 {
92 gpio-controller;
93 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +000094 interrupt-controller;
95 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +010096 reg = <0x4000 0x100>;
97 st,bank-name = "PIO4";
98 };
99 PIO40: gpio@fe615000 {
100 gpio-controller;
101 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000102 interrupt-controller;
103 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100104 reg = <0x5000 0x100>;
105 st,bank-name = "PIO40";
106 st,retime-pin-mask = <0x7f>;
107 };
108
109 sbc_serial1 {
110 pinctrl_sbc_serial1: sbc_serial1 {
111 st,pins {
112 tx = <&PIO2 6 ALT3 OUT>;
113 rx = <&PIO2 7 ALT3 IN>;
114 };
115 };
116 };
Maxime COQUELINf53e99a2013-11-06 09:25:13 +0100117
118 sbc_i2c0 {
119 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
120 st,pins {
121 sda = <&PIO4 6 ALT1 BIDIR>;
122 scl = <&PIO4 5 ALT1 BIDIR>;
123 };
124 };
125 };
126
127 sbc_i2c1 {
128 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
129 st,pins {
130 sda = <&PIO3 2 ALT2 BIDIR>;
131 scl = <&PIO3 1 ALT2 BIDIR>;
132 };
133 };
134 };
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100135 };
136
137 pin-controller-front {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "st,stih416-front-pinctrl";
141 st,syscfg = <&syscfg_front>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000142 reg = <0xfee0f080 0x4>;
143 reg-names = "irqmux";
144 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
145 interrupts-names = "irqmux";
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100146 ranges = <0 0xfee00000 0x10000>;
147
148 PIO5: gpio@fee00000 {
149 gpio-controller;
150 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000151 interrupt-controller;
152 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100153 reg = <0 0x100>;
154 st,bank-name = "PIO5";
155 };
156 PIO6: gpio@fee01000 {
157 gpio-controller;
158 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000159 interrupt-controller;
160 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100161 reg = <0x1000 0x100>;
162 st,bank-name = "PIO6";
163 };
164 PIO7: gpio@fee02000 {
165 gpio-controller;
166 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000167 interrupt-controller;
168 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100169 reg = <0x2000 0x100>;
170 st,bank-name = "PIO7";
171 };
172 PIO8: gpio@fee03000 {
173 gpio-controller;
174 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000175 interrupt-controller;
176 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100177 reg = <0x3000 0x100>;
178 st,bank-name = "PIO8";
179 };
180 PIO9: gpio@fee04000 {
181 gpio-controller;
182 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000183 interrupt-controller;
184 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100185 reg = <0x4000 0x100>;
186 st,bank-name = "PIO9";
187 };
188 PIO10: gpio@fee05000 {
189 gpio-controller;
190 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000191 interrupt-controller;
192 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100193 reg = <0x5000 0x100>;
194 st,bank-name = "PIO10";
195 };
196 PIO11: gpio@fee06000 {
197 gpio-controller;
198 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000199 interrupt-controller;
200 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100201 reg = <0x6000 0x100>;
202 st,bank-name = "PIO11";
203 };
204 PIO12: gpio@fee07000 {
205 gpio-controller;
206 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000207 interrupt-controller;
208 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100209 reg = <0x7000 0x100>;
210 st,bank-name = "PIO12";
211 };
212 PIO30: gpio@fee08000 {
213 gpio-controller;
214 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000215 interrupt-controller;
216 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100217 reg = <0x8000 0x100>;
218 st,bank-name = "PIO30";
219 };
220 PIO31: gpio@fee09000 {
221 gpio-controller;
222 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000223 interrupt-controller;
224 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100225 reg = <0x9000 0x100>;
226 st,bank-name = "PIO31";
227 };
Srinivas Kandagatla334ab912013-07-09 08:26:24 +0100228
229 serial2-oe {
230 pinctrl_serial2_oe: serial2-1 {
231 st,pins {
232 output-enable = <&PIO11 3 ALT2 OUT>;
233 };
234 };
235 };
236
Maxime COQUELINf53e99a2013-11-06 09:25:13 +0100237 i2c0 {
238 pinctrl_i2c0_default: i2c0-default {
239 st,pins {
240 sda = <&PIO9 3 ALT1 BIDIR>;
241 scl = <&PIO9 2 ALT1 BIDIR>;
242 };
243 };
244 };
245
246 i2c1 {
247 pinctrl_i2c1_default: i2c1-default {
248 st,pins {
249 sda = <&PIO12 1 ALT1 BIDIR>;
250 scl = <&PIO12 0 ALT1 BIDIR>;
251 };
252 };
253 };
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100254 };
255
256 pin-controller-rear {
257 #address-cells = <1>;
258 #size-cells = <1>;
259 compatible = "st,stih416-rear-pinctrl";
260 st,syscfg = <&syscfg_rear>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000261 reg = <0xfe82f080 0x4>;
262 reg-names = "irqmux";
263 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
264 interrupts-names = "irqmux";
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100265 ranges = <0 0xfe820000 0x6000>;
266
267 PIO13: gpio@fe820000 {
268 gpio-controller;
269 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000270 interrupt-controller;
271 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100272 reg = <0 0x100>;
273 st,bank-name = "PIO13";
274 };
275 PIO14: gpio@fe821000 {
276 gpio-controller;
277 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000278 interrupt-controller;
279 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100280 reg = <0x1000 0x100>;
281 st,bank-name = "PIO14";
282 };
283 PIO15: gpio@fe822000 {
284 gpio-controller;
285 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000286 interrupt-controller;
287 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100288 reg = <0x2000 0x100>;
289 st,bank-name = "PIO15";
290 };
291 PIO16: gpio@fe823000 {
292 gpio-controller;
293 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000294 interrupt-controller;
295 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100296 reg = <0x3000 0x100>;
297 st,bank-name = "PIO16";
298 };
299 PIO17: gpio@fe824000 {
300 gpio-controller;
301 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000302 interrupt-controller;
303 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100304 reg = <0x4000 0x100>;
305 st,bank-name = "PIO17";
306 };
307 PIO18: gpio@fe825000 {
308 gpio-controller;
309 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000310 interrupt-controller;
311 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100312 reg = <0x5000 0x100>;
313 st,bank-name = "PIO18";
314 st,retime-pin-mask = <0xf>;
315 };
316
317 serial2 {
318 pinctrl_serial2: serial2-0 {
319 st,pins {
320 tx = <&PIO17 4 ALT2 OUT>;
321 rx = <&PIO17 5 ALT2 IN>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100322 };
323 };
324 };
325 };
326
327 pin-controller-fvdp-fe {
328 #address-cells = <1>;
329 #size-cells = <1>;
330 compatible = "st,stih416-fvdp-fe-pinctrl";
331 st,syscfg = <&syscfg_fvdp_fe>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000332 reg = <0xfd6bf080 0x4>;
333 reg-names = "irqmux";
334 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
335 interrupts-names = "irqmux";
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100336 ranges = <0 0xfd6b0000 0x3000>;
337
338 PIO100: gpio@fd6b0000 {
339 gpio-controller;
340 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000341 interrupt-controller;
342 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100343 reg = <0 0x100>;
344 st,bank-name = "PIO100";
345 };
346 PIO101: gpio@fd6b1000 {
347 gpio-controller;
348 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000349 interrupt-controller;
350 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100351 reg = <0x1000 0x100>;
352 st,bank-name = "PIO101";
353 };
354 PIO102: gpio@fd6b2000 {
355 gpio-controller;
356 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000357 interrupt-controller;
358 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100359 reg = <0x2000 0x100>;
360 st,bank-name = "PIO102";
361 };
362 };
363
364 pin-controller-fvdp-lite {
365 #address-cells = <1>;
366 #size-cells = <1>;
367 compatible = "st,stih416-fvdp-lite-pinctrl";
368 st,syscfg = <&syscfg_fvdp_lite>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000369 reg = <0xfd33f080 0x4>;
370 reg-names = "irqmux";
371 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
372 interrupts-names = "irqmux";
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100373 ranges = <0 0xfd330000 0x5000>;
374
375 PIO103: gpio@fd330000 {
376 gpio-controller;
377 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000378 interrupt-controller;
379 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100380 reg = <0 0x100>;
381 st,bank-name = "PIO103";
382 };
383 PIO104: gpio@fd331000 {
384 gpio-controller;
385 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000386 interrupt-controller;
387 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100388 reg = <0x1000 0x100>;
389 st,bank-name = "PIO104";
390 };
391 PIO105: gpio@fd332000 {
392 gpio-controller;
393 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000394 interrupt-controller;
395 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100396 reg = <0x2000 0x100>;
397 st,bank-name = "PIO105";
398 };
399 PIO106: gpio@fd333000 {
400 gpio-controller;
401 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000402 interrupt-controller;
403 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100404 reg = <0x3000 0x100>;
405 st,bank-name = "PIO106";
406 };
407
408 PIO107: gpio@fd334000 {
409 gpio-controller;
410 #gpio-cells = <1>;
Srinivas Kandagatlabdda8b02014-01-08 12:47:52 +0000411 interrupt-controller;
412 #interrupt-cells = <2>;
Srinivas Kandagatla15969b42013-06-25 12:15:23 +0100413 reg = <0x4000 0x100>;
414 st,bank-name = "PIO107";
415 st,retime-pin-mask = <0xf>;
416 };
417 };
418 };
419};