Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1 | /* |
| 2 | * drivers/spi/amba-pl022.c |
| 3 | * |
| 4 | * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. |
| 5 | * |
| 6 | * Copyright (C) 2008-2009 ST-Ericsson AB |
| 7 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. |
| 8 | * |
| 9 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
| 10 | * |
| 11 | * Initial version inspired by: |
| 12 | * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c |
| 13 | * Initial adoption to PL022 by: |
| 14 | * Sachin Verma <sachin.verma@st.com> |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License as published by |
| 18 | * the Free Software Foundation; either version 2 of the License, or |
| 19 | * (at your option) any later version. |
| 20 | * |
| 21 | * This program is distributed in the hope that it will be useful, |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 24 | * GNU General Public License for more details. |
| 25 | */ |
| 26 | |
| 27 | /* |
| 28 | * TODO: |
| 29 | * - add timeout on polled transfers |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 30 | */ |
| 31 | |
| 32 | #include <linux/init.h> |
| 33 | #include <linux/module.h> |
| 34 | #include <linux/device.h> |
| 35 | #include <linux/ioport.h> |
| 36 | #include <linux/errno.h> |
| 37 | #include <linux/interrupt.h> |
| 38 | #include <linux/spi/spi.h> |
| 39 | #include <linux/workqueue.h> |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 40 | #include <linux/delay.h> |
| 41 | #include <linux/clk.h> |
| 42 | #include <linux/err.h> |
| 43 | #include <linux/amba/bus.h> |
| 44 | #include <linux/amba/pl022.h> |
| 45 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 46 | #include <linux/slab.h> |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 47 | #include <linux/dmaengine.h> |
| 48 | #include <linux/dma-mapping.h> |
| 49 | #include <linux/scatterlist.h> |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 50 | |
| 51 | /* |
| 52 | * This macro is used to define some register default values. |
| 53 | * reg is masked with mask, the OR:ed with an (again masked) |
| 54 | * val shifted sb steps to the left. |
| 55 | */ |
| 56 | #define SSP_WRITE_BITS(reg, val, mask, sb) \ |
| 57 | ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) |
| 58 | |
| 59 | /* |
| 60 | * This macro is also used to define some default values. |
| 61 | * It will just shift val by sb steps to the left and mask |
| 62 | * the result with mask. |
| 63 | */ |
| 64 | #define GEN_MASK_BITS(val, mask, sb) \ |
| 65 | (((val)<<(sb)) & (mask)) |
| 66 | |
| 67 | #define DRIVE_TX 0 |
| 68 | #define DO_NOT_DRIVE_TX 1 |
| 69 | |
| 70 | #define DO_NOT_QUEUE_DMA 0 |
| 71 | #define QUEUE_DMA 1 |
| 72 | |
| 73 | #define RX_TRANSFER 1 |
| 74 | #define TX_TRANSFER 2 |
| 75 | |
| 76 | /* |
| 77 | * Macros to access SSP Registers with their offsets |
| 78 | */ |
| 79 | #define SSP_CR0(r) (r + 0x000) |
| 80 | #define SSP_CR1(r) (r + 0x004) |
| 81 | #define SSP_DR(r) (r + 0x008) |
| 82 | #define SSP_SR(r) (r + 0x00C) |
| 83 | #define SSP_CPSR(r) (r + 0x010) |
| 84 | #define SSP_IMSC(r) (r + 0x014) |
| 85 | #define SSP_RIS(r) (r + 0x018) |
| 86 | #define SSP_MIS(r) (r + 0x01C) |
| 87 | #define SSP_ICR(r) (r + 0x020) |
| 88 | #define SSP_DMACR(r) (r + 0x024) |
| 89 | #define SSP_ITCR(r) (r + 0x080) |
| 90 | #define SSP_ITIP(r) (r + 0x084) |
| 91 | #define SSP_ITOP(r) (r + 0x088) |
| 92 | #define SSP_TDR(r) (r + 0x08C) |
| 93 | |
| 94 | #define SSP_PID0(r) (r + 0xFE0) |
| 95 | #define SSP_PID1(r) (r + 0xFE4) |
| 96 | #define SSP_PID2(r) (r + 0xFE8) |
| 97 | #define SSP_PID3(r) (r + 0xFEC) |
| 98 | |
| 99 | #define SSP_CID0(r) (r + 0xFF0) |
| 100 | #define SSP_CID1(r) (r + 0xFF4) |
| 101 | #define SSP_CID2(r) (r + 0xFF8) |
| 102 | #define SSP_CID3(r) (r + 0xFFC) |
| 103 | |
| 104 | /* |
| 105 | * SSP Control Register 0 - SSP_CR0 |
| 106 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 107 | #define SSP_CR0_MASK_DSS (0x0FUL << 0) |
| 108 | #define SSP_CR0_MASK_FRF (0x3UL << 4) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 109 | #define SSP_CR0_MASK_SPO (0x1UL << 6) |
| 110 | #define SSP_CR0_MASK_SPH (0x1UL << 7) |
| 111 | #define SSP_CR0_MASK_SCR (0xFFUL << 8) |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 112 | |
| 113 | /* |
| 114 | * The ST version of this block moves som bits |
| 115 | * in SSP_CR0 and extends it to 32 bits |
| 116 | */ |
| 117 | #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) |
| 118 | #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) |
| 119 | #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) |
| 120 | #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) |
| 121 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 122 | |
| 123 | /* |
| 124 | * SSP Control Register 0 - SSP_CR1 |
| 125 | */ |
| 126 | #define SSP_CR1_MASK_LBM (0x1UL << 0) |
| 127 | #define SSP_CR1_MASK_SSE (0x1UL << 1) |
| 128 | #define SSP_CR1_MASK_MS (0x1UL << 2) |
| 129 | #define SSP_CR1_MASK_SOD (0x1UL << 3) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 130 | |
| 131 | /* |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 132 | * The ST version of this block adds some bits |
| 133 | * in SSP_CR1 |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 134 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 135 | #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) |
| 136 | #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) |
| 137 | #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) |
| 138 | #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) |
| 139 | #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 140 | /* This one is only in the PL023 variant */ |
| 141 | #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 142 | |
| 143 | /* |
| 144 | * SSP Status Register - SSP_SR |
| 145 | */ |
| 146 | #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ |
| 147 | #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ |
| 148 | #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 149 | #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 150 | #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ |
| 151 | |
| 152 | /* |
| 153 | * SSP Clock Prescale Register - SSP_CPSR |
| 154 | */ |
| 155 | #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) |
| 156 | |
| 157 | /* |
| 158 | * SSP Interrupt Mask Set/Clear Register - SSP_IMSC |
| 159 | */ |
| 160 | #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ |
| 161 | #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ |
| 162 | #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ |
| 163 | #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ |
| 164 | |
| 165 | /* |
| 166 | * SSP Raw Interrupt Status Register - SSP_RIS |
| 167 | */ |
| 168 | /* Receive Overrun Raw Interrupt status */ |
| 169 | #define SSP_RIS_MASK_RORRIS (0x1UL << 0) |
| 170 | /* Receive Timeout Raw Interrupt status */ |
| 171 | #define SSP_RIS_MASK_RTRIS (0x1UL << 1) |
| 172 | /* Receive FIFO Raw Interrupt status */ |
| 173 | #define SSP_RIS_MASK_RXRIS (0x1UL << 2) |
| 174 | /* Transmit FIFO Raw Interrupt status */ |
| 175 | #define SSP_RIS_MASK_TXRIS (0x1UL << 3) |
| 176 | |
| 177 | /* |
| 178 | * SSP Masked Interrupt Status Register - SSP_MIS |
| 179 | */ |
| 180 | /* Receive Overrun Masked Interrupt status */ |
| 181 | #define SSP_MIS_MASK_RORMIS (0x1UL << 0) |
| 182 | /* Receive Timeout Masked Interrupt status */ |
| 183 | #define SSP_MIS_MASK_RTMIS (0x1UL << 1) |
| 184 | /* Receive FIFO Masked Interrupt status */ |
| 185 | #define SSP_MIS_MASK_RXMIS (0x1UL << 2) |
| 186 | /* Transmit FIFO Masked Interrupt status */ |
| 187 | #define SSP_MIS_MASK_TXMIS (0x1UL << 3) |
| 188 | |
| 189 | /* |
| 190 | * SSP Interrupt Clear Register - SSP_ICR |
| 191 | */ |
| 192 | /* Receive Overrun Raw Clear Interrupt bit */ |
| 193 | #define SSP_ICR_MASK_RORIC (0x1UL << 0) |
| 194 | /* Receive Timeout Clear Interrupt bit */ |
| 195 | #define SSP_ICR_MASK_RTIC (0x1UL << 1) |
| 196 | |
| 197 | /* |
| 198 | * SSP DMA Control Register - SSP_DMACR |
| 199 | */ |
| 200 | /* Receive DMA Enable bit */ |
| 201 | #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) |
| 202 | /* Transmit DMA Enable bit */ |
| 203 | #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) |
| 204 | |
| 205 | /* |
| 206 | * SSP Integration Test control Register - SSP_ITCR |
| 207 | */ |
| 208 | #define SSP_ITCR_MASK_ITEN (0x1UL << 0) |
| 209 | #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) |
| 210 | |
| 211 | /* |
| 212 | * SSP Integration Test Input Register - SSP_ITIP |
| 213 | */ |
| 214 | #define ITIP_MASK_SSPRXD (0x1UL << 0) |
| 215 | #define ITIP_MASK_SSPFSSIN (0x1UL << 1) |
| 216 | #define ITIP_MASK_SSPCLKIN (0x1UL << 2) |
| 217 | #define ITIP_MASK_RXDMAC (0x1UL << 3) |
| 218 | #define ITIP_MASK_TXDMAC (0x1UL << 4) |
| 219 | #define ITIP_MASK_SSPTXDIN (0x1UL << 5) |
| 220 | |
| 221 | /* |
| 222 | * SSP Integration Test output Register - SSP_ITOP |
| 223 | */ |
| 224 | #define ITOP_MASK_SSPTXD (0x1UL << 0) |
| 225 | #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) |
| 226 | #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) |
| 227 | #define ITOP_MASK_SSPOEn (0x1UL << 3) |
| 228 | #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) |
| 229 | #define ITOP_MASK_RORINTR (0x1UL << 5) |
| 230 | #define ITOP_MASK_RTINTR (0x1UL << 6) |
| 231 | #define ITOP_MASK_RXINTR (0x1UL << 7) |
| 232 | #define ITOP_MASK_TXINTR (0x1UL << 8) |
| 233 | #define ITOP_MASK_INTR (0x1UL << 9) |
| 234 | #define ITOP_MASK_RXDMABREQ (0x1UL << 10) |
| 235 | #define ITOP_MASK_RXDMASREQ (0x1UL << 11) |
| 236 | #define ITOP_MASK_TXDMABREQ (0x1UL << 12) |
| 237 | #define ITOP_MASK_TXDMASREQ (0x1UL << 13) |
| 238 | |
| 239 | /* |
| 240 | * SSP Test Data Register - SSP_TDR |
| 241 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 242 | #define TDR_MASK_TESTDATA (0xFFFFFFFF) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 243 | |
| 244 | /* |
| 245 | * Message State |
| 246 | * we use the spi_message.state (void *) pointer to |
| 247 | * hold a single state value, that's why all this |
| 248 | * (void *) casting is done here. |
| 249 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 250 | #define STATE_START ((void *) 0) |
| 251 | #define STATE_RUNNING ((void *) 1) |
| 252 | #define STATE_DONE ((void *) 2) |
| 253 | #define STATE_ERROR ((void *) -1) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 254 | |
| 255 | /* |
| 256 | * Queue State |
| 257 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 258 | #define QUEUE_RUNNING (0) |
| 259 | #define QUEUE_STOPPED (1) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 260 | /* |
| 261 | * SSP State - Whether Enabled or Disabled |
| 262 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 263 | #define SSP_DISABLED (0) |
| 264 | #define SSP_ENABLED (1) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 265 | |
| 266 | /* |
| 267 | * SSP DMA State - Whether DMA Enabled or Disabled |
| 268 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 269 | #define SSP_DMA_DISABLED (0) |
| 270 | #define SSP_DMA_ENABLED (1) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 271 | |
| 272 | /* |
| 273 | * SSP Clock Defaults |
| 274 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 275 | #define SSP_DEFAULT_CLKRATE 0x2 |
| 276 | #define SSP_DEFAULT_PRESCALE 0x40 |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 277 | |
| 278 | /* |
| 279 | * SSP Clock Parameter ranges |
| 280 | */ |
| 281 | #define CPSDVR_MIN 0x02 |
| 282 | #define CPSDVR_MAX 0xFE |
| 283 | #define SCR_MIN 0x00 |
| 284 | #define SCR_MAX 0xFF |
| 285 | |
| 286 | /* |
| 287 | * SSP Interrupt related Macros |
| 288 | */ |
| 289 | #define DEFAULT_SSP_REG_IMSC 0x0UL |
| 290 | #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC |
| 291 | #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) |
| 292 | |
| 293 | #define CLEAR_ALL_INTERRUPTS 0x3 |
| 294 | |
| 295 | |
| 296 | /* |
| 297 | * The type of reading going on on this chip |
| 298 | */ |
| 299 | enum ssp_reading { |
| 300 | READING_NULL, |
| 301 | READING_U8, |
| 302 | READING_U16, |
| 303 | READING_U32 |
| 304 | }; |
| 305 | |
| 306 | /** |
| 307 | * The type of writing going on on this chip |
| 308 | */ |
| 309 | enum ssp_writing { |
| 310 | WRITING_NULL, |
| 311 | WRITING_U8, |
| 312 | WRITING_U16, |
| 313 | WRITING_U32 |
| 314 | }; |
| 315 | |
| 316 | /** |
| 317 | * struct vendor_data - vendor-specific config parameters |
| 318 | * for PL022 derivates |
| 319 | * @fifodepth: depth of FIFOs (both) |
| 320 | * @max_bpw: maximum number of bits per word |
| 321 | * @unidir: supports unidirection transfers |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 322 | * @extended_cr: 32 bit wide control register 0 with extra |
| 323 | * features and extra features in CR1 as found in the ST variants |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 324 | * @pl023: supports a subset of the ST extensions called "PL023" |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 325 | */ |
| 326 | struct vendor_data { |
| 327 | int fifodepth; |
| 328 | int max_bpw; |
| 329 | bool unidir; |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 330 | bool extended_cr; |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 331 | bool pl023; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 332 | }; |
| 333 | |
| 334 | /** |
| 335 | * struct pl022 - This is the private SSP driver data structure |
| 336 | * @adev: AMBA device model hookup |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 337 | * @vendor: Vendor data for the IP block |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 338 | * @phybase: The physical memory where the SSP device resides |
| 339 | * @virtbase: The virtual memory where the SSP is mapped |
| 340 | * @master: SPI framework hookup |
| 341 | * @master_info: controller-specific data from machine setup |
| 342 | * @regs: SSP controller register's virtual address |
| 343 | * @pump_messages: Work struct for scheduling work to the workqueue |
| 344 | * @lock: spinlock to syncronise access to driver data |
| 345 | * @workqueue: a workqueue on which any spi_message request is queued |
| 346 | * @busy: workqueue is busy |
| 347 | * @run: workqueue is running |
| 348 | * @pump_transfers: Tasklet used in Interrupt Transfer mode |
| 349 | * @cur_msg: Pointer to current spi_message being processed |
| 350 | * @cur_transfer: Pointer to current spi_transfer |
| 351 | * @cur_chip: pointer to current clients chip(assigned from controller_state) |
| 352 | * @tx: current position in TX buffer to be read |
| 353 | * @tx_end: end position in TX buffer to be read |
| 354 | * @rx: current position in RX buffer to be written |
| 355 | * @rx_end: end position in RX buffer to be written |
| 356 | * @readingtype: the type of read currently going on |
| 357 | * @writingtype: the type or write currently going on |
| 358 | */ |
| 359 | struct pl022 { |
| 360 | struct amba_device *adev; |
| 361 | struct vendor_data *vendor; |
| 362 | resource_size_t phybase; |
| 363 | void __iomem *virtbase; |
| 364 | struct clk *clk; |
| 365 | struct spi_master *master; |
| 366 | struct pl022_ssp_controller *master_info; |
| 367 | /* Driver message queue */ |
| 368 | struct workqueue_struct *workqueue; |
| 369 | struct work_struct pump_messages; |
| 370 | spinlock_t queue_lock; |
| 371 | struct list_head queue; |
| 372 | int busy; |
| 373 | int run; |
| 374 | /* Message transfer pump */ |
| 375 | struct tasklet_struct pump_transfers; |
| 376 | struct spi_message *cur_msg; |
| 377 | struct spi_transfer *cur_transfer; |
| 378 | struct chip_data *cur_chip; |
| 379 | void *tx; |
| 380 | void *tx_end; |
| 381 | void *rx; |
| 382 | void *rx_end; |
| 383 | enum ssp_reading read; |
| 384 | enum ssp_writing write; |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 385 | u32 exp_fifo_level; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 386 | /* DMA settings */ |
| 387 | #ifdef CONFIG_DMA_ENGINE |
| 388 | struct dma_chan *dma_rx_channel; |
| 389 | struct dma_chan *dma_tx_channel; |
| 390 | struct sg_table sgt_rx; |
| 391 | struct sg_table sgt_tx; |
| 392 | char *dummypage; |
| 393 | #endif |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 394 | }; |
| 395 | |
| 396 | /** |
| 397 | * struct chip_data - To maintain runtime state of SSP for each client chip |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 398 | * @cr0: Value of control register CR0 of SSP - on later ST variants this |
| 399 | * register is 32 bits wide rather than just 16 |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 400 | * @cr1: Value of control register CR1 of SSP |
| 401 | * @dmacr: Value of DMA control Register of SSP |
| 402 | * @cpsr: Value of Clock prescale register |
| 403 | * @n_bytes: how many bytes(power of 2) reqd for a given data width of client |
| 404 | * @enable_dma: Whether to enable DMA or not |
| 405 | * @write: function ptr to be used to write when doing xfer for this chip |
| 406 | * @read: function ptr to be used to read when doing xfer for this chip |
| 407 | * @cs_control: chip select callback provided by chip |
| 408 | * @xfer_type: polling/interrupt/DMA |
| 409 | * |
| 410 | * Runtime state of the SSP controller, maintained per chip, |
| 411 | * This would be set according to the current message that would be served |
| 412 | */ |
| 413 | struct chip_data { |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 414 | u32 cr0; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 415 | u16 cr1; |
| 416 | u16 dmacr; |
| 417 | u16 cpsr; |
| 418 | u8 n_bytes; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 419 | bool enable_dma; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 420 | enum ssp_reading read; |
| 421 | enum ssp_writing write; |
| 422 | void (*cs_control) (u32 command); |
| 423 | int xfer_type; |
| 424 | }; |
| 425 | |
| 426 | /** |
| 427 | * null_cs_control - Dummy chip select function |
| 428 | * @command: select/delect the chip |
| 429 | * |
| 430 | * If no chip select function is provided by client this is used as dummy |
| 431 | * chip select |
| 432 | */ |
| 433 | static void null_cs_control(u32 command) |
| 434 | { |
| 435 | pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); |
| 436 | } |
| 437 | |
| 438 | /** |
| 439 | * giveback - current spi_message is over, schedule next message and call |
| 440 | * callback of this message. Assumes that caller already |
| 441 | * set message->status; dma and pio irqs are blocked |
| 442 | * @pl022: SSP driver private data structure |
| 443 | */ |
| 444 | static void giveback(struct pl022 *pl022) |
| 445 | { |
| 446 | struct spi_transfer *last_transfer; |
| 447 | unsigned long flags; |
| 448 | struct spi_message *msg; |
| 449 | void (*curr_cs_control) (u32 command); |
| 450 | |
| 451 | /* |
| 452 | * This local reference to the chip select function |
| 453 | * is needed because we set curr_chip to NULL |
| 454 | * as a step toward termininating the message. |
| 455 | */ |
| 456 | curr_cs_control = pl022->cur_chip->cs_control; |
| 457 | spin_lock_irqsave(&pl022->queue_lock, flags); |
| 458 | msg = pl022->cur_msg; |
| 459 | pl022->cur_msg = NULL; |
| 460 | pl022->cur_transfer = NULL; |
| 461 | pl022->cur_chip = NULL; |
| 462 | queue_work(pl022->workqueue, &pl022->pump_messages); |
| 463 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
| 464 | |
| 465 | last_transfer = list_entry(msg->transfers.prev, |
| 466 | struct spi_transfer, |
| 467 | transfer_list); |
| 468 | |
| 469 | /* Delay if requested before any change in chip select */ |
| 470 | if (last_transfer->delay_usecs) |
| 471 | /* |
| 472 | * FIXME: This runs in interrupt context. |
| 473 | * Is this really smart? |
| 474 | */ |
| 475 | udelay(last_transfer->delay_usecs); |
| 476 | |
| 477 | /* |
| 478 | * Drop chip select UNLESS cs_change is true or we are returning |
| 479 | * a message with an error, or next message is for another chip |
| 480 | */ |
| 481 | if (!last_transfer->cs_change) |
| 482 | curr_cs_control(SSP_CHIP_DESELECT); |
| 483 | else { |
| 484 | struct spi_message *next_msg; |
| 485 | |
| 486 | /* Holding of cs was hinted, but we need to make sure |
| 487 | * the next message is for the same chip. Don't waste |
| 488 | * time with the following tests unless this was hinted. |
| 489 | * |
| 490 | * We cannot postpone this until pump_messages, because |
| 491 | * after calling msg->complete (below) the driver that |
| 492 | * sent the current message could be unloaded, which |
| 493 | * could invalidate the cs_control() callback... |
| 494 | */ |
| 495 | |
| 496 | /* get a pointer to the next message, if any */ |
| 497 | spin_lock_irqsave(&pl022->queue_lock, flags); |
| 498 | if (list_empty(&pl022->queue)) |
| 499 | next_msg = NULL; |
| 500 | else |
| 501 | next_msg = list_entry(pl022->queue.next, |
| 502 | struct spi_message, queue); |
| 503 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
| 504 | |
| 505 | /* see if the next and current messages point |
| 506 | * to the same chip |
| 507 | */ |
| 508 | if (next_msg && next_msg->spi != msg->spi) |
| 509 | next_msg = NULL; |
| 510 | if (!next_msg || msg->state == STATE_ERROR) |
| 511 | curr_cs_control(SSP_CHIP_DESELECT); |
| 512 | } |
| 513 | msg->state = NULL; |
| 514 | if (msg->complete) |
| 515 | msg->complete(msg->context); |
Linus Walleij | 545074f | 2010-08-21 11:07:36 +0200 | [diff] [blame] | 516 | /* This message is completed, so let's turn off the clocks! */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 517 | clk_disable(pl022->clk); |
Linus Walleij | 545074f | 2010-08-21 11:07:36 +0200 | [diff] [blame] | 518 | amba_pclk_disable(pl022->adev); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 519 | } |
| 520 | |
| 521 | /** |
| 522 | * flush - flush the FIFO to reach a clean state |
| 523 | * @pl022: SSP driver private data structure |
| 524 | */ |
| 525 | static int flush(struct pl022 *pl022) |
| 526 | { |
| 527 | unsigned long limit = loops_per_jiffy << 1; |
| 528 | |
| 529 | dev_dbg(&pl022->adev->dev, "flush\n"); |
| 530 | do { |
| 531 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
| 532 | readw(SSP_DR(pl022->virtbase)); |
| 533 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 534 | |
| 535 | pl022->exp_fifo_level = 0; |
| 536 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 537 | return limit; |
| 538 | } |
| 539 | |
| 540 | /** |
| 541 | * restore_state - Load configuration of current chip |
| 542 | * @pl022: SSP driver private data structure |
| 543 | */ |
| 544 | static void restore_state(struct pl022 *pl022) |
| 545 | { |
| 546 | struct chip_data *chip = pl022->cur_chip; |
| 547 | |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 548 | if (pl022->vendor->extended_cr) |
| 549 | writel(chip->cr0, SSP_CR0(pl022->virtbase)); |
| 550 | else |
| 551 | writew(chip->cr0, SSP_CR0(pl022->virtbase)); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 552 | writew(chip->cr1, SSP_CR1(pl022->virtbase)); |
| 553 | writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); |
| 554 | writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); |
| 555 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
| 556 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
| 557 | } |
| 558 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 559 | /* |
| 560 | * Default SSP Register Values |
| 561 | */ |
| 562 | #define DEFAULT_SSP_REG_CR0 ( \ |
| 563 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 564 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 565 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
Linus Walleij | ee2b805 | 2009-08-15 15:12:05 +0100 | [diff] [blame] | 566 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 567 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ |
| 568 | ) |
| 569 | |
| 570 | /* ST versions have slightly different bit layout */ |
| 571 | #define DEFAULT_SSP_REG_CR0_ST ( \ |
| 572 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ |
| 573 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ |
| 574 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
| 575 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
| 576 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ |
| 577 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ |
| 578 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 579 | ) |
| 580 | |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 581 | /* The PL023 version is slightly different again */ |
| 582 | #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ |
| 583 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ |
| 584 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
| 585 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
| 586 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ |
| 587 | ) |
| 588 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 589 | #define DEFAULT_SSP_REG_CR1 ( \ |
| 590 | GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ |
| 591 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ |
| 592 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 593 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 594 | ) |
| 595 | |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 596 | /* ST versions extend this register to use all 16 bits */ |
| 597 | #define DEFAULT_SSP_REG_CR1_ST ( \ |
| 598 | DEFAULT_SSP_REG_CR1 | \ |
| 599 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ |
| 600 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ |
| 601 | GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ |
| 602 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ |
| 603 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ |
| 604 | ) |
| 605 | |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 606 | /* |
| 607 | * The PL023 variant has further differences: no loopback mode, no microwire |
| 608 | * support, and a new clock feedback delay setting. |
| 609 | */ |
| 610 | #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ |
| 611 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ |
| 612 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ |
| 613 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ |
| 614 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ |
| 615 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ |
| 616 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ |
| 617 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ |
| 618 | GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ |
| 619 | ) |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 620 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 621 | #define DEFAULT_SSP_REG_CPSR ( \ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 622 | GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 623 | ) |
| 624 | |
| 625 | #define DEFAULT_SSP_REG_DMACR (\ |
| 626 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ |
| 627 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ |
| 628 | ) |
| 629 | |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 630 | /** |
| 631 | * load_ssp_default_config - Load default configuration for SSP |
| 632 | * @pl022: SSP driver private data structure |
| 633 | */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 634 | static void load_ssp_default_config(struct pl022 *pl022) |
| 635 | { |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 636 | if (pl022->vendor->pl023) { |
| 637 | writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); |
| 638 | writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); |
| 639 | } else if (pl022->vendor->extended_cr) { |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 640 | writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); |
| 641 | writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); |
| 642 | } else { |
| 643 | writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); |
| 644 | writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); |
| 645 | } |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 646 | writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); |
| 647 | writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); |
| 648 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
| 649 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
| 650 | } |
| 651 | |
| 652 | /** |
| 653 | * This will write to TX and read from RX according to the parameters |
| 654 | * set in pl022. |
| 655 | */ |
| 656 | static void readwriter(struct pl022 *pl022) |
| 657 | { |
| 658 | |
| 659 | /* |
| 660 | * The FIFO depth is different inbetween primecell variants. |
| 661 | * I believe filling in too much in the FIFO might cause |
| 662 | * errons in 8bit wide transfers on ARM variants (just 8 words |
| 663 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. |
| 664 | * |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 665 | * To prevent this issue, the TX FIFO is only filled to the |
| 666 | * unused RX FIFO fill length, regardless of what the TX |
| 667 | * FIFO status flag indicates. |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 668 | */ |
| 669 | dev_dbg(&pl022->adev->dev, |
| 670 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", |
| 671 | __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); |
| 672 | |
| 673 | /* Read as much as you can */ |
| 674 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
| 675 | && (pl022->rx < pl022->rx_end)) { |
| 676 | switch (pl022->read) { |
| 677 | case READING_NULL: |
| 678 | readw(SSP_DR(pl022->virtbase)); |
| 679 | break; |
| 680 | case READING_U8: |
| 681 | *(u8 *) (pl022->rx) = |
| 682 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; |
| 683 | break; |
| 684 | case READING_U16: |
| 685 | *(u16 *) (pl022->rx) = |
| 686 | (u16) readw(SSP_DR(pl022->virtbase)); |
| 687 | break; |
| 688 | case READING_U32: |
| 689 | *(u32 *) (pl022->rx) = |
| 690 | readl(SSP_DR(pl022->virtbase)); |
| 691 | break; |
| 692 | } |
| 693 | pl022->rx += (pl022->cur_chip->n_bytes); |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 694 | pl022->exp_fifo_level--; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 695 | } |
| 696 | /* |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 697 | * Write as much as possible up to the RX FIFO size |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 698 | */ |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 699 | while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 700 | && (pl022->tx < pl022->tx_end)) { |
| 701 | switch (pl022->write) { |
| 702 | case WRITING_NULL: |
| 703 | writew(0x0, SSP_DR(pl022->virtbase)); |
| 704 | break; |
| 705 | case WRITING_U8: |
| 706 | writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); |
| 707 | break; |
| 708 | case WRITING_U16: |
| 709 | writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); |
| 710 | break; |
| 711 | case WRITING_U32: |
| 712 | writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); |
| 713 | break; |
| 714 | } |
| 715 | pl022->tx += (pl022->cur_chip->n_bytes); |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 716 | pl022->exp_fifo_level++; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 717 | /* |
| 718 | * This inner reader takes care of things appearing in the RX |
| 719 | * FIFO as we're transmitting. This will happen a lot since the |
| 720 | * clock starts running when you put things into the TX FIFO, |
| 721 | * and then things are continously clocked into the RX FIFO. |
| 722 | */ |
| 723 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
| 724 | && (pl022->rx < pl022->rx_end)) { |
| 725 | switch (pl022->read) { |
| 726 | case READING_NULL: |
| 727 | readw(SSP_DR(pl022->virtbase)); |
| 728 | break; |
| 729 | case READING_U8: |
| 730 | *(u8 *) (pl022->rx) = |
| 731 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; |
| 732 | break; |
| 733 | case READING_U16: |
| 734 | *(u16 *) (pl022->rx) = |
| 735 | (u16) readw(SSP_DR(pl022->virtbase)); |
| 736 | break; |
| 737 | case READING_U32: |
| 738 | *(u32 *) (pl022->rx) = |
| 739 | readl(SSP_DR(pl022->virtbase)); |
| 740 | break; |
| 741 | } |
| 742 | pl022->rx += (pl022->cur_chip->n_bytes); |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 743 | pl022->exp_fifo_level--; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 744 | } |
| 745 | } |
| 746 | /* |
| 747 | * When we exit here the TX FIFO should be full and the RX FIFO |
| 748 | * should be empty |
| 749 | */ |
| 750 | } |
| 751 | |
| 752 | |
| 753 | /** |
| 754 | * next_transfer - Move to the Next transfer in the current spi message |
| 755 | * @pl022: SSP driver private data structure |
| 756 | * |
| 757 | * This function moves though the linked list of spi transfers in the |
| 758 | * current spi message and returns with the state of current spi |
| 759 | * message i.e whether its last transfer is done(STATE_DONE) or |
| 760 | * Next transfer is ready(STATE_RUNNING) |
| 761 | */ |
| 762 | static void *next_transfer(struct pl022 *pl022) |
| 763 | { |
| 764 | struct spi_message *msg = pl022->cur_msg; |
| 765 | struct spi_transfer *trans = pl022->cur_transfer; |
| 766 | |
| 767 | /* Move to next transfer */ |
| 768 | if (trans->transfer_list.next != &msg->transfers) { |
| 769 | pl022->cur_transfer = |
| 770 | list_entry(trans->transfer_list.next, |
| 771 | struct spi_transfer, transfer_list); |
| 772 | return STATE_RUNNING; |
| 773 | } |
| 774 | return STATE_DONE; |
| 775 | } |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 776 | |
| 777 | /* |
| 778 | * This DMA functionality is only compiled in if we have |
| 779 | * access to the generic DMA devices/DMA engine. |
| 780 | */ |
| 781 | #ifdef CONFIG_DMA_ENGINE |
| 782 | static void unmap_free_dma_scatter(struct pl022 *pl022) |
| 783 | { |
| 784 | /* Unmap and free the SG tables */ |
| 785 | dma_unmap_sg(&pl022->adev->dev, pl022->sgt_tx.sgl, |
| 786 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
| 787 | dma_unmap_sg(&pl022->adev->dev, pl022->sgt_rx.sgl, |
| 788 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
| 789 | sg_free_table(&pl022->sgt_rx); |
| 790 | sg_free_table(&pl022->sgt_tx); |
| 791 | } |
| 792 | |
| 793 | static void dma_callback(void *data) |
| 794 | { |
| 795 | struct pl022 *pl022 = data; |
| 796 | struct spi_message *msg = pl022->cur_msg; |
| 797 | |
| 798 | BUG_ON(!pl022->sgt_rx.sgl); |
| 799 | |
| 800 | #ifdef VERBOSE_DEBUG |
| 801 | /* |
| 802 | * Optionally dump out buffers to inspect contents, this is |
| 803 | * good if you want to convince yourself that the loopback |
| 804 | * read/write contents are the same, when adopting to a new |
| 805 | * DMA engine. |
| 806 | */ |
| 807 | { |
| 808 | struct scatterlist *sg; |
| 809 | unsigned int i; |
| 810 | |
| 811 | dma_sync_sg_for_cpu(&pl022->adev->dev, |
| 812 | pl022->sgt_rx.sgl, |
| 813 | pl022->sgt_rx.nents, |
| 814 | DMA_FROM_DEVICE); |
| 815 | |
| 816 | for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { |
| 817 | dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); |
| 818 | print_hex_dump(KERN_ERR, "SPI RX: ", |
| 819 | DUMP_PREFIX_OFFSET, |
| 820 | 16, |
| 821 | 1, |
| 822 | sg_virt(sg), |
| 823 | sg_dma_len(sg), |
| 824 | 1); |
| 825 | } |
| 826 | for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { |
| 827 | dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); |
| 828 | print_hex_dump(KERN_ERR, "SPI TX: ", |
| 829 | DUMP_PREFIX_OFFSET, |
| 830 | 16, |
| 831 | 1, |
| 832 | sg_virt(sg), |
| 833 | sg_dma_len(sg), |
| 834 | 1); |
| 835 | } |
| 836 | } |
| 837 | #endif |
| 838 | |
| 839 | unmap_free_dma_scatter(pl022); |
| 840 | |
| 841 | /* Update total bytes transfered */ |
| 842 | msg->actual_length += pl022->cur_transfer->len; |
| 843 | if (pl022->cur_transfer->cs_change) |
| 844 | pl022->cur_chip-> |
| 845 | cs_control(SSP_CHIP_DESELECT); |
| 846 | |
| 847 | /* Move to next transfer */ |
| 848 | msg->state = next_transfer(pl022); |
| 849 | tasklet_schedule(&pl022->pump_transfers); |
| 850 | } |
| 851 | |
| 852 | static void setup_dma_scatter(struct pl022 *pl022, |
| 853 | void *buffer, |
| 854 | unsigned int length, |
| 855 | struct sg_table *sgtab) |
| 856 | { |
| 857 | struct scatterlist *sg; |
| 858 | int bytesleft = length; |
| 859 | void *bufp = buffer; |
| 860 | int mapbytes; |
| 861 | int i; |
| 862 | |
| 863 | if (buffer) { |
| 864 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { |
| 865 | /* |
| 866 | * If there are less bytes left than what fits |
| 867 | * in the current page (plus page alignment offset) |
| 868 | * we just feed in this, else we stuff in as much |
| 869 | * as we can. |
| 870 | */ |
| 871 | if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) |
| 872 | mapbytes = bytesleft; |
| 873 | else |
| 874 | mapbytes = PAGE_SIZE - offset_in_page(bufp); |
| 875 | sg_set_page(sg, virt_to_page(bufp), |
| 876 | mapbytes, offset_in_page(bufp)); |
| 877 | bufp += mapbytes; |
| 878 | bytesleft -= mapbytes; |
| 879 | dev_dbg(&pl022->adev->dev, |
| 880 | "set RX/TX target page @ %p, %d bytes, %d left\n", |
| 881 | bufp, mapbytes, bytesleft); |
| 882 | } |
| 883 | } else { |
| 884 | /* Map the dummy buffer on every page */ |
| 885 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { |
| 886 | if (bytesleft < PAGE_SIZE) |
| 887 | mapbytes = bytesleft; |
| 888 | else |
| 889 | mapbytes = PAGE_SIZE; |
| 890 | sg_set_page(sg, virt_to_page(pl022->dummypage), |
| 891 | mapbytes, 0); |
| 892 | bytesleft -= mapbytes; |
| 893 | dev_dbg(&pl022->adev->dev, |
| 894 | "set RX/TX to dummy page %d bytes, %d left\n", |
| 895 | mapbytes, bytesleft); |
| 896 | |
| 897 | } |
| 898 | } |
| 899 | BUG_ON(bytesleft); |
| 900 | } |
| 901 | |
| 902 | /** |
| 903 | * configure_dma - configures the channels for the next transfer |
| 904 | * @pl022: SSP driver's private data structure |
| 905 | */ |
| 906 | static int configure_dma(struct pl022 *pl022) |
| 907 | { |
| 908 | struct dma_slave_config rx_conf = { |
| 909 | .src_addr = SSP_DR(pl022->phybase), |
| 910 | .direction = DMA_FROM_DEVICE, |
| 911 | .src_maxburst = pl022->vendor->fifodepth >> 1, |
| 912 | }; |
| 913 | struct dma_slave_config tx_conf = { |
| 914 | .dst_addr = SSP_DR(pl022->phybase), |
| 915 | .direction = DMA_TO_DEVICE, |
| 916 | .dst_maxburst = pl022->vendor->fifodepth >> 1, |
| 917 | }; |
| 918 | unsigned int pages; |
| 919 | int ret; |
| 920 | int sglen; |
| 921 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
| 922 | struct dma_chan *txchan = pl022->dma_tx_channel; |
| 923 | struct dma_async_tx_descriptor *rxdesc; |
| 924 | struct dma_async_tx_descriptor *txdesc; |
| 925 | dma_cookie_t cookie; |
| 926 | |
| 927 | /* Check that the channels are available */ |
| 928 | if (!rxchan || !txchan) |
| 929 | return -ENODEV; |
| 930 | |
| 931 | switch (pl022->read) { |
| 932 | case READING_NULL: |
| 933 | /* Use the same as for writing */ |
| 934 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
| 935 | break; |
| 936 | case READING_U8: |
| 937 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
| 938 | break; |
| 939 | case READING_U16: |
| 940 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
| 941 | break; |
| 942 | case READING_U32: |
| 943 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 944 | break; |
| 945 | } |
| 946 | |
| 947 | switch (pl022->write) { |
| 948 | case WRITING_NULL: |
| 949 | /* Use the same as for reading */ |
| 950 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
| 951 | break; |
| 952 | case WRITING_U8: |
| 953 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
| 954 | break; |
| 955 | case WRITING_U16: |
| 956 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
| 957 | break; |
| 958 | case WRITING_U32: |
| 959 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;; |
| 960 | break; |
| 961 | } |
| 962 | |
| 963 | /* SPI pecularity: we need to read and write the same width */ |
| 964 | if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 965 | rx_conf.src_addr_width = tx_conf.dst_addr_width; |
| 966 | if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 967 | tx_conf.dst_addr_width = rx_conf.src_addr_width; |
| 968 | BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); |
| 969 | |
| 970 | rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG, |
| 971 | (unsigned long) &rx_conf); |
| 972 | txchan->device->device_control(txchan, DMA_SLAVE_CONFIG, |
| 973 | (unsigned long) &tx_conf); |
| 974 | |
| 975 | /* Create sglists for the transfers */ |
| 976 | pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1; |
| 977 | dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); |
| 978 | |
| 979 | ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL); |
| 980 | if (ret) |
| 981 | goto err_alloc_rx_sg; |
| 982 | |
| 983 | ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL); |
| 984 | if (ret) |
| 985 | goto err_alloc_tx_sg; |
| 986 | |
| 987 | /* Fill in the scatterlists for the RX+TX buffers */ |
| 988 | setup_dma_scatter(pl022, pl022->rx, |
| 989 | pl022->cur_transfer->len, &pl022->sgt_rx); |
| 990 | setup_dma_scatter(pl022, pl022->tx, |
| 991 | pl022->cur_transfer->len, &pl022->sgt_tx); |
| 992 | |
| 993 | /* Map DMA buffers */ |
| 994 | sglen = dma_map_sg(&pl022->adev->dev, pl022->sgt_rx.sgl, |
| 995 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
| 996 | if (!sglen) |
| 997 | goto err_rx_sgmap; |
| 998 | |
| 999 | sglen = dma_map_sg(&pl022->adev->dev, pl022->sgt_tx.sgl, |
| 1000 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
| 1001 | if (!sglen) |
| 1002 | goto err_tx_sgmap; |
| 1003 | |
| 1004 | /* Send both scatterlists */ |
| 1005 | rxdesc = rxchan->device->device_prep_slave_sg(rxchan, |
| 1006 | pl022->sgt_rx.sgl, |
| 1007 | pl022->sgt_rx.nents, |
| 1008 | DMA_FROM_DEVICE, |
| 1009 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 1010 | if (!rxdesc) |
| 1011 | goto err_rxdesc; |
| 1012 | |
| 1013 | txdesc = txchan->device->device_prep_slave_sg(txchan, |
| 1014 | pl022->sgt_tx.sgl, |
| 1015 | pl022->sgt_tx.nents, |
| 1016 | DMA_TO_DEVICE, |
| 1017 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 1018 | if (!txdesc) |
| 1019 | goto err_txdesc; |
| 1020 | |
| 1021 | /* Put the callback on the RX transfer only, that should finish last */ |
| 1022 | rxdesc->callback = dma_callback; |
| 1023 | rxdesc->callback_param = pl022; |
| 1024 | |
| 1025 | /* Submit and fire RX and TX with TX last so we're ready to read! */ |
| 1026 | cookie = rxdesc->tx_submit(rxdesc); |
| 1027 | if (dma_submit_error(cookie)) |
| 1028 | goto err_submit_rx; |
| 1029 | cookie = txdesc->tx_submit(txdesc); |
| 1030 | if (dma_submit_error(cookie)) |
| 1031 | goto err_submit_tx; |
| 1032 | rxchan->device->device_issue_pending(rxchan); |
| 1033 | txchan->device->device_issue_pending(txchan); |
| 1034 | |
| 1035 | return 0; |
| 1036 | |
| 1037 | err_submit_tx: |
| 1038 | err_submit_rx: |
| 1039 | err_txdesc: |
| 1040 | txchan->device->device_control(txchan, DMA_TERMINATE_ALL, 0); |
| 1041 | err_rxdesc: |
| 1042 | rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0); |
| 1043 | dma_unmap_sg(&pl022->adev->dev, pl022->sgt_tx.sgl, |
| 1044 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
| 1045 | err_tx_sgmap: |
| 1046 | dma_unmap_sg(&pl022->adev->dev, pl022->sgt_rx.sgl, |
| 1047 | pl022->sgt_tx.nents, DMA_FROM_DEVICE); |
| 1048 | err_rx_sgmap: |
| 1049 | sg_free_table(&pl022->sgt_tx); |
| 1050 | err_alloc_tx_sg: |
| 1051 | sg_free_table(&pl022->sgt_rx); |
| 1052 | err_alloc_rx_sg: |
| 1053 | return -ENOMEM; |
| 1054 | } |
| 1055 | |
| 1056 | static int __init pl022_dma_probe(struct pl022 *pl022) |
| 1057 | { |
| 1058 | dma_cap_mask_t mask; |
| 1059 | |
| 1060 | /* Try to acquire a generic DMA engine slave channel */ |
| 1061 | dma_cap_zero(mask); |
| 1062 | dma_cap_set(DMA_SLAVE, mask); |
| 1063 | /* |
| 1064 | * We need both RX and TX channels to do DMA, else do none |
| 1065 | * of them. |
| 1066 | */ |
| 1067 | pl022->dma_rx_channel = dma_request_channel(mask, |
| 1068 | pl022->master_info->dma_filter, |
| 1069 | pl022->master_info->dma_rx_param); |
| 1070 | if (!pl022->dma_rx_channel) { |
| 1071 | dev_err(&pl022->adev->dev, "no RX DMA channel!\n"); |
| 1072 | goto err_no_rxchan; |
| 1073 | } |
| 1074 | |
| 1075 | pl022->dma_tx_channel = dma_request_channel(mask, |
| 1076 | pl022->master_info->dma_filter, |
| 1077 | pl022->master_info->dma_tx_param); |
| 1078 | if (!pl022->dma_tx_channel) { |
| 1079 | dev_err(&pl022->adev->dev, "no TX DMA channel!\n"); |
| 1080 | goto err_no_txchan; |
| 1081 | } |
| 1082 | |
| 1083 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); |
| 1084 | if (!pl022->dummypage) { |
| 1085 | dev_err(&pl022->adev->dev, "no DMA dummypage!\n"); |
| 1086 | goto err_no_dummypage; |
| 1087 | } |
| 1088 | |
| 1089 | dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", |
| 1090 | dma_chan_name(pl022->dma_rx_channel), |
| 1091 | dma_chan_name(pl022->dma_tx_channel)); |
| 1092 | |
| 1093 | return 0; |
| 1094 | |
| 1095 | err_no_dummypage: |
| 1096 | dma_release_channel(pl022->dma_tx_channel); |
| 1097 | err_no_txchan: |
| 1098 | dma_release_channel(pl022->dma_rx_channel); |
| 1099 | pl022->dma_rx_channel = NULL; |
| 1100 | err_no_rxchan: |
| 1101 | return -ENODEV; |
| 1102 | } |
| 1103 | |
| 1104 | static void terminate_dma(struct pl022 *pl022) |
| 1105 | { |
| 1106 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
| 1107 | struct dma_chan *txchan = pl022->dma_tx_channel; |
| 1108 | |
| 1109 | rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0); |
| 1110 | txchan->device->device_control(txchan, DMA_TERMINATE_ALL, 0); |
| 1111 | unmap_free_dma_scatter(pl022); |
| 1112 | } |
| 1113 | |
| 1114 | static void pl022_dma_remove(struct pl022 *pl022) |
| 1115 | { |
| 1116 | if (pl022->busy) |
| 1117 | terminate_dma(pl022); |
| 1118 | if (pl022->dma_tx_channel) |
| 1119 | dma_release_channel(pl022->dma_tx_channel); |
| 1120 | if (pl022->dma_rx_channel) |
| 1121 | dma_release_channel(pl022->dma_rx_channel); |
| 1122 | kfree(pl022->dummypage); |
| 1123 | } |
| 1124 | |
| 1125 | #else |
| 1126 | static inline int configure_dma(struct pl022 *pl022) |
| 1127 | { |
| 1128 | return -ENODEV; |
| 1129 | } |
| 1130 | |
| 1131 | static inline int pl022_dma_probe(struct pl022 *pl022) |
| 1132 | { |
| 1133 | return 0; |
| 1134 | } |
| 1135 | |
| 1136 | static inline void pl022_dma_remove(struct pl022 *pl022) |
| 1137 | { |
| 1138 | } |
| 1139 | #endif |
| 1140 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1141 | /** |
| 1142 | * pl022_interrupt_handler - Interrupt handler for SSP controller |
| 1143 | * |
| 1144 | * This function handles interrupts generated for an interrupt based transfer. |
| 1145 | * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the |
| 1146 | * current message's state as STATE_ERROR and schedule the tasklet |
| 1147 | * pump_transfers which will do the postprocessing of the current message by |
| 1148 | * calling giveback(). Otherwise it reads data from RX FIFO till there is no |
| 1149 | * more data, and writes data in TX FIFO till it is not full. If we complete |
| 1150 | * the transfer we move to the next transfer and schedule the tasklet. |
| 1151 | */ |
| 1152 | static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) |
| 1153 | { |
| 1154 | struct pl022 *pl022 = dev_id; |
| 1155 | struct spi_message *msg = pl022->cur_msg; |
| 1156 | u16 irq_status = 0; |
| 1157 | u16 flag = 0; |
| 1158 | |
| 1159 | if (unlikely(!msg)) { |
| 1160 | dev_err(&pl022->adev->dev, |
| 1161 | "bad message state in interrupt handler"); |
| 1162 | /* Never fail */ |
| 1163 | return IRQ_HANDLED; |
| 1164 | } |
| 1165 | |
| 1166 | /* Read the Interrupt Status Register */ |
| 1167 | irq_status = readw(SSP_MIS(pl022->virtbase)); |
| 1168 | |
| 1169 | if (unlikely(!irq_status)) |
| 1170 | return IRQ_NONE; |
| 1171 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1172 | /* |
| 1173 | * This handles the FIFO interrupts, the timeout |
| 1174 | * interrupts are flatly ignored, they cannot be |
| 1175 | * trusted. |
| 1176 | */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1177 | if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { |
| 1178 | /* |
| 1179 | * Overrun interrupt - bail out since our Data has been |
| 1180 | * corrupted |
| 1181 | */ |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1182 | dev_err(&pl022->adev->dev, "FIFO overrun\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1183 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) |
| 1184 | dev_err(&pl022->adev->dev, |
| 1185 | "RXFIFO is full\n"); |
| 1186 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) |
| 1187 | dev_err(&pl022->adev->dev, |
| 1188 | "TXFIFO is full\n"); |
| 1189 | |
| 1190 | /* |
| 1191 | * Disable and clear interrupts, disable SSP, |
| 1192 | * mark message with bad status so it can be |
| 1193 | * retried. |
| 1194 | */ |
| 1195 | writew(DISABLE_ALL_INTERRUPTS, |
| 1196 | SSP_IMSC(pl022->virtbase)); |
| 1197 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
| 1198 | writew((readw(SSP_CR1(pl022->virtbase)) & |
| 1199 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); |
| 1200 | msg->state = STATE_ERROR; |
| 1201 | |
| 1202 | /* Schedule message queue handler */ |
| 1203 | tasklet_schedule(&pl022->pump_transfers); |
| 1204 | return IRQ_HANDLED; |
| 1205 | } |
| 1206 | |
| 1207 | readwriter(pl022); |
| 1208 | |
| 1209 | if ((pl022->tx == pl022->tx_end) && (flag == 0)) { |
| 1210 | flag = 1; |
| 1211 | /* Disable Transmit interrupt */ |
| 1212 | writew(readw(SSP_IMSC(pl022->virtbase)) & |
| 1213 | (~SSP_IMSC_MASK_TXIM), |
| 1214 | SSP_IMSC(pl022->virtbase)); |
| 1215 | } |
| 1216 | |
| 1217 | /* |
| 1218 | * Since all transactions must write as much as shall be read, |
| 1219 | * we can conclude the entire transaction once RX is complete. |
| 1220 | * At this point, all TX will always be finished. |
| 1221 | */ |
| 1222 | if (pl022->rx >= pl022->rx_end) { |
| 1223 | writew(DISABLE_ALL_INTERRUPTS, |
| 1224 | SSP_IMSC(pl022->virtbase)); |
| 1225 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
| 1226 | if (unlikely(pl022->rx > pl022->rx_end)) { |
| 1227 | dev_warn(&pl022->adev->dev, "read %u surplus " |
| 1228 | "bytes (did you request an odd " |
| 1229 | "number of bytes on a 16bit bus?)\n", |
| 1230 | (u32) (pl022->rx - pl022->rx_end)); |
| 1231 | } |
| 1232 | /* Update total bytes transfered */ |
| 1233 | msg->actual_length += pl022->cur_transfer->len; |
| 1234 | if (pl022->cur_transfer->cs_change) |
| 1235 | pl022->cur_chip-> |
| 1236 | cs_control(SSP_CHIP_DESELECT); |
| 1237 | /* Move to next transfer */ |
| 1238 | msg->state = next_transfer(pl022); |
| 1239 | tasklet_schedule(&pl022->pump_transfers); |
| 1240 | return IRQ_HANDLED; |
| 1241 | } |
| 1242 | |
| 1243 | return IRQ_HANDLED; |
| 1244 | } |
| 1245 | |
| 1246 | /** |
| 1247 | * This sets up the pointers to memory for the next message to |
| 1248 | * send out on the SPI bus. |
| 1249 | */ |
| 1250 | static int set_up_next_transfer(struct pl022 *pl022, |
| 1251 | struct spi_transfer *transfer) |
| 1252 | { |
| 1253 | int residue; |
| 1254 | |
| 1255 | /* Sanity check the message for this bus width */ |
| 1256 | residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; |
| 1257 | if (unlikely(residue != 0)) { |
| 1258 | dev_err(&pl022->adev->dev, |
| 1259 | "message of %u bytes to transmit but the current " |
| 1260 | "chip bus has a data width of %u bytes!\n", |
| 1261 | pl022->cur_transfer->len, |
| 1262 | pl022->cur_chip->n_bytes); |
| 1263 | dev_err(&pl022->adev->dev, "skipping this message\n"); |
| 1264 | return -EIO; |
| 1265 | } |
| 1266 | pl022->tx = (void *)transfer->tx_buf; |
| 1267 | pl022->tx_end = pl022->tx + pl022->cur_transfer->len; |
| 1268 | pl022->rx = (void *)transfer->rx_buf; |
| 1269 | pl022->rx_end = pl022->rx + pl022->cur_transfer->len; |
| 1270 | pl022->write = |
| 1271 | pl022->tx ? pl022->cur_chip->write : WRITING_NULL; |
| 1272 | pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; |
| 1273 | return 0; |
| 1274 | } |
| 1275 | |
| 1276 | /** |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1277 | * pump_transfers - Tasklet function which schedules next transfer |
| 1278 | * when running in interrupt or DMA transfer mode. |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1279 | * @data: SSP driver private data structure |
| 1280 | * |
| 1281 | */ |
| 1282 | static void pump_transfers(unsigned long data) |
| 1283 | { |
| 1284 | struct pl022 *pl022 = (struct pl022 *) data; |
| 1285 | struct spi_message *message = NULL; |
| 1286 | struct spi_transfer *transfer = NULL; |
| 1287 | struct spi_transfer *previous = NULL; |
| 1288 | |
| 1289 | /* Get current state information */ |
| 1290 | message = pl022->cur_msg; |
| 1291 | transfer = pl022->cur_transfer; |
| 1292 | |
| 1293 | /* Handle for abort */ |
| 1294 | if (message->state == STATE_ERROR) { |
| 1295 | message->status = -EIO; |
| 1296 | giveback(pl022); |
| 1297 | return; |
| 1298 | } |
| 1299 | |
| 1300 | /* Handle end of message */ |
| 1301 | if (message->state == STATE_DONE) { |
| 1302 | message->status = 0; |
| 1303 | giveback(pl022); |
| 1304 | return; |
| 1305 | } |
| 1306 | |
| 1307 | /* Delay if requested at end of transfer before CS change */ |
| 1308 | if (message->state == STATE_RUNNING) { |
| 1309 | previous = list_entry(transfer->transfer_list.prev, |
| 1310 | struct spi_transfer, |
| 1311 | transfer_list); |
| 1312 | if (previous->delay_usecs) |
| 1313 | /* |
| 1314 | * FIXME: This runs in interrupt context. |
| 1315 | * Is this really smart? |
| 1316 | */ |
| 1317 | udelay(previous->delay_usecs); |
| 1318 | |
| 1319 | /* Drop chip select only if cs_change is requested */ |
| 1320 | if (previous->cs_change) |
| 1321 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |
| 1322 | } else { |
| 1323 | /* STATE_START */ |
| 1324 | message->state = STATE_RUNNING; |
| 1325 | } |
| 1326 | |
| 1327 | if (set_up_next_transfer(pl022, transfer)) { |
| 1328 | message->state = STATE_ERROR; |
| 1329 | message->status = -EIO; |
| 1330 | giveback(pl022); |
| 1331 | return; |
| 1332 | } |
| 1333 | /* Flush the FIFOs and let's go! */ |
| 1334 | flush(pl022); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1335 | |
| 1336 | if (pl022->cur_chip->enable_dma) { |
| 1337 | if (configure_dma(pl022)) { |
| 1338 | dev_dbg(&pl022->adev->dev, |
| 1339 | "configuration of DMA failed, fall back to interrupt mode\n"); |
| 1340 | goto err_config_dma; |
| 1341 | } |
| 1342 | return; |
| 1343 | } |
| 1344 | |
| 1345 | err_config_dma: |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1346 | writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
| 1347 | } |
| 1348 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1349 | static void do_interrupt_dma_transfer(struct pl022 *pl022) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1350 | { |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1351 | u32 irqflags = ENABLE_ALL_INTERRUPTS; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1352 | |
| 1353 | /* Enable target chip */ |
| 1354 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |
| 1355 | if (set_up_next_transfer(pl022, pl022->cur_transfer)) { |
| 1356 | /* Error path */ |
| 1357 | pl022->cur_msg->state = STATE_ERROR; |
| 1358 | pl022->cur_msg->status = -EIO; |
| 1359 | giveback(pl022); |
| 1360 | return; |
| 1361 | } |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1362 | /* If we're using DMA, set up DMA here */ |
| 1363 | if (pl022->cur_chip->enable_dma) { |
| 1364 | /* Configure DMA transfer */ |
| 1365 | if (configure_dma(pl022)) { |
| 1366 | dev_dbg(&pl022->adev->dev, |
| 1367 | "configuration of DMA failed, fall back to interrupt mode\n"); |
| 1368 | goto err_config_dma; |
| 1369 | } |
| 1370 | /* Disable interrupts in DMA mode, IRQ from DMA controller */ |
| 1371 | irqflags = DISABLE_ALL_INTERRUPTS; |
| 1372 | } |
| 1373 | err_config_dma: |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1374 | /* Enable SSP, turn on interrupts */ |
| 1375 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), |
| 1376 | SSP_CR1(pl022->virtbase)); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1377 | writew(irqflags, SSP_IMSC(pl022->virtbase)); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1378 | } |
| 1379 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1380 | static void do_polling_transfer(struct pl022 *pl022) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1381 | { |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1382 | struct spi_message *message = NULL; |
| 1383 | struct spi_transfer *transfer = NULL; |
| 1384 | struct spi_transfer *previous = NULL; |
| 1385 | struct chip_data *chip; |
| 1386 | |
| 1387 | chip = pl022->cur_chip; |
| 1388 | message = pl022->cur_msg; |
| 1389 | |
| 1390 | while (message->state != STATE_DONE) { |
| 1391 | /* Handle for abort */ |
| 1392 | if (message->state == STATE_ERROR) |
| 1393 | break; |
| 1394 | transfer = pl022->cur_transfer; |
| 1395 | |
| 1396 | /* Delay if requested at end of transfer */ |
| 1397 | if (message->state == STATE_RUNNING) { |
| 1398 | previous = |
| 1399 | list_entry(transfer->transfer_list.prev, |
| 1400 | struct spi_transfer, transfer_list); |
| 1401 | if (previous->delay_usecs) |
| 1402 | udelay(previous->delay_usecs); |
| 1403 | if (previous->cs_change) |
| 1404 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |
| 1405 | } else { |
| 1406 | /* STATE_START */ |
| 1407 | message->state = STATE_RUNNING; |
| 1408 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); |
| 1409 | } |
| 1410 | |
| 1411 | /* Configuration Changing Per Transfer */ |
| 1412 | if (set_up_next_transfer(pl022, transfer)) { |
| 1413 | /* Error path */ |
| 1414 | message->state = STATE_ERROR; |
| 1415 | break; |
| 1416 | } |
| 1417 | /* Flush FIFOs and enable SSP */ |
| 1418 | flush(pl022); |
| 1419 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), |
| 1420 | SSP_CR1(pl022->virtbase)); |
| 1421 | |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1422 | dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1423 | /* FIXME: insert a timeout so we don't hang here indefinately */ |
| 1424 | while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) |
| 1425 | readwriter(pl022); |
| 1426 | |
| 1427 | /* Update total byte transfered */ |
| 1428 | message->actual_length += pl022->cur_transfer->len; |
| 1429 | if (pl022->cur_transfer->cs_change) |
| 1430 | pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); |
| 1431 | /* Move to next transfer */ |
| 1432 | message->state = next_transfer(pl022); |
| 1433 | } |
| 1434 | |
| 1435 | /* Handle end of message */ |
| 1436 | if (message->state == STATE_DONE) |
| 1437 | message->status = 0; |
| 1438 | else |
| 1439 | message->status = -EIO; |
| 1440 | |
| 1441 | giveback(pl022); |
| 1442 | return; |
| 1443 | } |
| 1444 | |
| 1445 | /** |
| 1446 | * pump_messages - Workqueue function which processes spi message queue |
| 1447 | * @data: pointer to private data of SSP driver |
| 1448 | * |
| 1449 | * This function checks if there is any spi message in the queue that |
| 1450 | * needs processing and delegate control to appropriate function |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1451 | * do_polling_transfer()/do_interrupt_dma_transfer() |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1452 | * based on the kind of the transfer |
| 1453 | * |
| 1454 | */ |
| 1455 | static void pump_messages(struct work_struct *work) |
| 1456 | { |
| 1457 | struct pl022 *pl022 = |
| 1458 | container_of(work, struct pl022, pump_messages); |
| 1459 | unsigned long flags; |
| 1460 | |
| 1461 | /* Lock queue and check for queue work */ |
| 1462 | spin_lock_irqsave(&pl022->queue_lock, flags); |
| 1463 | if (list_empty(&pl022->queue) || pl022->run == QUEUE_STOPPED) { |
| 1464 | pl022->busy = 0; |
| 1465 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
| 1466 | return; |
| 1467 | } |
| 1468 | /* Make sure we are not already running a message */ |
| 1469 | if (pl022->cur_msg) { |
| 1470 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
| 1471 | return; |
| 1472 | } |
| 1473 | /* Extract head of queue */ |
| 1474 | pl022->cur_msg = |
| 1475 | list_entry(pl022->queue.next, struct spi_message, queue); |
| 1476 | |
| 1477 | list_del_init(&pl022->cur_msg->queue); |
| 1478 | pl022->busy = 1; |
| 1479 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
| 1480 | |
| 1481 | /* Initial message state */ |
| 1482 | pl022->cur_msg->state = STATE_START; |
| 1483 | pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, |
| 1484 | struct spi_transfer, |
| 1485 | transfer_list); |
| 1486 | |
| 1487 | /* Setup the SPI using the per chip configuration */ |
| 1488 | pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); |
| 1489 | /* |
Linus Walleij | 545074f | 2010-08-21 11:07:36 +0200 | [diff] [blame] | 1490 | * We enable the clocks here, then the clocks will be disabled when |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1491 | * giveback() is called in each method (poll/interrupt/DMA) |
| 1492 | */ |
Linus Walleij | 545074f | 2010-08-21 11:07:36 +0200 | [diff] [blame] | 1493 | amba_pclk_enable(pl022->adev); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1494 | clk_enable(pl022->clk); |
| 1495 | restore_state(pl022); |
| 1496 | flush(pl022); |
| 1497 | |
| 1498 | if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) |
| 1499 | do_polling_transfer(pl022); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1500 | else |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1501 | do_interrupt_dma_transfer(pl022); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1502 | } |
| 1503 | |
| 1504 | |
| 1505 | static int __init init_queue(struct pl022 *pl022) |
| 1506 | { |
| 1507 | INIT_LIST_HEAD(&pl022->queue); |
| 1508 | spin_lock_init(&pl022->queue_lock); |
| 1509 | |
| 1510 | pl022->run = QUEUE_STOPPED; |
| 1511 | pl022->busy = 0; |
| 1512 | |
| 1513 | tasklet_init(&pl022->pump_transfers, |
| 1514 | pump_transfers, (unsigned long)pl022); |
| 1515 | |
| 1516 | INIT_WORK(&pl022->pump_messages, pump_messages); |
| 1517 | pl022->workqueue = create_singlethread_workqueue( |
| 1518 | dev_name(pl022->master->dev.parent)); |
| 1519 | if (pl022->workqueue == NULL) |
| 1520 | return -EBUSY; |
| 1521 | |
| 1522 | return 0; |
| 1523 | } |
| 1524 | |
| 1525 | |
| 1526 | static int start_queue(struct pl022 *pl022) |
| 1527 | { |
| 1528 | unsigned long flags; |
| 1529 | |
| 1530 | spin_lock_irqsave(&pl022->queue_lock, flags); |
| 1531 | |
| 1532 | if (pl022->run == QUEUE_RUNNING || pl022->busy) { |
| 1533 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
| 1534 | return -EBUSY; |
| 1535 | } |
| 1536 | |
| 1537 | pl022->run = QUEUE_RUNNING; |
| 1538 | pl022->cur_msg = NULL; |
| 1539 | pl022->cur_transfer = NULL; |
| 1540 | pl022->cur_chip = NULL; |
| 1541 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
| 1542 | |
| 1543 | queue_work(pl022->workqueue, &pl022->pump_messages); |
| 1544 | |
| 1545 | return 0; |
| 1546 | } |
| 1547 | |
| 1548 | |
| 1549 | static int stop_queue(struct pl022 *pl022) |
| 1550 | { |
| 1551 | unsigned long flags; |
| 1552 | unsigned limit = 500; |
| 1553 | int status = 0; |
| 1554 | |
| 1555 | spin_lock_irqsave(&pl022->queue_lock, flags); |
| 1556 | |
| 1557 | /* This is a bit lame, but is optimized for the common execution path. |
| 1558 | * A wait_queue on the pl022->busy could be used, but then the common |
| 1559 | * execution path (pump_messages) would be required to call wake_up or |
| 1560 | * friends on every SPI message. Do this instead */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1561 | while (!list_empty(&pl022->queue) && pl022->busy && limit--) { |
| 1562 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
| 1563 | msleep(10); |
| 1564 | spin_lock_irqsave(&pl022->queue_lock, flags); |
| 1565 | } |
| 1566 | |
| 1567 | if (!list_empty(&pl022->queue) || pl022->busy) |
| 1568 | status = -EBUSY; |
Grzegorz Sygieda | 4a12404 | 2010-05-20 22:28:30 +0000 | [diff] [blame] | 1569 | else pl022->run = QUEUE_STOPPED; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1570 | |
| 1571 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
| 1572 | |
| 1573 | return status; |
| 1574 | } |
| 1575 | |
| 1576 | static int destroy_queue(struct pl022 *pl022) |
| 1577 | { |
| 1578 | int status; |
| 1579 | |
| 1580 | status = stop_queue(pl022); |
| 1581 | /* we are unloading the module or failing to load (only two calls |
| 1582 | * to this routine), and neither call can handle a return value. |
| 1583 | * However, destroy_workqueue calls flush_workqueue, and that will |
| 1584 | * block until all work is done. If the reason that stop_queue |
| 1585 | * timed out is that the work will never finish, then it does no |
| 1586 | * good to call destroy_workqueue, so return anyway. */ |
| 1587 | if (status != 0) |
| 1588 | return status; |
| 1589 | |
| 1590 | destroy_workqueue(pl022->workqueue); |
| 1591 | |
| 1592 | return 0; |
| 1593 | } |
| 1594 | |
| 1595 | static int verify_controller_parameters(struct pl022 *pl022, |
| 1596 | struct pl022_config_chip *chip_info) |
| 1597 | { |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1598 | if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) |
| 1599 | || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { |
| 1600 | dev_err(chip_info->dev, |
| 1601 | "interface is configured incorrectly\n"); |
| 1602 | return -EINVAL; |
| 1603 | } |
| 1604 | if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && |
| 1605 | (!pl022->vendor->unidir)) { |
| 1606 | dev_err(chip_info->dev, |
| 1607 | "unidirectional mode not supported in this " |
| 1608 | "hardware version\n"); |
| 1609 | return -EINVAL; |
| 1610 | } |
| 1611 | if ((chip_info->hierarchy != SSP_MASTER) |
| 1612 | && (chip_info->hierarchy != SSP_SLAVE)) { |
| 1613 | dev_err(chip_info->dev, |
| 1614 | "hierarchy is configured incorrectly\n"); |
| 1615 | return -EINVAL; |
| 1616 | } |
| 1617 | if (((chip_info->clk_freq).cpsdvsr < CPSDVR_MIN) |
| 1618 | || ((chip_info->clk_freq).cpsdvsr > CPSDVR_MAX)) { |
| 1619 | dev_err(chip_info->dev, |
| 1620 | "cpsdvsr is configured incorrectly\n"); |
| 1621 | return -EINVAL; |
| 1622 | } |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1623 | if ((chip_info->com_mode != INTERRUPT_TRANSFER) |
| 1624 | && (chip_info->com_mode != DMA_TRANSFER) |
| 1625 | && (chip_info->com_mode != POLLING_TRANSFER)) { |
| 1626 | dev_err(chip_info->dev, |
| 1627 | "Communication mode is configured incorrectly\n"); |
| 1628 | return -EINVAL; |
| 1629 | } |
| 1630 | if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM) |
| 1631 | || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) { |
| 1632 | dev_err(chip_info->dev, |
| 1633 | "RX FIFO Trigger Level is configured incorrectly\n"); |
| 1634 | return -EINVAL; |
| 1635 | } |
| 1636 | if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC) |
| 1637 | || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) { |
| 1638 | dev_err(chip_info->dev, |
| 1639 | "TX FIFO Trigger Level is configured incorrectly\n"); |
| 1640 | return -EINVAL; |
| 1641 | } |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1642 | if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { |
| 1643 | if ((chip_info->ctrl_len < SSP_BITS_4) |
| 1644 | || (chip_info->ctrl_len > SSP_BITS_32)) { |
| 1645 | dev_err(chip_info->dev, |
| 1646 | "CTRL LEN is configured incorrectly\n"); |
| 1647 | return -EINVAL; |
| 1648 | } |
| 1649 | if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) |
| 1650 | && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { |
| 1651 | dev_err(chip_info->dev, |
| 1652 | "Wait State is configured incorrectly\n"); |
| 1653 | return -EINVAL; |
| 1654 | } |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1655 | /* Half duplex is only available in the ST Micro version */ |
| 1656 | if (pl022->vendor->extended_cr) { |
| 1657 | if ((chip_info->duplex != |
| 1658 | SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) |
| 1659 | && (chip_info->duplex != |
Julia Lawall | 4a4fd47 | 2010-09-29 17:31:30 +0900 | [diff] [blame] | 1660 | SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1661 | dev_err(chip_info->dev, |
| 1662 | "Microwire duplex mode is configured incorrectly\n"); |
| 1663 | return -EINVAL; |
Julia Lawall | 4a4fd47 | 2010-09-29 17:31:30 +0900 | [diff] [blame] | 1664 | } |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1665 | } else { |
| 1666 | if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) |
| 1667 | dev_err(chip_info->dev, |
| 1668 | "Microwire half duplex mode requested," |
| 1669 | " but this is only available in the" |
| 1670 | " ST version of PL022\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1671 | return -EINVAL; |
| 1672 | } |
| 1673 | } |
| 1674 | if (chip_info->cs_control == NULL) { |
| 1675 | dev_warn(chip_info->dev, |
| 1676 | "Chip Select Function is NULL for this chip\n"); |
| 1677 | chip_info->cs_control = null_cs_control; |
| 1678 | } |
| 1679 | return 0; |
| 1680 | } |
| 1681 | |
| 1682 | /** |
| 1683 | * pl022_transfer - transfer function registered to SPI master framework |
| 1684 | * @spi: spi device which is requesting transfer |
| 1685 | * @msg: spi message which is to handled is queued to driver queue |
| 1686 | * |
| 1687 | * This function is registered to the SPI framework for this SPI master |
| 1688 | * controller. It will queue the spi_message in the queue of driver if |
| 1689 | * the queue is not stopped and return. |
| 1690 | */ |
| 1691 | static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) |
| 1692 | { |
| 1693 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); |
| 1694 | unsigned long flags; |
| 1695 | |
| 1696 | spin_lock_irqsave(&pl022->queue_lock, flags); |
| 1697 | |
| 1698 | if (pl022->run == QUEUE_STOPPED) { |
| 1699 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
| 1700 | return -ESHUTDOWN; |
| 1701 | } |
| 1702 | msg->actual_length = 0; |
| 1703 | msg->status = -EINPROGRESS; |
| 1704 | msg->state = STATE_START; |
| 1705 | |
| 1706 | list_add_tail(&msg->queue, &pl022->queue); |
| 1707 | if (pl022->run == QUEUE_RUNNING && !pl022->busy) |
| 1708 | queue_work(pl022->workqueue, &pl022->pump_messages); |
| 1709 | |
| 1710 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
| 1711 | return 0; |
| 1712 | } |
| 1713 | |
| 1714 | static int calculate_effective_freq(struct pl022 *pl022, |
| 1715 | int freq, |
| 1716 | struct ssp_clock_params *clk_freq) |
| 1717 | { |
| 1718 | /* Lets calculate the frequency parameters */ |
| 1719 | u16 cpsdvsr = 2; |
| 1720 | u16 scr = 0; |
| 1721 | bool freq_found = false; |
| 1722 | u32 rate; |
| 1723 | u32 max_tclk; |
| 1724 | u32 min_tclk; |
| 1725 | |
| 1726 | rate = clk_get_rate(pl022->clk); |
| 1727 | /* cpsdvscr = 2 & scr 0 */ |
| 1728 | max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN))); |
| 1729 | /* cpsdvsr = 254 & scr = 255 */ |
| 1730 | min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX))); |
| 1731 | |
| 1732 | if ((freq <= max_tclk) && (freq >= min_tclk)) { |
| 1733 | while (cpsdvsr <= CPSDVR_MAX && !freq_found) { |
| 1734 | while (scr <= SCR_MAX && !freq_found) { |
| 1735 | if ((rate / |
| 1736 | (cpsdvsr * (1 + scr))) > freq) |
| 1737 | scr += 1; |
| 1738 | else { |
| 1739 | /* |
| 1740 | * This bool is made true when |
| 1741 | * effective frequency >= |
| 1742 | * target frequency is found |
| 1743 | */ |
| 1744 | freq_found = true; |
| 1745 | if ((rate / |
| 1746 | (cpsdvsr * (1 + scr))) != freq) { |
| 1747 | if (scr == SCR_MIN) { |
| 1748 | cpsdvsr -= 2; |
| 1749 | scr = SCR_MAX; |
| 1750 | } else |
| 1751 | scr -= 1; |
| 1752 | } |
| 1753 | } |
| 1754 | } |
| 1755 | if (!freq_found) { |
| 1756 | cpsdvsr += 2; |
| 1757 | scr = SCR_MIN; |
| 1758 | } |
| 1759 | } |
| 1760 | if (cpsdvsr != 0) { |
| 1761 | dev_dbg(&pl022->adev->dev, |
| 1762 | "SSP Effective Frequency is %u\n", |
| 1763 | (rate / (cpsdvsr * (1 + scr)))); |
| 1764 | clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF); |
| 1765 | clk_freq->scr = (u8) (scr & 0xFF); |
| 1766 | dev_dbg(&pl022->adev->dev, |
| 1767 | "SSP cpsdvsr = %d, scr = %d\n", |
| 1768 | clk_freq->cpsdvsr, clk_freq->scr); |
| 1769 | } |
| 1770 | } else { |
| 1771 | dev_err(&pl022->adev->dev, |
| 1772 | "controller data is incorrect: out of range frequency"); |
| 1773 | return -EINVAL; |
| 1774 | } |
| 1775 | return 0; |
| 1776 | } |
| 1777 | |
| 1778 | /** |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1779 | * pl022_setup - setup function registered to SPI master framework |
| 1780 | * @spi: spi device which is requesting setup |
| 1781 | * |
| 1782 | * This function is registered to the SPI framework for this SPI master |
| 1783 | * controller. If it is the first time when setup is called by this device, |
| 1784 | * this function will initialize the runtime state for this chip and save |
| 1785 | * the same in the device structure. Else it will update the runtime info |
| 1786 | * with the updated chip info. Nothing is really being written to the |
| 1787 | * controller hardware here, that is not done until the actual transfer |
| 1788 | * commence. |
| 1789 | */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1790 | static int pl022_setup(struct spi_device *spi) |
| 1791 | { |
| 1792 | struct pl022_config_chip *chip_info; |
| 1793 | struct chip_data *chip; |
| 1794 | int status = 0; |
| 1795 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 1796 | unsigned int bits = spi->bits_per_word; |
| 1797 | u32 tmp; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1798 | |
| 1799 | if (!spi->max_speed_hz) |
| 1800 | return -EINVAL; |
| 1801 | |
| 1802 | /* Get controller_state if one is supplied */ |
| 1803 | chip = spi_get_ctldata(spi); |
| 1804 | |
| 1805 | if (chip == NULL) { |
| 1806 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
| 1807 | if (!chip) { |
| 1808 | dev_err(&spi->dev, |
| 1809 | "cannot allocate controller state\n"); |
| 1810 | return -ENOMEM; |
| 1811 | } |
| 1812 | dev_dbg(&spi->dev, |
| 1813 | "allocated memory for controller's runtime state\n"); |
| 1814 | } |
| 1815 | |
| 1816 | /* Get controller data if one is supplied */ |
| 1817 | chip_info = spi->controller_data; |
| 1818 | |
| 1819 | if (chip_info == NULL) { |
| 1820 | /* spi_board_info.controller_data not is supplied */ |
| 1821 | dev_dbg(&spi->dev, |
| 1822 | "using default controller_data settings\n"); |
| 1823 | |
| 1824 | chip_info = |
| 1825 | kzalloc(sizeof(struct pl022_config_chip), GFP_KERNEL); |
| 1826 | |
| 1827 | if (!chip_info) { |
| 1828 | dev_err(&spi->dev, |
| 1829 | "cannot allocate controller data\n"); |
| 1830 | status = -ENOMEM; |
| 1831 | goto err_first_setup; |
| 1832 | } |
| 1833 | |
| 1834 | dev_dbg(&spi->dev, "allocated memory for controller data\n"); |
| 1835 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1836 | /* |
| 1837 | * Set controller data default values: |
| 1838 | * Polling is supported by default |
| 1839 | */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1840 | chip_info->com_mode = POLLING_TRANSFER; |
| 1841 | chip_info->iface = SSP_INTERFACE_MOTOROLA_SPI; |
| 1842 | chip_info->hierarchy = SSP_SLAVE; |
| 1843 | chip_info->slave_tx_disable = DO_NOT_DRIVE_TX; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1844 | chip_info->rx_lev_trig = SSP_RX_1_OR_MORE_ELEM; |
| 1845 | chip_info->tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1846 | chip_info->ctrl_len = SSP_BITS_8; |
| 1847 | chip_info->wait_state = SSP_MWIRE_WAIT_ZERO; |
| 1848 | chip_info->duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX; |
| 1849 | chip_info->cs_control = null_cs_control; |
| 1850 | } else { |
| 1851 | dev_dbg(&spi->dev, |
| 1852 | "using user supplied controller_data settings\n"); |
| 1853 | } |
| 1854 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1855 | /* Pointer back to the SPI device */ |
| 1856 | chip_info->dev = &spi->dev; |
| 1857 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1858 | /* |
| 1859 | * We can override with custom divisors, else we use the board |
| 1860 | * frequency setting |
| 1861 | */ |
| 1862 | if ((0 == chip_info->clk_freq.cpsdvsr) |
| 1863 | && (0 == chip_info->clk_freq.scr)) { |
| 1864 | status = calculate_effective_freq(pl022, |
| 1865 | spi->max_speed_hz, |
| 1866 | &chip_info->clk_freq); |
| 1867 | if (status < 0) |
| 1868 | goto err_config_params; |
| 1869 | } else { |
| 1870 | if ((chip_info->clk_freq.cpsdvsr % 2) != 0) |
| 1871 | chip_info->clk_freq.cpsdvsr = |
| 1872 | chip_info->clk_freq.cpsdvsr - 1; |
| 1873 | } |
| 1874 | status = verify_controller_parameters(pl022, chip_info); |
| 1875 | if (status) { |
| 1876 | dev_err(&spi->dev, "controller data is incorrect"); |
| 1877 | goto err_config_params; |
| 1878 | } |
| 1879 | /* Now set controller state based on controller data */ |
| 1880 | chip->xfer_type = chip_info->com_mode; |
| 1881 | chip->cs_control = chip_info->cs_control; |
| 1882 | |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 1883 | if (bits <= 3) { |
| 1884 | /* PL022 doesn't support less than 4-bits */ |
| 1885 | status = -ENOTSUPP; |
| 1886 | goto err_config_params; |
| 1887 | } else if (bits <= 8) { |
| 1888 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1889 | chip->n_bytes = 1; |
| 1890 | chip->read = READING_U8; |
| 1891 | chip->write = WRITING_U8; |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 1892 | } else if (bits <= 16) { |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1893 | dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); |
| 1894 | chip->n_bytes = 2; |
| 1895 | chip->read = READING_U16; |
| 1896 | chip->write = WRITING_U16; |
| 1897 | } else { |
| 1898 | if (pl022->vendor->max_bpw >= 32) { |
| 1899 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); |
| 1900 | chip->n_bytes = 4; |
| 1901 | chip->read = READING_U32; |
| 1902 | chip->write = WRITING_U32; |
| 1903 | } else { |
| 1904 | dev_err(&spi->dev, |
| 1905 | "illegal data size for this controller!\n"); |
| 1906 | dev_err(&spi->dev, |
| 1907 | "a standard pl022 can only handle " |
| 1908 | "1 <= n <= 16 bit words\n"); |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 1909 | status = -ENOTSUPP; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1910 | goto err_config_params; |
| 1911 | } |
| 1912 | } |
| 1913 | |
| 1914 | /* Now Initialize all register settings required for this chip */ |
| 1915 | chip->cr0 = 0; |
| 1916 | chip->cr1 = 0; |
| 1917 | chip->dmacr = 0; |
| 1918 | chip->cpsr = 0; |
| 1919 | if ((chip_info->com_mode == DMA_TRANSFER) |
| 1920 | && ((pl022->master_info)->enable_dma)) { |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1921 | chip->enable_dma = true; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1922 | dev_dbg(&spi->dev, "DMA mode set in controller state\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1923 | if (status < 0) |
| 1924 | goto err_config_params; |
| 1925 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
| 1926 | SSP_DMACR_MASK_RXDMAE, 0); |
| 1927 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
| 1928 | SSP_DMACR_MASK_TXDMAE, 1); |
| 1929 | } else { |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1930 | chip->enable_dma = false; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1931 | dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); |
| 1932 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, |
| 1933 | SSP_DMACR_MASK_RXDMAE, 0); |
| 1934 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, |
| 1935 | SSP_DMACR_MASK_TXDMAE, 1); |
| 1936 | } |
| 1937 | |
| 1938 | chip->cpsr = chip_info->clk_freq.cpsdvsr; |
| 1939 | |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1940 | /* Special setup for the ST micro extended control registers */ |
| 1941 | if (pl022->vendor->extended_cr) { |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 1942 | u32 etx; |
| 1943 | |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 1944 | if (pl022->vendor->pl023) { |
| 1945 | /* These bits are only in the PL023 */ |
| 1946 | SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, |
| 1947 | SSP_CR1_MASK_FBCLKDEL_ST, 13); |
| 1948 | } else { |
| 1949 | /* These bits are in the PL022 but not PL023 */ |
| 1950 | SSP_WRITE_BITS(chip->cr0, chip_info->duplex, |
| 1951 | SSP_CR0_MASK_HALFDUP_ST, 5); |
| 1952 | SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, |
| 1953 | SSP_CR0_MASK_CSS_ST, 16); |
| 1954 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, |
| 1955 | SSP_CR0_MASK_FRF_ST, 21); |
| 1956 | SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, |
| 1957 | SSP_CR1_MASK_MWAIT_ST, 6); |
| 1958 | } |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 1959 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1960 | SSP_CR0_MASK_DSS_ST, 0); |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 1961 | |
| 1962 | if (spi->mode & SPI_LSB_FIRST) { |
| 1963 | tmp = SSP_RX_LSB; |
| 1964 | etx = SSP_TX_LSB; |
| 1965 | } else { |
| 1966 | tmp = SSP_RX_MSB; |
| 1967 | etx = SSP_TX_MSB; |
| 1968 | } |
| 1969 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); |
| 1970 | SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1971 | SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, |
| 1972 | SSP_CR1_MASK_RXIFLSEL_ST, 7); |
| 1973 | SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, |
| 1974 | SSP_CR1_MASK_TXIFLSEL_ST, 10); |
| 1975 | } else { |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 1976 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1977 | SSP_CR0_MASK_DSS, 0); |
| 1978 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, |
| 1979 | SSP_CR0_MASK_FRF, 4); |
| 1980 | } |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 1981 | |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1982 | /* Stuff that is common for all versions */ |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 1983 | if (spi->mode & SPI_CPOL) |
| 1984 | tmp = SSP_CLK_POL_IDLE_HIGH; |
| 1985 | else |
| 1986 | tmp = SSP_CLK_POL_IDLE_LOW; |
| 1987 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); |
| 1988 | |
| 1989 | if (spi->mode & SPI_CPHA) |
| 1990 | tmp = SSP_CLK_SECOND_EDGE; |
| 1991 | else |
| 1992 | tmp = SSP_CLK_FIRST_EDGE; |
| 1993 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); |
| 1994 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1995 | SSP_WRITE_BITS(chip->cr0, chip_info->clk_freq.scr, SSP_CR0_MASK_SCR, 8); |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 1996 | /* Loopback is available on all versions except PL023 */ |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 1997 | if (!pl022->vendor->pl023) { |
| 1998 | if (spi->mode & SPI_LOOP) |
| 1999 | tmp = LOOPBACK_ENABLED; |
| 2000 | else |
| 2001 | tmp = LOOPBACK_DISABLED; |
| 2002 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); |
| 2003 | } |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2004 | SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); |
| 2005 | SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); |
| 2006 | SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2007 | |
| 2008 | /* Save controller_state */ |
| 2009 | spi_set_ctldata(spi, chip); |
| 2010 | return status; |
| 2011 | err_config_params: |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 2012 | spi_set_ctldata(spi, NULL); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2013 | err_first_setup: |
| 2014 | kfree(chip); |
| 2015 | return status; |
| 2016 | } |
| 2017 | |
| 2018 | /** |
| 2019 | * pl022_cleanup - cleanup function registered to SPI master framework |
| 2020 | * @spi: spi device which is requesting cleanup |
| 2021 | * |
| 2022 | * This function is registered to the SPI framework for this SPI master |
| 2023 | * controller. It will free the runtime state of chip. |
| 2024 | */ |
| 2025 | static void pl022_cleanup(struct spi_device *spi) |
| 2026 | { |
| 2027 | struct chip_data *chip = spi_get_ctldata(spi); |
| 2028 | |
| 2029 | spi_set_ctldata(spi, NULL); |
| 2030 | kfree(chip); |
| 2031 | } |
| 2032 | |
| 2033 | |
Kevin Wells | b422588 | 2010-07-27 16:39:30 +0000 | [diff] [blame] | 2034 | static int __devinit |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2035 | pl022_probe(struct amba_device *adev, struct amba_id *id) |
| 2036 | { |
| 2037 | struct device *dev = &adev->dev; |
| 2038 | struct pl022_ssp_controller *platform_info = adev->dev.platform_data; |
| 2039 | struct spi_master *master; |
| 2040 | struct pl022 *pl022 = NULL; /*Data for this driver */ |
| 2041 | int status = 0; |
| 2042 | |
| 2043 | dev_info(&adev->dev, |
| 2044 | "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); |
| 2045 | if (platform_info == NULL) { |
| 2046 | dev_err(&adev->dev, "probe - no platform data supplied\n"); |
| 2047 | status = -ENODEV; |
| 2048 | goto err_no_pdata; |
| 2049 | } |
| 2050 | |
| 2051 | /* Allocate master with space for data */ |
| 2052 | master = spi_alloc_master(dev, sizeof(struct pl022)); |
| 2053 | if (master == NULL) { |
| 2054 | dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); |
| 2055 | status = -ENOMEM; |
| 2056 | goto err_no_master; |
| 2057 | } |
| 2058 | |
| 2059 | pl022 = spi_master_get_devdata(master); |
| 2060 | pl022->master = master; |
| 2061 | pl022->master_info = platform_info; |
| 2062 | pl022->adev = adev; |
| 2063 | pl022->vendor = id->data; |
| 2064 | |
| 2065 | /* |
| 2066 | * Bus Number Which has been Assigned to this SSP controller |
| 2067 | * on this board |
| 2068 | */ |
| 2069 | master->bus_num = platform_info->bus_id; |
| 2070 | master->num_chipselect = platform_info->num_chipselect; |
| 2071 | master->cleanup = pl022_cleanup; |
| 2072 | master->setup = pl022_setup; |
| 2073 | master->transfer = pl022_transfer; |
| 2074 | |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame^] | 2075 | /* |
| 2076 | * Supports mode 0-3, loopback, and active low CS. Transfers are |
| 2077 | * always MS bit first on the original pl022. |
| 2078 | */ |
| 2079 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
| 2080 | if (pl022->vendor->extended_cr) |
| 2081 | master->mode_bits |= SPI_LSB_FIRST; |
| 2082 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2083 | dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); |
| 2084 | |
| 2085 | status = amba_request_regions(adev, NULL); |
| 2086 | if (status) |
| 2087 | goto err_no_ioregion; |
| 2088 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 2089 | pl022->phybase = adev->res.start; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2090 | pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); |
| 2091 | if (pl022->virtbase == NULL) { |
| 2092 | status = -ENOMEM; |
| 2093 | goto err_no_ioremap; |
| 2094 | } |
| 2095 | printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", |
| 2096 | adev->res.start, pl022->virtbase); |
| 2097 | |
| 2098 | pl022->clk = clk_get(&adev->dev, NULL); |
| 2099 | if (IS_ERR(pl022->clk)) { |
| 2100 | status = PTR_ERR(pl022->clk); |
| 2101 | dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); |
| 2102 | goto err_no_clk; |
| 2103 | } |
| 2104 | |
| 2105 | /* Disable SSP */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2106 | writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), |
| 2107 | SSP_CR1(pl022->virtbase)); |
| 2108 | load_ssp_default_config(pl022); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2109 | |
| 2110 | status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", |
| 2111 | pl022); |
| 2112 | if (status < 0) { |
| 2113 | dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); |
| 2114 | goto err_no_irq; |
| 2115 | } |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 2116 | |
| 2117 | /* Get DMA channels */ |
| 2118 | if (platform_info->enable_dma) { |
| 2119 | status = pl022_dma_probe(pl022); |
| 2120 | if (status != 0) |
| 2121 | goto err_no_dma; |
| 2122 | } |
| 2123 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2124 | /* Initialize and start queue */ |
| 2125 | status = init_queue(pl022); |
| 2126 | if (status != 0) { |
| 2127 | dev_err(&adev->dev, "probe - problem initializing queue\n"); |
| 2128 | goto err_init_queue; |
| 2129 | } |
| 2130 | status = start_queue(pl022); |
| 2131 | if (status != 0) { |
| 2132 | dev_err(&adev->dev, "probe - problem starting queue\n"); |
| 2133 | goto err_start_queue; |
| 2134 | } |
| 2135 | /* Register with the SPI framework */ |
| 2136 | amba_set_drvdata(adev, pl022); |
| 2137 | status = spi_register_master(master); |
| 2138 | if (status != 0) { |
| 2139 | dev_err(&adev->dev, |
| 2140 | "probe - problem registering spi master\n"); |
| 2141 | goto err_spi_register; |
| 2142 | } |
| 2143 | dev_dbg(dev, "probe succeded\n"); |
Linus Walleij | 545074f | 2010-08-21 11:07:36 +0200 | [diff] [blame] | 2144 | /* Disable the silicon block pclk and clock it when needed */ |
| 2145 | amba_pclk_disable(adev); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2146 | return 0; |
| 2147 | |
| 2148 | err_spi_register: |
| 2149 | err_start_queue: |
| 2150 | err_init_queue: |
| 2151 | destroy_queue(pl022); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 2152 | pl022_dma_remove(pl022); |
| 2153 | err_no_dma: |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2154 | free_irq(adev->irq[0], pl022); |
| 2155 | err_no_irq: |
| 2156 | clk_put(pl022->clk); |
| 2157 | err_no_clk: |
| 2158 | iounmap(pl022->virtbase); |
| 2159 | err_no_ioremap: |
| 2160 | amba_release_regions(adev); |
| 2161 | err_no_ioregion: |
| 2162 | spi_master_put(master); |
| 2163 | err_no_master: |
| 2164 | err_no_pdata: |
| 2165 | return status; |
| 2166 | } |
| 2167 | |
Kevin Wells | b422588 | 2010-07-27 16:39:30 +0000 | [diff] [blame] | 2168 | static int __devexit |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2169 | pl022_remove(struct amba_device *adev) |
| 2170 | { |
| 2171 | struct pl022 *pl022 = amba_get_drvdata(adev); |
| 2172 | int status = 0; |
| 2173 | if (!pl022) |
| 2174 | return 0; |
| 2175 | |
| 2176 | /* Remove the queue */ |
| 2177 | status = destroy_queue(pl022); |
| 2178 | if (status != 0) { |
| 2179 | dev_err(&adev->dev, |
| 2180 | "queue remove failed (%d)\n", status); |
| 2181 | return status; |
| 2182 | } |
| 2183 | load_ssp_default_config(pl022); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 2184 | pl022_dma_remove(pl022); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2185 | free_irq(adev->irq[0], pl022); |
| 2186 | clk_disable(pl022->clk); |
| 2187 | clk_put(pl022->clk); |
| 2188 | iounmap(pl022->virtbase); |
| 2189 | amba_release_regions(adev); |
| 2190 | tasklet_disable(&pl022->pump_transfers); |
| 2191 | spi_unregister_master(pl022->master); |
| 2192 | spi_master_put(pl022->master); |
| 2193 | amba_set_drvdata(adev, NULL); |
| 2194 | dev_dbg(&adev->dev, "remove succeded\n"); |
| 2195 | return 0; |
| 2196 | } |
| 2197 | |
| 2198 | #ifdef CONFIG_PM |
| 2199 | static int pl022_suspend(struct amba_device *adev, pm_message_t state) |
| 2200 | { |
| 2201 | struct pl022 *pl022 = amba_get_drvdata(adev); |
| 2202 | int status = 0; |
| 2203 | |
| 2204 | status = stop_queue(pl022); |
| 2205 | if (status) { |
| 2206 | dev_warn(&adev->dev, "suspend cannot stop queue\n"); |
| 2207 | return status; |
| 2208 | } |
| 2209 | |
Linus Walleij | 545074f | 2010-08-21 11:07:36 +0200 | [diff] [blame] | 2210 | amba_pclk_enable(adev); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2211 | load_ssp_default_config(pl022); |
Linus Walleij | 545074f | 2010-08-21 11:07:36 +0200 | [diff] [blame] | 2212 | amba_pclk_disable(adev); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2213 | dev_dbg(&adev->dev, "suspended\n"); |
| 2214 | return 0; |
| 2215 | } |
| 2216 | |
| 2217 | static int pl022_resume(struct amba_device *adev) |
| 2218 | { |
| 2219 | struct pl022 *pl022 = amba_get_drvdata(adev); |
| 2220 | int status = 0; |
| 2221 | |
| 2222 | /* Start the queue running */ |
| 2223 | status = start_queue(pl022); |
| 2224 | if (status) |
| 2225 | dev_err(&adev->dev, "problem starting queue (%d)\n", status); |
| 2226 | else |
| 2227 | dev_dbg(&adev->dev, "resumed\n"); |
| 2228 | |
| 2229 | return status; |
| 2230 | } |
| 2231 | #else |
| 2232 | #define pl022_suspend NULL |
| 2233 | #define pl022_resume NULL |
| 2234 | #endif /* CONFIG_PM */ |
| 2235 | |
| 2236 | static struct vendor_data vendor_arm = { |
| 2237 | .fifodepth = 8, |
| 2238 | .max_bpw = 16, |
| 2239 | .unidir = false, |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 2240 | .extended_cr = false, |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 2241 | .pl023 = false, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2242 | }; |
| 2243 | |
| 2244 | |
| 2245 | static struct vendor_data vendor_st = { |
| 2246 | .fifodepth = 32, |
| 2247 | .max_bpw = 32, |
| 2248 | .unidir = false, |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 2249 | .extended_cr = true, |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 2250 | .pl023 = false, |
| 2251 | }; |
| 2252 | |
| 2253 | static struct vendor_data vendor_st_pl023 = { |
| 2254 | .fifodepth = 32, |
| 2255 | .max_bpw = 32, |
| 2256 | .unidir = false, |
| 2257 | .extended_cr = true, |
| 2258 | .pl023 = true, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2259 | }; |
| 2260 | |
| 2261 | static struct amba_id pl022_ids[] = { |
| 2262 | { |
| 2263 | /* |
| 2264 | * ARM PL022 variant, this has a 16bit wide |
| 2265 | * and 8 locations deep TX/RX FIFO |
| 2266 | */ |
| 2267 | .id = 0x00041022, |
| 2268 | .mask = 0x000fffff, |
| 2269 | .data = &vendor_arm, |
| 2270 | }, |
| 2271 | { |
| 2272 | /* |
| 2273 | * ST Micro derivative, this has 32bit wide |
| 2274 | * and 32 locations deep TX/RX FIFO |
| 2275 | */ |
Srinidhi Kasagar | e89e04f | 2009-10-05 06:13:53 +0100 | [diff] [blame] | 2276 | .id = 0x01080022, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2277 | .mask = 0xffffffff, |
| 2278 | .data = &vendor_st, |
| 2279 | }, |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 2280 | { |
| 2281 | /* |
| 2282 | * ST-Ericsson derivative "PL023" (this is not |
| 2283 | * an official ARM number), this is a PL022 SSP block |
| 2284 | * stripped to SPI mode only, it has 32bit wide |
| 2285 | * and 32 locations deep TX/RX FIFO but no extended |
| 2286 | * CR0/CR1 register |
| 2287 | */ |
| 2288 | .id = 0x00080023, |
| 2289 | .mask = 0xffffffff, |
| 2290 | .data = &vendor_st_pl023, |
| 2291 | }, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2292 | { 0, 0 }, |
| 2293 | }; |
| 2294 | |
| 2295 | static struct amba_driver pl022_driver = { |
| 2296 | .drv = { |
| 2297 | .name = "ssp-pl022", |
| 2298 | }, |
| 2299 | .id_table = pl022_ids, |
| 2300 | .probe = pl022_probe, |
Kevin Wells | b422588 | 2010-07-27 16:39:30 +0000 | [diff] [blame] | 2301 | .remove = __devexit_p(pl022_remove), |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2302 | .suspend = pl022_suspend, |
| 2303 | .resume = pl022_resume, |
| 2304 | }; |
| 2305 | |
| 2306 | |
| 2307 | static int __init pl022_init(void) |
| 2308 | { |
| 2309 | return amba_driver_register(&pl022_driver); |
| 2310 | } |
| 2311 | |
Linus Walleij | 25c8e03 | 2010-09-06 11:02:12 +0200 | [diff] [blame] | 2312 | subsys_initcall(pl022_init); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2313 | |
| 2314 | static void __exit pl022_exit(void) |
| 2315 | { |
| 2316 | amba_driver_unregister(&pl022_driver); |
| 2317 | } |
| 2318 | |
| 2319 | module_exit(pl022_exit); |
| 2320 | |
| 2321 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); |
| 2322 | MODULE_DESCRIPTION("PL022 SSP Controller Driver"); |
| 2323 | MODULE_LICENSE("GPL"); |