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gerrit-public.fairphone.software / kernel / msm-4.19 / be5c7a90753fb9f74c867f74489abe822ffb4b26 / . / arch / powerpc / kvm / bookehv_interrupts.S
blob: e8ed7d659c55f8cbcdc341c07ea58a8bc26b744d [file] [log] [blame]
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
16 *
17 * Author: Varun Sethi <varun.sethi@freescale.com>
18 * Author: Scott Wood <scotwood@freescale.com>
Mihai Caramane51f8f32012-10-11 06:13:21 +0000[diff] [blame]19 * Author: Mihai Caraman <mihai.caraman@freescale.com>
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]20 *
21 * This file is derived from arch/powerpc/kvm/booke_interrupts.S
22 */
23
24#include <asm/ppc_asm.h>
25#include <asm/kvm_asm.h>
26#include <asm/reg.h>
27#include <asm/mmu-44x.h>
28#include <asm/page.h>
29#include <asm/asm-compat.h>
30#include <asm/asm-offsets.h>
31#include <asm/bitsperlong.h>
Alexander Graf1d628af2012-02-15 23:24:28 +0000[diff] [blame]32#include <asm/thread_info.h>
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]33
Mihai Caramane51f8f32012-10-11 06:13:21 +0000[diff] [blame]34#ifdef CONFIG_64BIT
35#include <asm/exception-64e.h>
36#else
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]37#include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
Mihai Caramane51f8f32012-10-11 06:13:21 +0000[diff] [blame]38#endif
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]39
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]40#define LONGBYTES (BITS_PER_LONG / 8)
41
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]42#define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES))
43
44/* The host stack layout: */
Mihai Caramane51f8f32012-10-11 06:13:21 +0000[diff] [blame]45#define HOST_R1 0 /* Implied by stwu. */
46#define HOST_CALLEE_LR PPC_LR_STKOFF
47#define HOST_RUN (HOST_CALLEE_LR + LONGBYTES)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]48/*
49 * r2 is special: it holds 'current', and it made nonvolatile in the
50 * kernel with the -ffixed-r2 gcc option.
51 */
Mihai Caramane51f8f32012-10-11 06:13:21 +0000[diff] [blame]52#define HOST_R2 (HOST_RUN + LONGBYTES)
53#define HOST_CR (HOST_R2 + LONGBYTES)
54#define HOST_NV_GPRS (HOST_CR + LONGBYTES)
Alexander Graf38df8502012-07-24 13:02:34 +0000[diff] [blame]55#define __HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
56#define HOST_NV_GPR(n) __HOST_NV_GPR(__REG_##n)
57#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + LONGBYTES)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]58#define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
Mihai Caramane51f8f32012-10-11 06:13:21 +0000[diff] [blame]59/* LR in caller stack frame. */
60#define HOST_STACK_LR (HOST_STACK_SIZE + PPC_LR_STKOFF)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]61
62#define NEED_EMU 0x00000001 /* emulation -- save nv regs */
63#define NEED_DEAR 0x00000002 /* save faulting DEAR */
64#define NEED_ESR 0x00000004 /* save faulting ESR */
65
66/*
67 * On entry:
68 * r4 = vcpu, r5 = srr0, r6 = srr1
69 * saved in vcpu: cr, ctr, r3-r13
70 */
71.macro kvm_handler_common intno, srr0, flags
Alexander Grafa2723ce2012-02-15 23:06:24 +0000[diff] [blame]72 /* Restore host stack pointer */
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]73 PPC_STL r1, VCPU_GPR(R1)(r4)
74 PPC_STL r2, VCPU_GPR(R2)(r4)
Alexander Grafa2723ce2012-02-15 23:06:24 +0000[diff] [blame]75 PPC_LL r1, VCPU_HOST_STACK(r4)
76 PPC_LL r2, HOST_R2(r1)
77
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]78 mfspr r10, SPRN_PID
79 lwz r8, VCPU_HOST_PID(r4)
80 PPC_LL r11, VCPU_SHARED(r4)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]81 PPC_STL r14, VCPU_GPR(R14)(r4) /* We need a non-volatile GPR. */
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]82 li r14, \intno
83
84 stw r10, VCPU_GUEST_PID(r4)
85 mtspr SPRN_PID, r8
86
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]87#ifdef CONFIG_KVM_EXIT_TIMING
88 /* save exit time */
891: mfspr r7, SPRN_TBRU
90 mfspr r8, SPRN_TBRL
91 mfspr r9, SPRN_TBRU
92 cmpw r9, r7
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]93 stw r8, VCPU_TIMING_EXIT_TBL(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]94 bne- 1b
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]95 stw r9, VCPU_TIMING_EXIT_TBU(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]96#endif
97
98 oris r8, r6, MSR_CE@h
Varun Sethi185e4182012-04-25 01:26:43 +0000[diff] [blame]99 PPC_STD(r6, VCPU_SHARED_MSR, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]100 ori r8, r8, MSR_ME | MSR_RI
101 PPC_STL r5, VCPU_PC(r4)
102
103 /*
104 * Make sure CE/ME/RI are set (if appropriate for exception type)
105 * whether or not the guest had it set. Since mfmsr/mtmsr are
106 * somewhat expensive, skip in the common case where the guest
107 * had all these bits set (and thus they're still set if
108 * appropriate for the exception type).
109 */
110 cmpw r6, r8
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]111 beq 1f
112 mfmsr r7
113 .if \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0
114 oris r7, r7, MSR_CE@h
115 .endif
116 .if \srr0 != SPRN_MCSRR0
117 ori r7, r7, MSR_ME | MSR_RI
118 .endif
119 mtmsr r7
1201:
121
122 .if \flags & NEED_EMU
123 /*
124 * This assumes you have external PID support.
125 * To support a bookehv CPU without external PID, you'll
126 * need to look up the TLB entry and create a temporary mapping.
127 *
128 * FIXME: we don't currently handle if the lwepx faults. PR-mode
129 * booke doesn't handle it either. Since Linux doesn't use
130 * broadcast tlbivax anymore, the only way this should happen is
131 * if the guest maps its memory execute-but-not-read, or if we
132 * somehow take a TLB miss in the middle of this entry code and
133 * evict the relevant entry. On e500mc, all kernel lowmem is
134 * bolted into TLB1 large page mappings, and we don't use
135 * broadcast invalidates, so we should not take a TLB miss here.
136 *
137 * Later we'll need to deal with faults here. Disallowing guest
138 * mappings that are execute-but-not-read could be an option on
139 * e500mc, but not on chips with an LRAT if it is used.
140 */
141
142 mfspr r3, SPRN_EPLC /* will already have correct ELPID and EGS */
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]143 PPC_STL r15, VCPU_GPR(R15)(r4)
144 PPC_STL r16, VCPU_GPR(R16)(r4)
145 PPC_STL r17, VCPU_GPR(R17)(r4)
146 PPC_STL r18, VCPU_GPR(R18)(r4)
147 PPC_STL r19, VCPU_GPR(R19)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]148 mr r8, r3
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]149 PPC_STL r20, VCPU_GPR(R20)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]150 rlwimi r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]151 PPC_STL r21, VCPU_GPR(R21)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]152 rlwimi r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]153 PPC_STL r22, VCPU_GPR(R22)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]154 rlwimi r8, r10, EPC_EPID_SHIFT, EPC_EPID
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]155 PPC_STL r23, VCPU_GPR(R23)(r4)
156 PPC_STL r24, VCPU_GPR(R24)(r4)
157 PPC_STL r25, VCPU_GPR(R25)(r4)
158 PPC_STL r26, VCPU_GPR(R26)(r4)
159 PPC_STL r27, VCPU_GPR(R27)(r4)
160 PPC_STL r28, VCPU_GPR(R28)(r4)
161 PPC_STL r29, VCPU_GPR(R29)(r4)
162 PPC_STL r30, VCPU_GPR(R30)(r4)
163 PPC_STL r31, VCPU_GPR(R31)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]164 mtspr SPRN_EPLC, r8
Alexander Graf1d628af2012-02-15 23:24:28 +0000[diff] [blame]165
166 /* disable preemption, so we are sure we hit the fixup handler */
Stuart Yoder9778b692012-07-05 04:41:35 +0000[diff] [blame]167 CURRENT_THREAD_INFO(r8, r1)
Alexander Graf1d628af2012-02-15 23:24:28 +0000[diff] [blame]168 li r7, 1
169 stw r7, TI_PREEMPT(r8)
170
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]171 isync
Alexander Graf1d628af2012-02-15 23:24:28 +0000[diff] [blame]172
173 /*
174 * In case the read goes wrong, we catch it and write an invalid value
175 * in LAST_INST instead.
176 */
1771: lwepx r9, 0, r5
1782:
179.section .fixup, "ax"
1803: li r9, KVM_INST_FETCH_FAILED
181 b 2b
182.previous
183.section __ex_table,"a"
184 PPC_LONG_ALIGN
185 PPC_LONG 1b,3b
186.previous
187
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]188 mtspr SPRN_EPLC, r3
Alexander Graf1d628af2012-02-15 23:24:28 +0000[diff] [blame]189 li r7, 0
190 stw r7, TI_PREEMPT(r8)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]191 stw r9, VCPU_LAST_INST(r4)
192 .endif
193
194 .if \flags & NEED_ESR
195 mfspr r8, SPRN_ESR
196 PPC_STL r8, VCPU_FAULT_ESR(r4)
197 .endif
198
199 .if \flags & NEED_DEAR
200 mfspr r9, SPRN_DEAR
201 PPC_STL r9, VCPU_FAULT_DEAR(r4)
202 .endif
203
204 b kvmppc_resume_host
205.endm
206
Mihai Caramane51f8f32012-10-11 06:13:21 +0000[diff] [blame]207#ifdef CONFIG_64BIT
208/* Exception types */
209#define EX_GEN 1
210#define EX_GDBELL 2
211#define EX_DBG 3
212#define EX_MC 4
213#define EX_CRIT 5
214#define EX_TLB 6
215
216/*
217 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
218 */
219.macro kvm_handler intno type scratch, paca_ex, ex_r10, ex_r11, srr0, srr1, flags
220 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
221 mr r11, r4
222 /*
223 * Get vcpu from Paca: paca->__current.thread->kvm_vcpu
224 */
225 PPC_LL r4, PACACURRENT(r13)
226 PPC_LL r4, (THREAD + THREAD_KVM_VCPU)(r4)
227 stw r10, VCPU_CR(r4)
228 PPC_STL r11, VCPU_GPR(R4)(r4)
229 PPC_STL r5, VCPU_GPR(R5)(r4)
230 .if \type == EX_CRIT
231 PPC_LL r5, (\paca_ex + EX_R13)(r13)
232 .else
233 mfspr r5, \scratch
234 .endif
235 PPC_STL r6, VCPU_GPR(R6)(r4)
236 PPC_STL r8, VCPU_GPR(R8)(r4)
237 PPC_STL r9, VCPU_GPR(R9)(r4)
238 PPC_STL r5, VCPU_GPR(R13)(r4)
239 PPC_LL r6, (\paca_ex + \ex_r10)(r13)
240 PPC_LL r8, (\paca_ex + \ex_r11)(r13)
241 PPC_STL r3, VCPU_GPR(R3)(r4)
242 PPC_STL r7, VCPU_GPR(R7)(r4)
243 PPC_STL r12, VCPU_GPR(R12)(r4)
244 PPC_STL r6, VCPU_GPR(R10)(r4)
245 PPC_STL r8, VCPU_GPR(R11)(r4)
246 mfctr r5
247 PPC_STL r5, VCPU_CTR(r4)
248 mfspr r5, \srr0
249 mfspr r6, \srr1
250 kvm_handler_common \intno, \srr0, \flags
251.endm
252
253#define EX_PARAMS(type) \
254 EX_##type, \
255 SPRN_SPRG_##type##_SCRATCH, \
256 PACA_EX##type, \
257 EX_R10, \
258 EX_R11
259
260#define EX_PARAMS_TLB \
261 EX_TLB, \
262 SPRN_SPRG_GEN_SCRATCH, \
263 PACA_EXTLB, \
264 EX_TLB_R10, \
265 EX_TLB_R11
266
267kvm_handler BOOKE_INTERRUPT_CRITICAL, EX_PARAMS(CRIT), \
268 SPRN_CSRR0, SPRN_CSRR1, 0
269kvm_handler BOOKE_INTERRUPT_MACHINE_CHECK, EX_PARAMS(MC), \
270 SPRN_MCSRR0, SPRN_MCSRR1, 0
271kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, EX_PARAMS(GEN), \
272 SPRN_SRR0, SPRN_SRR1,(NEED_EMU | NEED_DEAR | NEED_ESR)
273kvm_handler BOOKE_INTERRUPT_INST_STORAGE, EX_PARAMS(GEN), \
274 SPRN_SRR0, SPRN_SRR1, NEED_ESR
275kvm_handler BOOKE_INTERRUPT_EXTERNAL, EX_PARAMS(GEN), \
276 SPRN_SRR0, SPRN_SRR1, 0
277kvm_handler BOOKE_INTERRUPT_ALIGNMENT, EX_PARAMS(GEN), \
278 SPRN_SRR0, SPRN_SRR1,(NEED_DEAR | NEED_ESR)
279kvm_handler BOOKE_INTERRUPT_PROGRAM, EX_PARAMS(GEN), \
280 SPRN_SRR0, SPRN_SRR1,NEED_ESR
281kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, EX_PARAMS(GEN), \
282 SPRN_SRR0, SPRN_SRR1, 0
283kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, EX_PARAMS(GEN), \
284 SPRN_SRR0, SPRN_SRR1, 0
285kvm_handler BOOKE_INTERRUPT_DECREMENTER, EX_PARAMS(GEN), \
286 SPRN_SRR0, SPRN_SRR1, 0
287kvm_handler BOOKE_INTERRUPT_FIT, EX_PARAMS(GEN), \
288 SPRN_SRR0, SPRN_SRR1, 0
289kvm_handler BOOKE_INTERRUPT_WATCHDOG, EX_PARAMS(CRIT),\
290 SPRN_CSRR0, SPRN_CSRR1, 0
291/*
292 * Only bolted TLB miss exception handlers are supported for now
293 */
294kvm_handler BOOKE_INTERRUPT_DTLB_MISS, EX_PARAMS_TLB, \
295 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
296kvm_handler BOOKE_INTERRUPT_ITLB_MISS, EX_PARAMS_TLB, \
297 SPRN_SRR0, SPRN_SRR1, 0
298kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, EX_PARAMS(GEN), \
299 SPRN_SRR0, SPRN_SRR1, 0
300kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, EX_PARAMS(GEN), \
301 SPRN_SRR0, SPRN_SRR1, 0
302kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, EX_PARAMS(GEN), \
303 SPRN_SRR0, SPRN_SRR1, 0
304kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, EX_PARAMS(GEN), \
305 SPRN_SRR0, SPRN_SRR1, 0
306kvm_handler BOOKE_INTERRUPT_DOORBELL, EX_PARAMS(GEN), \
307 SPRN_SRR0, SPRN_SRR1, 0
308kvm_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, EX_PARAMS(CRIT), \
309 SPRN_CSRR0, SPRN_CSRR1, 0
310kvm_handler BOOKE_INTERRUPT_HV_PRIV, EX_PARAMS(GEN), \
311 SPRN_SRR0, SPRN_SRR1, NEED_EMU
312kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, EX_PARAMS(GEN), \
313 SPRN_SRR0, SPRN_SRR1, 0
314kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, EX_PARAMS(GDBELL), \
315 SPRN_GSRR0, SPRN_GSRR1, 0
316kvm_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, EX_PARAMS(CRIT), \
317 SPRN_CSRR0, SPRN_CSRR1, 0
318kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(DBG), \
319 SPRN_DSRR0, SPRN_DSRR1, 0
320kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(CRIT), \
321 SPRN_CSRR0, SPRN_CSRR1, 0
322#else
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]323/*
324 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
325 */
326.macro kvm_handler intno srr0, srr1, flags
327_GLOBAL(kvmppc_handler_\intno\()_\srr1)
Mihai Caramanff594742012-10-11 06:13:20 +0000[diff] [blame]328 PPC_LL r11, THREAD_KVM_VCPU(r10)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]329 PPC_STL r3, VCPU_GPR(R3)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]330 mfspr r3, SPRN_SPRG_RSCRATCH0
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]331 PPC_STL r4, VCPU_GPR(R4)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]332 PPC_LL r4, THREAD_NORMSAVE(0)(r10)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]333 PPC_STL r5, VCPU_GPR(R5)(r11)
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]334 stw r13, VCPU_CR(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]335 mfspr r5, \srr0
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]336 PPC_STL r3, VCPU_GPR(R10)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]337 PPC_LL r3, THREAD_NORMSAVE(2)(r10)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]338 PPC_STL r6, VCPU_GPR(R6)(r11)
339 PPC_STL r4, VCPU_GPR(R11)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]340 mfspr r6, \srr1
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]341 PPC_STL r7, VCPU_GPR(R7)(r11)
342 PPC_STL r8, VCPU_GPR(R8)(r11)
343 PPC_STL r9, VCPU_GPR(R9)(r11)
344 PPC_STL r3, VCPU_GPR(R13)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]345 mfctr r7
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]346 PPC_STL r12, VCPU_GPR(R12)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]347 PPC_STL r7, VCPU_CTR(r11)
348 mr r4, r11
349 kvm_handler_common \intno, \srr0, \flags
350.endm
351
352.macro kvm_lvl_handler intno scratch srr0, srr1, flags
353_GLOBAL(kvmppc_handler_\intno\()_\srr1)
354 mfspr r10, SPRN_SPRG_THREAD
Mihai Caramanff594742012-10-11 06:13:20 +0000[diff] [blame]355 PPC_LL r11, THREAD_KVM_VCPU(r10)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]356 PPC_STL r3, VCPU_GPR(R3)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]357 mfspr r3, \scratch
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]358 PPC_STL r4, VCPU_GPR(R4)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]359 PPC_LL r4, GPR9(r8)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]360 PPC_STL r5, VCPU_GPR(R5)(r11)
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]361 stw r9, VCPU_CR(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]362 mfspr r5, \srr0
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]363 PPC_STL r3, VCPU_GPR(R8)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]364 PPC_LL r3, GPR10(r8)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]365 PPC_STL r6, VCPU_GPR(R6)(r11)
366 PPC_STL r4, VCPU_GPR(R9)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]367 mfspr r6, \srr1
368 PPC_LL r4, GPR11(r8)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]369 PPC_STL r7, VCPU_GPR(R7)(r11)
370 PPC_STL r3, VCPU_GPR(R10)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]371 mfctr r7
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]372 PPC_STL r12, VCPU_GPR(R12)(r11)
373 PPC_STL r13, VCPU_GPR(R13)(r11)
374 PPC_STL r4, VCPU_GPR(R11)(r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]375 PPC_STL r7, VCPU_CTR(r11)
376 mr r4, r11
377 kvm_handler_common \intno, \srr0, \flags
378.endm
379
380kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
381 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
382kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
383 SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
384kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
Mihai Caraman99977822012-06-22 13:33:12 +0000[diff] [blame]385 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]386kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
387kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
388kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
389 SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
390kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR
391kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
392kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
393kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
394kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
395kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
396kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
397 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
398kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
399 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
400kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
401kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
402kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0
403kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0
404kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
405kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
406kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
407 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
408kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
409kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
410kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
411kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
412 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
413kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
414 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
415kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
416 SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
Mihai Caramane51f8f32012-10-11 06:13:21 +0000[diff] [blame]417#endif
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]418
419/* Registers:
420 * SPRG_SCRATCH0: guest r10
421 * r4: vcpu pointer
422 * r11: vcpu->arch.shared
423 * r14: KVM exit number
424 */
425_GLOBAL(kvmppc_resume_host)
426 /* Save remaining volatile guest register state to vcpu. */
427 mfspr r3, SPRN_VRSAVE
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]428 PPC_STL r0, VCPU_GPR(R0)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]429 mflr r5
430 mfspr r6, SPRN_SPRG4
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]431 PPC_STL r5, VCPU_LR(r4)
432 mfspr r7, SPRN_SPRG5
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]433 stw r3, VCPU_VRSAVE(r4)
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]434 PPC_STD(r6, VCPU_SHARED_SPRG4, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]435 mfspr r8, SPRN_SPRG6
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]436 PPC_STD(r7, VCPU_SHARED_SPRG5, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]437 mfspr r9, SPRN_SPRG7
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]438 PPC_STD(r8, VCPU_SHARED_SPRG6, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]439 mfxer r3
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]440 PPC_STD(r9, VCPU_SHARED_SPRG7, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]441
442 /* save guest MAS registers and restore host mas4 & mas6 */
443 mfspr r5, SPRN_MAS0
444 PPC_STL r3, VCPU_XER(r4)
445 mfspr r6, SPRN_MAS1
446 stw r5, VCPU_SHARED_MAS0(r11)
447 mfspr r7, SPRN_MAS2
448 stw r6, VCPU_SHARED_MAS1(r11)
Varun Sethi185e4182012-04-25 01:26:43 +0000[diff] [blame]449 PPC_STD(r7, VCPU_SHARED_MAS2, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]450 mfspr r5, SPRN_MAS3
451 mfspr r6, SPRN_MAS4
452 stw r5, VCPU_SHARED_MAS7_3+4(r11)
453 mfspr r7, SPRN_MAS6
454 stw r6, VCPU_SHARED_MAS4(r11)
455 mfspr r5, SPRN_MAS7
456 lwz r6, VCPU_HOST_MAS4(r4)
457 stw r7, VCPU_SHARED_MAS6(r11)
458 lwz r8, VCPU_HOST_MAS6(r4)
459 mtspr SPRN_MAS4, r6
460 stw r5, VCPU_SHARED_MAS7_3+0(r11)
461 mtspr SPRN_MAS6, r8
Alexander Grafe9ba39c2012-02-16 14:53:04 +0000[diff] [blame]462 /* Enable MAS register updates via exception */
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]463 mfspr r3, SPRN_EPCR
464 rlwinm r3, r3, 0, ~SPRN_EPCR_DMIUH
465 mtspr SPRN_EPCR, r3
466 isync
467
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]468 /* Switch to kernel stack and jump to handler. */
469 PPC_LL r3, HOST_RUN(r1)
470 mr r5, r14 /* intno */
471 mr r14, r4 /* Save vcpu pointer. */
472 bl kvmppc_handle_exit
473
474 /* Restore vcpu pointer and the nonvolatiles we used. */
475 mr r4, r14
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]476 PPC_LL r14, VCPU_GPR(R14)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]477
478 andi. r5, r3, RESUME_FLAG_NV
479 beq skip_nv_load
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]480 PPC_LL r15, VCPU_GPR(R15)(r4)
481 PPC_LL r16, VCPU_GPR(R16)(r4)
482 PPC_LL r17, VCPU_GPR(R17)(r4)
483 PPC_LL r18, VCPU_GPR(R18)(r4)
484 PPC_LL r19, VCPU_GPR(R19)(r4)
485 PPC_LL r20, VCPU_GPR(R20)(r4)
486 PPC_LL r21, VCPU_GPR(R21)(r4)
487 PPC_LL r22, VCPU_GPR(R22)(r4)
488 PPC_LL r23, VCPU_GPR(R23)(r4)
489 PPC_LL r24, VCPU_GPR(R24)(r4)
490 PPC_LL r25, VCPU_GPR(R25)(r4)
491 PPC_LL r26, VCPU_GPR(R26)(r4)
492 PPC_LL r27, VCPU_GPR(R27)(r4)
493 PPC_LL r28, VCPU_GPR(R28)(r4)
494 PPC_LL r29, VCPU_GPR(R29)(r4)
495 PPC_LL r30, VCPU_GPR(R30)(r4)
496 PPC_LL r31, VCPU_GPR(R31)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]497skip_nv_load:
498 /* Should we return to the guest? */
499 andi. r5, r3, RESUME_FLAG_HOST
500 beq lightweight_exit
501
502 srawi r3, r3, 2 /* Shift -ERR back down. */
503
504heavyweight_exit:
505 /* Not returning to guest. */
506 PPC_LL r5, HOST_STACK_LR(r1)
Alexander Graff6127712012-03-05 16:00:28 +0100[diff] [blame]507 lwz r6, HOST_CR(r1)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]508
509 /*
510 * We already saved guest volatile register state; now save the
511 * non-volatiles.
512 */
513
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]514 PPC_STL r15, VCPU_GPR(R15)(r4)
515 PPC_STL r16, VCPU_GPR(R16)(r4)
516 PPC_STL r17, VCPU_GPR(R17)(r4)
517 PPC_STL r18, VCPU_GPR(R18)(r4)
518 PPC_STL r19, VCPU_GPR(R19)(r4)
519 PPC_STL r20, VCPU_GPR(R20)(r4)
520 PPC_STL r21, VCPU_GPR(R21)(r4)
521 PPC_STL r22, VCPU_GPR(R22)(r4)
522 PPC_STL r23, VCPU_GPR(R23)(r4)
523 PPC_STL r24, VCPU_GPR(R24)(r4)
524 PPC_STL r25, VCPU_GPR(R25)(r4)
525 PPC_STL r26, VCPU_GPR(R26)(r4)
526 PPC_STL r27, VCPU_GPR(R27)(r4)
527 PPC_STL r28, VCPU_GPR(R28)(r4)
528 PPC_STL r29, VCPU_GPR(R29)(r4)
529 PPC_STL r30, VCPU_GPR(R30)(r4)
530 PPC_STL r31, VCPU_GPR(R31)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]531
532 /* Load host non-volatile register state from host stack. */
Alexander Graf38df8502012-07-24 13:02:34 +0000[diff] [blame]533 PPC_LL r14, HOST_NV_GPR(R14)(r1)
534 PPC_LL r15, HOST_NV_GPR(R15)(r1)
535 PPC_LL r16, HOST_NV_GPR(R16)(r1)
536 PPC_LL r17, HOST_NV_GPR(R17)(r1)
537 PPC_LL r18, HOST_NV_GPR(R18)(r1)
538 PPC_LL r19, HOST_NV_GPR(R19)(r1)
539 PPC_LL r20, HOST_NV_GPR(R20)(r1)
540 PPC_LL r21, HOST_NV_GPR(R21)(r1)
541 PPC_LL r22, HOST_NV_GPR(R22)(r1)
542 PPC_LL r23, HOST_NV_GPR(R23)(r1)
543 PPC_LL r24, HOST_NV_GPR(R24)(r1)
544 PPC_LL r25, HOST_NV_GPR(R25)(r1)
545 PPC_LL r26, HOST_NV_GPR(R26)(r1)
546 PPC_LL r27, HOST_NV_GPR(R27)(r1)
547 PPC_LL r28, HOST_NV_GPR(R28)(r1)
548 PPC_LL r29, HOST_NV_GPR(R29)(r1)
549 PPC_LL r30, HOST_NV_GPR(R30)(r1)
550 PPC_LL r31, HOST_NV_GPR(R31)(r1)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]551
552 /* Return to kvm_vcpu_run(). */
553 mtlr r5
Alexander Graff6127712012-03-05 16:00:28 +0100[diff] [blame]554 mtcr r6
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]555 addi r1, r1, HOST_STACK_SIZE
556 /* r3 still contains the return code from kvmppc_handle_exit(). */
557 blr
558
559/* Registers:
560 * r3: kvm_run pointer
561 * r4: vcpu pointer
562 */
563_GLOBAL(__kvmppc_vcpu_run)
564 stwu r1, -HOST_STACK_SIZE(r1)
565 PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
566
567 /* Save host state to stack. */
568 PPC_STL r3, HOST_RUN(r1)
569 mflr r3
Alexander Graff6127712012-03-05 16:00:28 +0100[diff] [blame]570 mfcr r5
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]571 PPC_STL r3, HOST_STACK_LR(r1)
572
Alexander Graff6127712012-03-05 16:00:28 +0100[diff] [blame]573 stw r5, HOST_CR(r1)
574
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]575 /* Save host non-volatile register state to stack. */
Alexander Graf38df8502012-07-24 13:02:34 +0000[diff] [blame]576 PPC_STL r14, HOST_NV_GPR(R14)(r1)
577 PPC_STL r15, HOST_NV_GPR(R15)(r1)
578 PPC_STL r16, HOST_NV_GPR(R16)(r1)
579 PPC_STL r17, HOST_NV_GPR(R17)(r1)
580 PPC_STL r18, HOST_NV_GPR(R18)(r1)
581 PPC_STL r19, HOST_NV_GPR(R19)(r1)
582 PPC_STL r20, HOST_NV_GPR(R20)(r1)
583 PPC_STL r21, HOST_NV_GPR(R21)(r1)
584 PPC_STL r22, HOST_NV_GPR(R22)(r1)
585 PPC_STL r23, HOST_NV_GPR(R23)(r1)
586 PPC_STL r24, HOST_NV_GPR(R24)(r1)
587 PPC_STL r25, HOST_NV_GPR(R25)(r1)
588 PPC_STL r26, HOST_NV_GPR(R26)(r1)
589 PPC_STL r27, HOST_NV_GPR(R27)(r1)
590 PPC_STL r28, HOST_NV_GPR(R28)(r1)
591 PPC_STL r29, HOST_NV_GPR(R29)(r1)
592 PPC_STL r30, HOST_NV_GPR(R30)(r1)
593 PPC_STL r31, HOST_NV_GPR(R31)(r1)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]594
595 /* Load guest non-volatiles. */
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]596 PPC_LL r14, VCPU_GPR(R14)(r4)
597 PPC_LL r15, VCPU_GPR(R15)(r4)
598 PPC_LL r16, VCPU_GPR(R16)(r4)
599 PPC_LL r17, VCPU_GPR(R17)(r4)
600 PPC_LL r18, VCPU_GPR(R18)(r4)
601 PPC_LL r19, VCPU_GPR(R19)(r4)
602 PPC_LL r20, VCPU_GPR(R20)(r4)
603 PPC_LL r21, VCPU_GPR(R21)(r4)
604 PPC_LL r22, VCPU_GPR(R22)(r4)
605 PPC_LL r23, VCPU_GPR(R23)(r4)
606 PPC_LL r24, VCPU_GPR(R24)(r4)
607 PPC_LL r25, VCPU_GPR(R25)(r4)
608 PPC_LL r26, VCPU_GPR(R26)(r4)
609 PPC_LL r27, VCPU_GPR(R27)(r4)
610 PPC_LL r28, VCPU_GPR(R28)(r4)
611 PPC_LL r29, VCPU_GPR(R29)(r4)
612 PPC_LL r30, VCPU_GPR(R30)(r4)
613 PPC_LL r31, VCPU_GPR(R31)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]614
615
616lightweight_exit:
617 PPC_STL r2, HOST_R2(r1)
618
619 mfspr r3, SPRN_PID
620 stw r3, VCPU_HOST_PID(r4)
621 lwz r3, VCPU_GUEST_PID(r4)
622 mtspr SPRN_PID, r3
623
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]624 PPC_LL r11, VCPU_SHARED(r4)
Alexander Grafe9ba39c2012-02-16 14:53:04 +0000[diff] [blame]625 /* Disable MAS register updates via exception */
626 mfspr r3, SPRN_EPCR
627 oris r3, r3, SPRN_EPCR_DMIUH@h
628 mtspr SPRN_EPCR, r3
629 isync
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]630 /* Save host mas4 and mas6 and load guest MAS registers */
631 mfspr r3, SPRN_MAS4
632 stw r3, VCPU_HOST_MAS4(r4)
633 mfspr r3, SPRN_MAS6
634 stw r3, VCPU_HOST_MAS6(r4)
635 lwz r3, VCPU_SHARED_MAS0(r11)
636 lwz r5, VCPU_SHARED_MAS1(r11)
Varun Sethi185e4182012-04-25 01:26:43 +0000[diff] [blame]637 PPC_LD(r6, VCPU_SHARED_MAS2, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]638 lwz r7, VCPU_SHARED_MAS7_3+4(r11)
639 lwz r8, VCPU_SHARED_MAS4(r11)
640 mtspr SPRN_MAS0, r3
641 mtspr SPRN_MAS1, r5
642 mtspr SPRN_MAS2, r6
643 mtspr SPRN_MAS3, r7
644 mtspr SPRN_MAS4, r8
645 lwz r3, VCPU_SHARED_MAS6(r11)
646 lwz r5, VCPU_SHARED_MAS7_3+0(r11)
647 mtspr SPRN_MAS6, r3
648 mtspr SPRN_MAS7, r5
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]649
650 /*
651 * Host interrupt handlers may have clobbered these guest-readable
652 * SPRGs, so we need to reload them here with the guest's values.
653 */
654 lwz r3, VCPU_VRSAVE(r4)
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]655 PPC_LD(r5, VCPU_SHARED_SPRG4, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]656 mtspr SPRN_VRSAVE, r3
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]657 PPC_LD(r6, VCPU_SHARED_SPRG5, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]658 mtspr SPRN_SPRG4W, r5
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]659 PPC_LD(r7, VCPU_SHARED_SPRG6, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]660 mtspr SPRN_SPRG5W, r6
Varun Sethi30124902012-04-25 01:27:34 +0000[diff] [blame]661 PPC_LD(r8, VCPU_SHARED_SPRG7, r11)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]662 mtspr SPRN_SPRG6W, r7
663 mtspr SPRN_SPRG7W, r8
664
665 /* Load some guest volatiles. */
666 PPC_LL r3, VCPU_LR(r4)
667 PPC_LL r5, VCPU_XER(r4)
668 PPC_LL r6, VCPU_CTR(r4)
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]669 lwz r7, VCPU_CR(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]670 PPC_LL r8, VCPU_PC(r4)
Varun Sethi185e4182012-04-25 01:26:43 +0000[diff] [blame]671 PPC_LD(r9, VCPU_SHARED_MSR, r11)
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]672 PPC_LL r0, VCPU_GPR(R0)(r4)
673 PPC_LL r1, VCPU_GPR(R1)(r4)
674 PPC_LL r2, VCPU_GPR(R2)(r4)
675 PPC_LL r10, VCPU_GPR(R10)(r4)
676 PPC_LL r11, VCPU_GPR(R11)(r4)
677 PPC_LL r12, VCPU_GPR(R12)(r4)
678 PPC_LL r13, VCPU_GPR(R13)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]679 mtlr r3
680 mtxer r5
681 mtctr r6
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]682 mtsrr0 r8
683 mtsrr1 r9
684
685#ifdef CONFIG_KVM_EXIT_TIMING
686 /* save enter time */
6871:
688 mfspr r6, SPRN_TBRU
Bharat Bhushanc0fe7b02012-03-05 01:34:08 +0000[diff] [blame]689 mfspr r9, SPRN_TBRL
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]690 mfspr r8, SPRN_TBRU
691 cmpw r8, r6
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]692 stw r9, VCPU_TIMING_LAST_ENTER_TBL(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]693 bne 1b
Mihai Caraman518f0402012-04-16 04:08:54 +0000[diff] [blame]694 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]695#endif
696
Bharat Bhushanc0fe7b02012-03-05 01:34:08 +0000[diff] [blame]697 /*
698 * Don't execute any instruction which can change CR after
699 * below instruction.
700 */
701 mtcr r7
702
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]703 /* Finish loading guest volatiles and jump to guest. */
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]704 PPC_LL r5, VCPU_GPR(R5)(r4)
705 PPC_LL r6, VCPU_GPR(R6)(r4)
706 PPC_LL r7, VCPU_GPR(R7)(r4)
707 PPC_LL r8, VCPU_GPR(R8)(r4)
708 PPC_LL r9, VCPU_GPR(R9)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]709
Michael Neulingc75df6f2012-06-25 13:33:10 +0000[diff] [blame]710 PPC_LL r3, VCPU_GPR(R3)(r4)
711 PPC_LL r4, VCPU_GPR(R4)(r4)
Scott Woodd30f6e42011-12-20 15:34:43 +0000[diff] [blame]712 rfi