Laxman Dewangan | 327156c | 2016-04-28 15:28:56 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Maxim MAX77620 MFD Driver |
| 3 | * |
| 4 | * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. |
| 5 | * |
| 6 | * Author: |
| 7 | * Laxman Dewangan <ldewangan@nvidia.com> |
| 8 | * Chaitanya Bandi <bandik@nvidia.com> |
| 9 | * Mallikarjun Kasoju <mkasoju@nvidia.com> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
| 16 | /****************** Teminology used in driver ******************** |
| 17 | * Here are some terminology used from datasheet for quick reference: |
| 18 | * Flexible Power Sequence (FPS): |
| 19 | * The Flexible Power Sequencer (FPS) allows each regulator to power up under |
| 20 | * hardware or software control. Additionally, each regulator can power on |
| 21 | * independently or among a group of other regulators with an adjustable |
| 22 | * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can |
| 23 | * be programmed to be part of a sequence allowing external regulators to be |
| 24 | * sequenced along with internal regulators. 32KHz clock can be programmed to |
| 25 | * be part of a sequence. |
| 26 | * There is 3 FPS confguration registers and all resources are configured to |
| 27 | * any of these FPS or no FPS. |
| 28 | */ |
| 29 | |
| 30 | #include <linux/i2c.h> |
| 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/mfd/core.h> |
| 33 | #include <linux/mfd/max77620.h> |
| 34 | #include <linux/module.h> |
| 35 | #include <linux/of.h> |
| 36 | #include <linux/of_device.h> |
| 37 | #include <linux/regmap.h> |
| 38 | #include <linux/slab.h> |
| 39 | |
| 40 | static struct resource gpio_resources[] = { |
| 41 | DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO), |
| 42 | }; |
| 43 | |
| 44 | static struct resource power_resources[] = { |
| 45 | DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW), |
| 46 | }; |
| 47 | |
| 48 | static struct resource rtc_resources[] = { |
| 49 | DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC), |
| 50 | }; |
| 51 | |
| 52 | static struct resource thermal_resources[] = { |
| 53 | DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1), |
| 54 | DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2), |
| 55 | }; |
| 56 | |
| 57 | static const struct regmap_irq max77620_top_irqs[] = { |
| 58 | REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK), |
| 59 | REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK), |
| 60 | REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK), |
| 61 | REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK), |
| 62 | REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK), |
| 63 | REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK), |
| 64 | REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK), |
| 65 | REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK), |
| 66 | REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK), |
| 67 | REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK), |
| 68 | }; |
| 69 | |
| 70 | static const struct mfd_cell max77620_children[] = { |
| 71 | { .name = "max77620-pinctrl", }, |
| 72 | { .name = "max77620-clock", }, |
| 73 | { .name = "max77620-pmic", }, |
| 74 | { .name = "max77620-watchdog", }, |
| 75 | { |
| 76 | .name = "max77620-gpio", |
| 77 | .resources = gpio_resources, |
| 78 | .num_resources = ARRAY_SIZE(gpio_resources), |
| 79 | }, { |
| 80 | .name = "max77620-rtc", |
| 81 | .resources = rtc_resources, |
| 82 | .num_resources = ARRAY_SIZE(rtc_resources), |
| 83 | }, { |
| 84 | .name = "max77620-power", |
| 85 | .resources = power_resources, |
| 86 | .num_resources = ARRAY_SIZE(power_resources), |
| 87 | }, { |
| 88 | .name = "max77620-thermal", |
| 89 | .resources = thermal_resources, |
| 90 | .num_resources = ARRAY_SIZE(thermal_resources), |
| 91 | }, |
| 92 | }; |
| 93 | |
| 94 | static const struct mfd_cell max20024_children[] = { |
| 95 | { .name = "max20024-pinctrl", }, |
| 96 | { .name = "max77620-clock", }, |
| 97 | { .name = "max20024-pmic", }, |
| 98 | { .name = "max77620-watchdog", }, |
| 99 | { |
| 100 | .name = "max77620-gpio", |
| 101 | .resources = gpio_resources, |
| 102 | .num_resources = ARRAY_SIZE(gpio_resources), |
| 103 | }, { |
| 104 | .name = "max77620-rtc", |
| 105 | .resources = rtc_resources, |
| 106 | .num_resources = ARRAY_SIZE(rtc_resources), |
| 107 | }, { |
| 108 | .name = "max20024-power", |
| 109 | .resources = power_resources, |
| 110 | .num_resources = ARRAY_SIZE(power_resources), |
| 111 | }, |
| 112 | }; |
| 113 | |
| 114 | static struct regmap_irq_chip max77620_top_irq_chip = { |
| 115 | .name = "max77620-top", |
| 116 | .irqs = max77620_top_irqs, |
| 117 | .num_irqs = ARRAY_SIZE(max77620_top_irqs), |
| 118 | .num_regs = 2, |
| 119 | .status_base = MAX77620_REG_IRQTOP, |
| 120 | .mask_base = MAX77620_REG_IRQTOPM, |
| 121 | }; |
| 122 | |
| 123 | static const struct regmap_range max77620_readable_ranges[] = { |
| 124 | regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), |
| 125 | }; |
| 126 | |
| 127 | static const struct regmap_access_table max77620_readable_table = { |
| 128 | .yes_ranges = max77620_readable_ranges, |
| 129 | .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges), |
| 130 | }; |
| 131 | |
| 132 | static const struct regmap_range max20024_readable_ranges[] = { |
| 133 | regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), |
| 134 | regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD), |
| 135 | }; |
| 136 | |
| 137 | static const struct regmap_access_table max20024_readable_table = { |
| 138 | .yes_ranges = max20024_readable_ranges, |
| 139 | .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges), |
| 140 | }; |
| 141 | |
| 142 | static const struct regmap_range max77620_writable_ranges[] = { |
| 143 | regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4), |
| 144 | }; |
| 145 | |
| 146 | static const struct regmap_access_table max77620_writable_table = { |
| 147 | .yes_ranges = max77620_writable_ranges, |
| 148 | .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges), |
| 149 | }; |
| 150 | |
| 151 | static const struct regmap_range max77620_cacheable_ranges[] = { |
| 152 | regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3), |
| 153 | regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3), |
| 154 | }; |
| 155 | |
| 156 | static const struct regmap_access_table max77620_volatile_table = { |
| 157 | .no_ranges = max77620_cacheable_ranges, |
| 158 | .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges), |
| 159 | }; |
| 160 | |
| 161 | static const struct regmap_config max77620_regmap_config = { |
| 162 | .name = "power-slave", |
| 163 | .reg_bits = 8, |
| 164 | .val_bits = 8, |
| 165 | .max_register = MAX77620_REG_DVSSD4 + 1, |
| 166 | .cache_type = REGCACHE_RBTREE, |
| 167 | .rd_table = &max77620_readable_table, |
| 168 | .wr_table = &max77620_writable_table, |
| 169 | .volatile_table = &max77620_volatile_table, |
| 170 | }; |
| 171 | |
| 172 | static const struct regmap_config max20024_regmap_config = { |
| 173 | .name = "power-slave", |
| 174 | .reg_bits = 8, |
| 175 | .val_bits = 8, |
| 176 | .max_register = MAX20024_REG_MAX_ADD + 1, |
| 177 | .cache_type = REGCACHE_RBTREE, |
| 178 | .rd_table = &max20024_readable_table, |
| 179 | .wr_table = &max77620_writable_table, |
| 180 | .volatile_table = &max77620_volatile_table, |
| 181 | }; |
| 182 | |
| 183 | /* max77620_get_fps_period_reg_value: Get FPS bit field value from |
| 184 | * requested periods. |
| 185 | * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560 |
| 186 | * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80, |
| 187 | * 160, 320, 540, 1280 and 2560 microseconds. |
| 188 | * The FPS register has 3 bits field to set the FPS period as |
| 189 | * bits max77620 max20024 |
| 190 | * 000 40 20 |
| 191 | * 001 80 40 |
| 192 | * ::: |
| 193 | */ |
| 194 | static int max77620_get_fps_period_reg_value(struct max77620_chip *chip, |
| 195 | int tperiod) |
| 196 | { |
| 197 | int fps_min_period; |
| 198 | int i; |
| 199 | |
| 200 | switch (chip->chip_id) { |
| 201 | case MAX20024: |
| 202 | fps_min_period = MAX20024_FPS_PERIOD_MIN_US; |
| 203 | break; |
| 204 | case MAX77620: |
| 205 | fps_min_period = MAX77620_FPS_PERIOD_MIN_US; |
Rhyland Klein | 82d8eb4 | 2016-05-12 13:45:04 -0400 | [diff] [blame] | 206 | break; |
Laxman Dewangan | 327156c | 2016-04-28 15:28:56 +0530 | [diff] [blame] | 207 | default: |
| 208 | return -EINVAL; |
| 209 | } |
| 210 | |
| 211 | for (i = 0; i < 7; i++) { |
| 212 | if (fps_min_period >= tperiod) |
| 213 | return i; |
| 214 | fps_min_period *= 2; |
| 215 | } |
| 216 | |
| 217 | return i; |
| 218 | } |
| 219 | |
| 220 | /* max77620_config_fps: Configure FPS configuration registers |
| 221 | * based on platform specific information. |
| 222 | */ |
| 223 | static int max77620_config_fps(struct max77620_chip *chip, |
| 224 | struct device_node *fps_np) |
| 225 | { |
| 226 | struct device *dev = chip->dev; |
| 227 | unsigned int mask = 0, config = 0; |
| 228 | u32 fps_max_period; |
| 229 | u32 param_val; |
| 230 | int tperiod, fps_id; |
| 231 | int ret; |
| 232 | char fps_name[10]; |
| 233 | |
| 234 | switch (chip->chip_id) { |
| 235 | case MAX20024: |
| 236 | fps_max_period = MAX20024_FPS_PERIOD_MAX_US; |
| 237 | break; |
| 238 | case MAX77620: |
| 239 | fps_max_period = MAX77620_FPS_PERIOD_MAX_US; |
Rhyland Klein | 82d8eb4 | 2016-05-12 13:45:04 -0400 | [diff] [blame] | 240 | break; |
Laxman Dewangan | 327156c | 2016-04-28 15:28:56 +0530 | [diff] [blame] | 241 | default: |
| 242 | return -EINVAL; |
| 243 | } |
| 244 | |
| 245 | for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) { |
| 246 | sprintf(fps_name, "fps%d", fps_id); |
| 247 | if (!strcmp(fps_np->name, fps_name)) |
| 248 | break; |
| 249 | } |
| 250 | |
| 251 | if (fps_id == MAX77620_FPS_COUNT) { |
| 252 | dev_err(dev, "FPS node name %s is not valid\n", fps_np->name); |
| 253 | return -EINVAL; |
| 254 | } |
| 255 | |
| 256 | ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us", |
| 257 | ¶m_val); |
| 258 | if (!ret) { |
| 259 | mask |= MAX77620_FPS_TIME_PERIOD_MASK; |
| 260 | chip->shutdown_fps_period[fps_id] = min(param_val, |
| 261 | fps_max_period); |
| 262 | tperiod = max77620_get_fps_period_reg_value(chip, |
| 263 | chip->shutdown_fps_period[fps_id]); |
| 264 | config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT; |
| 265 | } |
| 266 | |
| 267 | ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us", |
| 268 | ¶m_val); |
| 269 | if (!ret) |
| 270 | chip->suspend_fps_period[fps_id] = min(param_val, |
| 271 | fps_max_period); |
| 272 | |
| 273 | ret = of_property_read_u32(fps_np, "maxim,fps-event-source", |
| 274 | ¶m_val); |
| 275 | if (!ret) { |
| 276 | if (param_val > 2) { |
| 277 | dev_err(dev, "FPS%d event-source invalid\n", fps_id); |
| 278 | return -EINVAL; |
| 279 | } |
| 280 | mask |= MAX77620_FPS_EN_SRC_MASK; |
| 281 | config |= param_val << MAX77620_FPS_EN_SRC_SHIFT; |
| 282 | if (param_val == 2) { |
| 283 | mask |= MAX77620_FPS_ENFPS_SW_MASK; |
| 284 | config |= MAX77620_FPS_ENFPS_SW; |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | if (!chip->sleep_enable && !chip->enable_global_lpm) { |
| 289 | ret = of_property_read_u32(fps_np, |
| 290 | "maxim,device-state-on-disabled-event", |
| 291 | ¶m_val); |
| 292 | if (!ret) { |
| 293 | if (param_val == 0) |
| 294 | chip->sleep_enable = true; |
| 295 | else if (param_val == 1) |
| 296 | chip->enable_global_lpm = true; |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id, |
| 301 | mask, config); |
| 302 | if (ret < 0) { |
| 303 | dev_err(dev, "Failed to update FPS CFG: %d\n", ret); |
| 304 | return ret; |
| 305 | } |
| 306 | |
| 307 | return 0; |
| 308 | } |
| 309 | |
| 310 | static int max77620_initialise_fps(struct max77620_chip *chip) |
| 311 | { |
| 312 | struct device *dev = chip->dev; |
| 313 | struct device_node *fps_np, *fps_child; |
| 314 | u8 config; |
| 315 | int fps_id; |
| 316 | int ret; |
| 317 | |
| 318 | for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) { |
| 319 | chip->shutdown_fps_period[fps_id] = -1; |
| 320 | chip->suspend_fps_period[fps_id] = -1; |
| 321 | } |
| 322 | |
| 323 | fps_np = of_get_child_by_name(dev->of_node, "fps"); |
| 324 | if (!fps_np) |
| 325 | goto skip_fps; |
| 326 | |
| 327 | for_each_child_of_node(fps_np, fps_child) { |
| 328 | ret = max77620_config_fps(chip, fps_child); |
| 329 | if (ret < 0) |
| 330 | return ret; |
| 331 | } |
| 332 | |
| 333 | config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0; |
| 334 | ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, |
| 335 | MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config); |
| 336 | if (ret < 0) { |
| 337 | dev_err(dev, "Failed to update SLP_LPM: %d\n", ret); |
| 338 | return ret; |
| 339 | } |
| 340 | |
| 341 | skip_fps: |
| 342 | /* Enable wake on EN0 pin */ |
| 343 | ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, |
| 344 | MAX77620_ONOFFCNFG2_WK_EN0, |
| 345 | MAX77620_ONOFFCNFG2_WK_EN0); |
| 346 | if (ret < 0) { |
| 347 | dev_err(dev, "Failed to update WK_EN0: %d\n", ret); |
| 348 | return ret; |
| 349 | } |
| 350 | |
| 351 | /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */ |
| 352 | if ((chip->chip_id == MAX20024) && chip->sleep_enable) { |
| 353 | config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE; |
| 354 | ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, |
| 355 | config, config); |
| 356 | if (ret < 0) { |
| 357 | dev_err(dev, "Failed to update SLPEN: %d\n", ret); |
| 358 | return ret; |
| 359 | } |
| 360 | } |
| 361 | |
| 362 | return 0; |
| 363 | } |
| 364 | |
| 365 | static int max77620_read_es_version(struct max77620_chip *chip) |
| 366 | { |
| 367 | unsigned int val; |
| 368 | u8 cid_val[6]; |
| 369 | int i; |
| 370 | int ret; |
| 371 | |
| 372 | for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) { |
| 373 | ret = regmap_read(chip->rmap, i, &val); |
| 374 | if (ret < 0) { |
| 375 | dev_err(chip->dev, "Failed to read CID: %d\n", ret); |
| 376 | return ret; |
| 377 | } |
| 378 | dev_dbg(chip->dev, "CID%d: 0x%02x\n", |
| 379 | i - MAX77620_REG_CID0, val); |
| 380 | cid_val[i - MAX77620_REG_CID0] = val; |
| 381 | } |
| 382 | |
| 383 | /* CID4 is OTP Version and CID5 is ES version */ |
| 384 | dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n", |
| 385 | cid_val[4], MAX77620_CID5_DIDM(cid_val[5])); |
| 386 | |
| 387 | return ret; |
| 388 | } |
| 389 | |
| 390 | static int max77620_probe(struct i2c_client *client, |
| 391 | const struct i2c_device_id *id) |
| 392 | { |
| 393 | const struct regmap_config *rmap_config; |
| 394 | struct max77620_chip *chip; |
| 395 | const struct mfd_cell *mfd_cells; |
| 396 | int n_mfd_cells; |
| 397 | int ret; |
| 398 | |
| 399 | chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); |
| 400 | if (!chip) |
| 401 | return -ENOMEM; |
| 402 | |
| 403 | i2c_set_clientdata(client, chip); |
| 404 | chip->dev = &client->dev; |
| 405 | chip->irq_base = -1; |
| 406 | chip->chip_irq = client->irq; |
| 407 | chip->chip_id = (enum max77620_chip_id)id->driver_data; |
| 408 | |
| 409 | switch (chip->chip_id) { |
| 410 | case MAX77620: |
| 411 | mfd_cells = max77620_children; |
| 412 | n_mfd_cells = ARRAY_SIZE(max77620_children); |
| 413 | rmap_config = &max77620_regmap_config; |
| 414 | break; |
| 415 | case MAX20024: |
| 416 | mfd_cells = max20024_children; |
| 417 | n_mfd_cells = ARRAY_SIZE(max20024_children); |
| 418 | rmap_config = &max20024_regmap_config; |
| 419 | break; |
| 420 | default: |
| 421 | dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id); |
| 422 | return -EINVAL; |
| 423 | } |
| 424 | |
| 425 | chip->rmap = devm_regmap_init_i2c(client, rmap_config); |
| 426 | if (IS_ERR(chip->rmap)) { |
| 427 | ret = PTR_ERR(chip->rmap); |
| 428 | dev_err(chip->dev, "Failed to intialise regmap: %d\n", ret); |
| 429 | return ret; |
| 430 | } |
| 431 | |
| 432 | ret = max77620_read_es_version(chip); |
| 433 | if (ret < 0) |
| 434 | return ret; |
| 435 | |
| 436 | ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq, |
| 437 | IRQF_ONESHOT | IRQF_SHARED, |
| 438 | chip->irq_base, &max77620_top_irq_chip, |
| 439 | &chip->top_irq_data); |
| 440 | if (ret < 0) { |
| 441 | dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret); |
| 442 | return ret; |
| 443 | } |
| 444 | |
| 445 | ret = max77620_initialise_fps(chip); |
| 446 | if (ret < 0) |
| 447 | return ret; |
| 448 | |
| 449 | ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, |
| 450 | mfd_cells, n_mfd_cells, NULL, 0, |
| 451 | regmap_irq_get_domain(chip->top_irq_data)); |
| 452 | if (ret < 0) { |
| 453 | dev_err(chip->dev, "Failed to add MFD children: %d\n", ret); |
| 454 | return ret; |
| 455 | } |
| 456 | |
| 457 | return 0; |
| 458 | } |
| 459 | |
| 460 | #ifdef CONFIG_PM_SLEEP |
| 461 | static int max77620_set_fps_period(struct max77620_chip *chip, |
| 462 | int fps_id, int time_period) |
| 463 | { |
| 464 | int period = max77620_get_fps_period_reg_value(chip, time_period); |
| 465 | int ret; |
| 466 | |
| 467 | ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id, |
| 468 | MAX77620_FPS_TIME_PERIOD_MASK, |
| 469 | period << MAX77620_FPS_TIME_PERIOD_SHIFT); |
| 470 | if (ret < 0) { |
| 471 | dev_err(chip->dev, "Failed to update FPS period: %d\n", ret); |
| 472 | return ret; |
| 473 | } |
| 474 | |
| 475 | return 0; |
| 476 | } |
| 477 | |
| 478 | static int max77620_i2c_suspend(struct device *dev) |
| 479 | { |
| 480 | struct max77620_chip *chip = dev_get_drvdata(dev); |
| 481 | struct i2c_client *client = to_i2c_client(dev); |
| 482 | unsigned int config; |
| 483 | int fps; |
| 484 | int ret; |
| 485 | |
| 486 | for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) { |
| 487 | if (chip->suspend_fps_period[fps] < 0) |
| 488 | continue; |
| 489 | |
| 490 | ret = max77620_set_fps_period(chip, fps, |
| 491 | chip->suspend_fps_period[fps]); |
| 492 | if (ret < 0) |
| 493 | return ret; |
| 494 | } |
| 495 | |
| 496 | /* |
| 497 | * For MAX20024: No need to configure SLPEN on suspend as |
| 498 | * it will be configured on Init. |
| 499 | */ |
| 500 | if (chip->chip_id == MAX20024) |
| 501 | goto out; |
| 502 | |
| 503 | config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0; |
| 504 | ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1, |
| 505 | MAX77620_ONOFFCNFG1_SLPEN, |
| 506 | config); |
| 507 | if (ret < 0) { |
| 508 | dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret); |
| 509 | return ret; |
| 510 | } |
| 511 | |
| 512 | /* Disable WK_EN0 */ |
| 513 | ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, |
| 514 | MAX77620_ONOFFCNFG2_WK_EN0, 0); |
| 515 | if (ret < 0) { |
| 516 | dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret); |
| 517 | return ret; |
| 518 | } |
| 519 | |
| 520 | out: |
| 521 | disable_irq(client->irq); |
| 522 | |
| 523 | return 0; |
| 524 | } |
| 525 | |
| 526 | static int max77620_i2c_resume(struct device *dev) |
| 527 | { |
| 528 | struct max77620_chip *chip = dev_get_drvdata(dev); |
| 529 | struct i2c_client *client = to_i2c_client(dev); |
| 530 | int ret; |
| 531 | int fps; |
| 532 | |
| 533 | for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) { |
| 534 | if (chip->shutdown_fps_period[fps] < 0) |
| 535 | continue; |
| 536 | |
| 537 | ret = max77620_set_fps_period(chip, fps, |
| 538 | chip->shutdown_fps_period[fps]); |
| 539 | if (ret < 0) |
| 540 | return ret; |
| 541 | } |
| 542 | |
| 543 | /* |
| 544 | * For MAX20024: No need to configure WKEN0 on resume as |
| 545 | * it is configured on Init. |
| 546 | */ |
| 547 | if (chip->chip_id == MAX20024) |
| 548 | goto out; |
| 549 | |
| 550 | /* Enable WK_EN0 */ |
| 551 | ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, |
| 552 | MAX77620_ONOFFCNFG2_WK_EN0, |
| 553 | MAX77620_ONOFFCNFG2_WK_EN0); |
| 554 | if (ret < 0) { |
| 555 | dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret); |
| 556 | return ret; |
| 557 | } |
| 558 | |
| 559 | out: |
| 560 | enable_irq(client->irq); |
| 561 | |
| 562 | return 0; |
| 563 | } |
| 564 | #endif |
| 565 | |
| 566 | static const struct i2c_device_id max77620_id[] = { |
| 567 | {"max77620", MAX77620}, |
| 568 | {"max20024", MAX20024}, |
| 569 | {}, |
| 570 | }; |
| 571 | MODULE_DEVICE_TABLE(i2c, max77620_id); |
| 572 | |
| 573 | static const struct dev_pm_ops max77620_pm_ops = { |
| 574 | SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume) |
| 575 | }; |
| 576 | |
| 577 | static struct i2c_driver max77620_driver = { |
| 578 | .driver = { |
| 579 | .name = "max77620", |
| 580 | .pm = &max77620_pm_ops, |
| 581 | }, |
| 582 | .probe = max77620_probe, |
| 583 | .id_table = max77620_id, |
| 584 | }; |
| 585 | |
| 586 | module_i2c_driver(max77620_driver); |
| 587 | |
| 588 | MODULE_DESCRIPTION("MAX77620/MAX20024 Multi Function Device Core Driver"); |
| 589 | MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); |
| 590 | MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>"); |
| 591 | MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>"); |
| 592 | MODULE_LICENSE("GPL v2"); |