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Heiko Stuebner6bcf60f2013-10-14 17:34:02 +02001/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/pinctrl/rockchip.h>
Heiko Stuebnerb13d2a72014-04-15 01:16:44 +020018#include <dt-bindings/clock/rk3188-cru.h>
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +020019#include "rk3xxx.dtsi"
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +020020
21/ {
22 compatible = "rockchip,rk3188";
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
Heiko Stübner26ab69c2014-03-27 01:06:32 +010027 enable-method = "rockchip,rk3066-smp";
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +020028
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
33 reg = <0x0>;
34 };
35 cpu@1 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
39 reg = <0x1>;
40 };
41 cpu@2 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
45 reg = <0x2>;
46 };
47 cpu@3 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
51 reg = <0x3>;
52 };
53 };
54
Heiko Stuebnerc3030d32014-07-26 18:44:35 +020055 sram: sram@10080000 {
56 compatible = "mmio-sram";
57 reg = <0x10080000 0x8000>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges = <0 0x10080000 0x8000>;
61
62 smp-sram@0 {
63 compatible = "rockchip,rk3066-smp-sram";
64 reg = <0x0 0x50>;
65 };
66 };
67
68 cru: clock-controller@20000000 {
69 compatible = "rockchip,rk3188-cru";
70 reg = <0x20000000 0x1000>;
71 rockchip,grf = <&grf>;
72
73 #clock-cells = <1>;
74 #reset-cells = <1>;
75 };
76
Heiko Stuebner6e4b3b42014-07-22 22:56:16 +020077 pinctrl: pinctrl {
Heiko Stuebnerc3030d32014-07-26 18:44:35 +020078 compatible = "rockchip,rk3188-pinctrl";
79 rockchip,grf = <&grf>;
80 rockchip,pmu = <&pmu>;
81
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
85
86 gpio0: gpio0@0x2000a000 {
87 compatible = "rockchip,rk3188-gpio-bank0";
88 reg = <0x2000a000 0x100>;
89 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&cru PCLK_GPIO0>;
91
92 gpio-controller;
93 #gpio-cells = <2>;
94
95 interrupt-controller;
96 #interrupt-cells = <2>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +020097 };
98
Heiko Stuebnerc3030d32014-07-26 18:44:35 +020099 gpio1: gpio1@0x2003c000 {
100 compatible = "rockchip,gpio-bank";
101 reg = <0x2003c000 0x100>;
102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&cru PCLK_GPIO1>;
104
105 gpio-controller;
106 #gpio-cells = <2>;
107
108 interrupt-controller;
109 #interrupt-cells = <2>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200110 };
111
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200112 gpio2: gpio2@2003e000 {
113 compatible = "rockchip,gpio-bank";
114 reg = <0x2003e000 0x100>;
115 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&cru PCLK_GPIO2>;
Heiko Stuebnerde18e012013-06-17 22:08:31 +0200117
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200118 gpio-controller;
119 #gpio-cells = <2>;
120
121 interrupt-controller;
122 #interrupt-cells = <2>;
123 };
124
125 gpio3: gpio3@20080000 {
126 compatible = "rockchip,gpio-bank";
127 reg = <0x20080000 0x100>;
128 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&cru PCLK_GPIO3>;
130
131 gpio-controller;
132 #gpio-cells = <2>;
133
134 interrupt-controller;
135 #interrupt-cells = <2>;
136 };
137
138 pcfg_pull_up: pcfg_pull_up {
139 bias-pull-up;
140 };
141
142 pcfg_pull_down: pcfg_pull_down {
143 bias-pull-down;
144 };
145
146 pcfg_pull_none: pcfg_pull_none {
147 bias-disable;
148 };
149
Heiko Stuebner4ff4ae12014-09-10 17:04:36 +0200150 emmc {
151 emmc_clk: emmc-clk {
Heiko Stuebnerbee1cef2014-09-16 18:59:36 +0200152 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
Heiko Stuebner4ff4ae12014-09-10 17:04:36 +0200153 };
154
155 emmc_cmd: emmc-cmd {
Heiko Stuebnerbee1cef2014-09-16 18:59:36 +0200156 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
Heiko Stuebner4ff4ae12014-09-10 17:04:36 +0200157 };
158
159 emmc_rst: emmc-rst {
Heiko Stuebnerbee1cef2014-09-16 18:59:36 +0200160 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
Heiko Stuebner4ff4ae12014-09-10 17:04:36 +0200161 };
162
163 /*
164 * The data pins are shared between nandc and emmc and
165 * not accessible through pinctrl. Also they should've
166 * been already set correctly by firmware, as
167 * flash/emmc is the boot-device.
168 */
169 };
170
Heiko Stuebner9cdffd82014-06-24 20:12:06 +0200171 i2c0 {
172 i2c0_xfer: i2c0-xfer {
173 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
174 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
175 };
176 };
177
178 i2c1 {
179 i2c1_xfer: i2c1-xfer {
180 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
181 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
182 };
183 };
184
185 i2c2 {
186 i2c2_xfer: i2c2-xfer {
187 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
188 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
189 };
190 };
191
192 i2c3 {
193 i2c3_xfer: i2c3-xfer {
194 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
195 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
196 };
197 };
198
199 i2c4 {
200 i2c4_xfer: i2c4-xfer {
201 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
202 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
203 };
204 };
205
Beniamino Galvani550c7f42014-06-26 20:03:41 +0200206 pwm0 {
207 pwm0_out: pwm0-out {
208 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
209 };
210 };
211
212 pwm1 {
213 pwm1_out: pwm1-out {
214 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
215 };
216 };
217
218 pwm2 {
219 pwm2_out: pwm2-out {
220 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
221 };
222 };
223
224 pwm3 {
225 pwm3_out: pwm3-out {
226 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
227 };
228 };
229
Heiko Stuebner39c2bd72014-09-10 16:28:02 +0200230 spi0 {
231 spi0_clk: spi0-clk {
232 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
233 };
234 spi0_cs0: spi0-cs0 {
235 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
236 };
237 spi0_tx: spi0-tx {
238 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
239 };
240 spi0_rx: spi0-rx {
241 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
242 };
243 spi0_cs1: spi0-cs1 {
244 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
245 };
246 };
247
248 spi1 {
249 spi1_clk: spi1-clk {
250 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
251 };
252 spi1_cs0: spi1-cs0 {
253 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
254 };
255 spi1_rx: spi1-rx {
256 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
257 };
258 spi1_tx: spi1-tx {
259 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
260 };
261 spi1_cs1: spi1-cs1 {
262 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
263 };
264 };
265
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200266 uart0 {
267 uart0_xfer: uart0-xfer {
268 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
269 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
270 };
271
272 uart0_cts: uart0-cts {
273 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
274 };
275
276 uart0_rts: uart0-rts {
277 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebnerde18e012013-06-17 22:08:31 +0200278 };
279 };
280
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200281 uart1 {
282 uart1_xfer: uart1-xfer {
283 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
284 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
285 };
Heiko Stuebnerb13d2a72014-04-15 01:16:44 +0200286
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200287 uart1_cts: uart1-cts {
288 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
289 };
290
291 uart1_rts: uart1-rts {
292 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
293 };
Heiko Stuebnerb13d2a72014-04-15 01:16:44 +0200294 };
295
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200296 uart2 {
297 uart2_xfer: uart2-xfer {
298 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
299 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
300 };
301 /* no rts / cts for uart2 */
302 };
Heiko Stuebner56f2b892014-04-29 22:02:52 +0200303
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200304 uart3 {
305 uart3_xfer: uart3-xfer {
306 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
307 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200308 };
309
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200310 uart3_cts: uart3-cts {
311 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200312 };
313
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200314 uart3_rts: uart3-rts {
315 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
316 };
317 };
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200318
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200319 sd0 {
320 sd0_clk: sd0-clk {
321 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200322 };
323
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200324 sd0_cmd: sd0-cmd {
325 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200326 };
327
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200328 sd0_cd: sd0-cd {
329 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200330 };
331
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200332 sd0_wp: sd0-wp {
333 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200334 };
335
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200336 sd0_pwr: sd0-pwr {
337 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200338 };
339
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200340 sd0_bus1: sd0-bus-width1 {
341 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200342 };
343
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200344 sd0_bus4: sd0-bus-width4 {
345 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
346 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
347 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
348 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
349 };
350 };
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200351
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200352 sd1 {
353 sd1_clk: sd1-clk {
354 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200355 };
356
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200357 sd1_cmd: sd1-cmd {
358 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200359 };
360
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200361 sd1_cd: sd1-cd {
362 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200363 };
364
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200365 sd1_wp: sd1-wp {
366 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200367 };
368
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200369 sd1_bus1: sd1-bus-width1 {
370 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
371 };
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200372
Heiko Stuebnerc3030d32014-07-26 18:44:35 +0200373 sd1_bus4: sd1-bus-width4 {
374 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
375 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
376 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
377 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
Heiko Stuebner6bcf60f2013-10-14 17:34:02 +0200378 };
379 };
380 };
381};
Heiko Stuebnerfcbbf962014-07-26 23:08:06 +0200382
383&global_timer {
384 interrupts = <GIC_PPI 11 0xf04>;
385};
386
387&local_timer {
388 interrupts = <GIC_PPI 13 0xf04>;
389};
390
Heiko Stuebner9cdffd82014-06-24 20:12:06 +0200391&i2c0 {
392 compatible = "rockchip,rk3188-i2c";
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c0_xfer>;
395};
396
397&i2c1 {
398 compatible = "rockchip,rk3188-i2c";
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2c1_xfer>;
401};
402
403&i2c2 {
404 compatible = "rockchip,rk3188-i2c";
405 pinctrl-names = "default";
406 pinctrl-0 = <&i2c2_xfer>;
407};
408
409&i2c3 {
410 compatible = "rockchip,rk3188-i2c";
411 pinctrl-names = "default";
412 pinctrl-0 = <&i2c3_xfer>;
413};
414
415&i2c4 {
416 compatible = "rockchip,rk3188-i2c";
417 pinctrl-names = "default";
418 pinctrl-0 = <&i2c4_xfer>;
419};
420
Beniamino Galvani550c7f42014-06-26 20:03:41 +0200421&pwm0 {
422 pinctrl-names = "default";
423 pinctrl-0 = <&pwm0_out>;
424};
425
426&pwm1 {
427 pinctrl-names = "default";
428 pinctrl-0 = <&pwm1_out>;
429};
430
431&pwm2 {
432 pinctrl-names = "default";
433 pinctrl-0 = <&pwm2_out>;
434};
435
436&pwm3 {
437 pinctrl-names = "default";
438 pinctrl-0 = <&pwm3_out>;
439};
440
Heiko Stuebner39c2bd72014-09-10 16:28:02 +0200441&spi0 {
442 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
443 pinctrl-names = "default";
444 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
445};
446
447&spi1 {
448 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
449 pinctrl-names = "default";
450 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
451};
452
Heiko Stuebnerfcbbf962014-07-26 23:08:06 +0200453&uart0 {
454 pinctrl-names = "default";
455 pinctrl-0 = <&uart0_xfer>;
456};
457
458&uart1 {
459 pinctrl-names = "default";
460 pinctrl-0 = <&uart1_xfer>;
461};
462
463&uart2 {
464 pinctrl-names = "default";
465 pinctrl-0 = <&uart2_xfer>;
466};
467
468&uart3 {
469 pinctrl-names = "default";
470 pinctrl-0 = <&uart3_xfer>;
471};
Heiko Stuebnereb2b9d42014-07-30 10:16:17 +0200472
473&wdt {
474 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
475};