blob: e7e83835f7255e6bbbb46c019236729994d05d5c [file] [log] [blame]
Michael Bueschef1a6282008-08-27 18:53:02 +02001/*
2
3 Broadcom B43 wireless driver
4 Common PHY routines
5
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
Michael Büscheb032b92011-07-04 20:50:05 +02008 Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
Michael Bueschef1a6282008-08-27 18:53:02 +02009 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
26
27*/
28
29#include "phy_common.h"
30#include "phy_g.h"
31#include "phy_a.h"
Michael Buesch3d0da752008-08-30 02:27:19 +020032#include "phy_n.h"
Michael Buesche63e4362008-08-30 10:55:48 +020033#include "phy_lp.h"
Rafał Miłeckid7520b12011-06-13 16:20:06 +020034#include "phy_ht.h"
Rafał Miłecki58eb7ff2011-07-07 18:58:25 +020035#include "phy_lcn.h"
Michael Bueschef1a6282008-08-27 18:53:02 +020036#include "b43.h"
37#include "main.h"
38
39
Michael Bueschfb111372008-09-02 13:00:34 +020040int b43_phy_allocate(struct b43_wldev *dev)
Michael Bueschef1a6282008-08-27 18:53:02 +020041{
42 struct b43_phy *phy = &(dev->phy);
43 int err;
44
45 phy->ops = NULL;
46
47 switch (phy->type) {
48 case B43_PHYTYPE_A:
49 phy->ops = &b43_phyops_a;
50 break;
51 case B43_PHYTYPE_G:
52 phy->ops = &b43_phyops_g;
53 break;
54 case B43_PHYTYPE_N:
Rafał Miłecki692d2c02010-12-07 21:56:00 +010055#ifdef CONFIG_B43_PHY_N
Michael Bueschef1a6282008-08-27 18:53:02 +020056 phy->ops = &b43_phyops_n;
57#endif
58 break;
59 case B43_PHYTYPE_LP:
Michael Buesche63e4362008-08-30 10:55:48 +020060#ifdef CONFIG_B43_PHY_LP
61 phy->ops = &b43_phyops_lp;
62#endif
Michael Bueschef1a6282008-08-27 18:53:02 +020063 break;
Rafał Miłeckid7520b12011-06-13 16:20:06 +020064 case B43_PHYTYPE_HT:
65#ifdef CONFIG_B43_PHY_HT
66 phy->ops = &b43_phyops_ht;
67#endif
68 break;
Rafał Miłecki58eb7ff2011-07-07 18:58:25 +020069 case B43_PHYTYPE_LCN:
70#ifdef CONFIG_B43_PHY_LCN
71 phy->ops = &b43_phyops_lcn;
72#endif
73 break;
Michael Bueschef1a6282008-08-27 18:53:02 +020074 }
75 if (B43_WARN_ON(!phy->ops))
76 return -ENODEV;
77
78 err = phy->ops->allocate(dev);
79 if (err)
80 phy->ops = NULL;
81
82 return err;
83}
84
Michael Bueschfb111372008-09-02 13:00:34 +020085void b43_phy_free(struct b43_wldev *dev)
86{
87 dev->phy.ops->free(dev);
88 dev->phy.ops = NULL;
89}
90
Michael Bueschef1a6282008-08-27 18:53:02 +020091int b43_phy_init(struct b43_wldev *dev)
92{
93 struct b43_phy *phy = &dev->phy;
94 const struct b43_phy_operations *ops = phy->ops;
95 int err;
96
Rafał Miłeckiea42e712014-05-31 20:49:38 +020097 /* During PHY init we need to use some channel. On the first init this
98 * function is called *before* b43_op_config, so our pointer is NULL.
99 */
100 if (!phy->chandef) {
101 phy->chandef = &dev->wl->hw->conf.chandef;
102 phy->channel = phy->chandef->chan->hw_value;
103 }
Michael Bueschef1a6282008-08-27 18:53:02 +0200104
Rafał Miłecki7a8af8c2014-05-17 23:24:56 +0200105 phy->ops->switch_analog(dev, true);
Rafał Miłeckia6316e22014-04-22 13:54:36 +0200106 b43_software_rfkill(dev, false);
Rafał Miłecki09951ad2014-05-27 22:07:31 +0200107
Michael Bueschef1a6282008-08-27 18:53:02 +0200108 err = ops->init(dev);
109 if (err) {
110 b43err(dev->wl, "PHY init failed\n");
111 goto err_block_rf;
112 }
Rafał Miłecki09951ad2014-05-27 22:07:31 +0200113 phy->do_full_init = false;
114
Rafał Miłeckieb530b02014-05-31 20:49:36 +0200115 err = b43_switch_channel(dev, phy->channel);
Michael Bueschef1a6282008-08-27 18:53:02 +0200116 if (err) {
117 b43err(dev->wl, "PHY init: Channel switch to default failed\n");
118 goto err_phy_exit;
119 }
120
121 return 0;
122
123err_phy_exit:
Rafał Miłecki09951ad2014-05-27 22:07:31 +0200124 phy->do_full_init = true;
Michael Bueschef1a6282008-08-27 18:53:02 +0200125 if (ops->exit)
126 ops->exit(dev);
127err_block_rf:
Rafał Miłeckia6316e22014-04-22 13:54:36 +0200128 b43_software_rfkill(dev, true);
Michael Bueschef1a6282008-08-27 18:53:02 +0200129
130 return err;
131}
132
133void b43_phy_exit(struct b43_wldev *dev)
134{
135 const struct b43_phy_operations *ops = dev->phy.ops;
136
Rafał Miłeckia6316e22014-04-22 13:54:36 +0200137 b43_software_rfkill(dev, true);
Rafał Miłecki09951ad2014-05-27 22:07:31 +0200138 dev->phy.do_full_init = true;
Michael Bueschef1a6282008-08-27 18:53:02 +0200139 if (ops->exit)
140 ops->exit(dev);
141}
142
143bool b43_has_hardware_pctl(struct b43_wldev *dev)
144{
145 if (!dev->phy.hardware_power_control)
Zhao, Gang1a2b2502014-02-16 22:31:38 +0800146 return false;
Michael Bueschef1a6282008-08-27 18:53:02 +0200147 if (!dev->phy.ops->supports_hwpctl)
Zhao, Gang1a2b2502014-02-16 22:31:38 +0800148 return false;
Michael Bueschef1a6282008-08-27 18:53:02 +0200149 return dev->phy.ops->supports_hwpctl(dev);
150}
151
152void b43_radio_lock(struct b43_wldev *dev)
153{
154 u32 macctl;
155
Michael Buesch591f3dc2009-03-31 12:27:32 +0200156#if B43_DEBUG
157 B43_WARN_ON(dev->phy.radio_locked);
Rusty Russell3db1cd52011-12-19 13:56:45 +0000158 dev->phy.radio_locked = true;
Michael Buesch591f3dc2009-03-31 12:27:32 +0200159#endif
160
Michael Bueschef1a6282008-08-27 18:53:02 +0200161 macctl = b43_read32(dev, B43_MMIO_MACCTL);
Michael Bueschef1a6282008-08-27 18:53:02 +0200162 macctl |= B43_MACCTL_RADIOLOCK;
163 b43_write32(dev, B43_MMIO_MACCTL, macctl);
Michael Buesch591f3dc2009-03-31 12:27:32 +0200164 /* Commit the write and wait for the firmware
165 * to finish any radio register access. */
Michael Bueschef1a6282008-08-27 18:53:02 +0200166 b43_read32(dev, B43_MMIO_MACCTL);
167 udelay(10);
168}
169
170void b43_radio_unlock(struct b43_wldev *dev)
171{
172 u32 macctl;
173
Michael Buesch591f3dc2009-03-31 12:27:32 +0200174#if B43_DEBUG
175 B43_WARN_ON(!dev->phy.radio_locked);
Rusty Russell3db1cd52011-12-19 13:56:45 +0000176 dev->phy.radio_locked = false;
Michael Buesch591f3dc2009-03-31 12:27:32 +0200177#endif
178
Michael Bueschef1a6282008-08-27 18:53:02 +0200179 /* Commit any write */
180 b43_read16(dev, B43_MMIO_PHY_VER);
181 /* unlock */
182 macctl = b43_read32(dev, B43_MMIO_MACCTL);
Michael Bueschef1a6282008-08-27 18:53:02 +0200183 macctl &= ~B43_MACCTL_RADIOLOCK;
184 b43_write32(dev, B43_MMIO_MACCTL, macctl);
185}
186
187void b43_phy_lock(struct b43_wldev *dev)
188{
189#if B43_DEBUG
190 B43_WARN_ON(dev->phy.phy_locked);
Rusty Russell3db1cd52011-12-19 13:56:45 +0000191 dev->phy.phy_locked = true;
Michael Bueschef1a6282008-08-27 18:53:02 +0200192#endif
Rafał Miłecki21d889d2011-05-18 02:06:38 +0200193 B43_WARN_ON(dev->dev->core_rev < 3);
Michael Bueschef1a6282008-08-27 18:53:02 +0200194
Johannes Berg05c914f2008-09-11 00:01:58 +0200195 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
Michael Bueschef1a6282008-08-27 18:53:02 +0200196 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
197}
198
199void b43_phy_unlock(struct b43_wldev *dev)
200{
201#if B43_DEBUG
202 B43_WARN_ON(!dev->phy.phy_locked);
Rusty Russell3db1cd52011-12-19 13:56:45 +0000203 dev->phy.phy_locked = false;
Michael Bueschef1a6282008-08-27 18:53:02 +0200204#endif
Rafał Miłecki21d889d2011-05-18 02:06:38 +0200205 B43_WARN_ON(dev->dev->core_rev < 3);
Michael Bueschef1a6282008-08-27 18:53:02 +0200206
Johannes Berg05c914f2008-09-11 00:01:58 +0200207 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
Michael Bueschef1a6282008-08-27 18:53:02 +0200208 b43_power_saving_ctl_bits(dev, 0);
209}
210
Michael Bueschd10d0e52008-12-18 22:13:39 +0100211static inline void assert_mac_suspended(struct b43_wldev *dev)
212{
213 if (!B43_DEBUG)
214 return;
215 if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
216 (dev->mac_suspended <= 0)) {
217 b43dbg(dev->wl, "PHY/RADIO register access with "
218 "enabled MAC.\n");
219 dump_stack();
220 }
221}
222
Michael Bueschef1a6282008-08-27 18:53:02 +0200223u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
224{
Michael Bueschd10d0e52008-12-18 22:13:39 +0100225 assert_mac_suspended(dev);
Michael Bueschef1a6282008-08-27 18:53:02 +0200226 return dev->phy.ops->radio_read(dev, reg);
227}
228
229void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
230{
Michael Bueschd10d0e52008-12-18 22:13:39 +0100231 assert_mac_suspended(dev);
Michael Bueschef1a6282008-08-27 18:53:02 +0200232 dev->phy.ops->radio_write(dev, reg, value);
233}
234
235void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
236{
237 b43_radio_write16(dev, offset,
238 b43_radio_read16(dev, offset) & mask);
239}
240
241void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
242{
243 b43_radio_write16(dev, offset,
244 b43_radio_read16(dev, offset) | set);
245}
246
247void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
248{
249 b43_radio_write16(dev, offset,
250 (b43_radio_read16(dev, offset) & mask) | set);
251}
252
Rafał Miłecki0f941772012-07-26 00:07:37 +0200253bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
254 u16 value, int delay, int timeout)
255{
256 u16 val;
257 int i;
258
259 for (i = 0; i < timeout; i += delay) {
260 val = b43_radio_read(dev, offset);
261 if ((val & mask) == value)
262 return true;
263 udelay(delay);
264 }
265 return false;
266}
267
Michael Bueschef1a6282008-08-27 18:53:02 +0200268u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
269{
Michael Bueschd10d0e52008-12-18 22:13:39 +0100270 assert_mac_suspended(dev);
Rafał Miłecki15518082010-12-07 09:42:07 +0100271 dev->phy.writes_counter = 0;
Michael Bueschef1a6282008-08-27 18:53:02 +0200272 return dev->phy.ops->phy_read(dev, reg);
273}
274
275void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
276{
Michael Bueschd10d0e52008-12-18 22:13:39 +0100277 assert_mac_suspended(dev);
Michael Bueschef1a6282008-08-27 18:53:02 +0200278 dev->phy.ops->phy_write(dev, reg, value);
Rafał Miłecki15518082010-12-07 09:42:07 +0100279 if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) {
280 b43_read16(dev, B43_MMIO_PHY_VER);
281 dev->phy.writes_counter = 0;
282 }
Michael Bueschef1a6282008-08-27 18:53:02 +0200283}
284
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200285void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
286{
287 assert_mac_suspended(dev);
288 dev->phy.ops->phy_write(dev, destreg,
289 dev->phy.ops->phy_read(dev, srcreg));
290}
291
Michael Bueschef1a6282008-08-27 18:53:02 +0200292void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
293{
Gábor Stefanik68ec5322009-08-26 20:51:25 +0200294 if (dev->phy.ops->phy_maskset) {
295 assert_mac_suspended(dev);
296 dev->phy.ops->phy_maskset(dev, offset, mask, 0);
297 } else {
298 b43_phy_write(dev, offset,
299 b43_phy_read(dev, offset) & mask);
300 }
Michael Bueschef1a6282008-08-27 18:53:02 +0200301}
302
303void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
304{
Gábor Stefanik68ec5322009-08-26 20:51:25 +0200305 if (dev->phy.ops->phy_maskset) {
306 assert_mac_suspended(dev);
307 dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
308 } else {
309 b43_phy_write(dev, offset,
310 b43_phy_read(dev, offset) | set);
311 }
Michael Bueschef1a6282008-08-27 18:53:02 +0200312}
313
314void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
315{
Gábor Stefanik68ec5322009-08-26 20:51:25 +0200316 if (dev->phy.ops->phy_maskset) {
317 assert_mac_suspended(dev);
318 dev->phy.ops->phy_maskset(dev, offset, mask, set);
319 } else {
320 b43_phy_write(dev, offset,
321 (b43_phy_read(dev, offset) & mask) | set);
322 }
Michael Bueschef1a6282008-08-27 18:53:02 +0200323}
324
Rafał Miłeckib60c3c22014-05-17 23:24:54 +0200325void b43_phy_put_into_reset(struct b43_wldev *dev)
326{
Rafał Miłeckib60c3c22014-05-17 23:24:54 +0200327 u32 tmp;
Rafał Miłeckib60c3c22014-05-17 23:24:54 +0200328
329 switch (dev->dev->bus_type) {
330#ifdef CONFIG_B43_BCMA
331 case B43_BUS_BCMA:
Rafał Miłecki50c1b592014-05-17 23:24:55 +0200332 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
333 tmp &= ~B43_BCMA_IOCTL_GMODE;
334 tmp |= B43_BCMA_IOCTL_PHY_RESET;
335 tmp |= BCMA_IOCTL_FGC;
336 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
337 udelay(1);
338
339 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
340 tmp &= ~BCMA_IOCTL_FGC;
341 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
342 udelay(1);
Rafał Miłeckib60c3c22014-05-17 23:24:54 +0200343 break;
344#endif
345#ifdef CONFIG_B43_SSB
346 case B43_BUS_SSB:
347 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
348 tmp &= ~B43_TMSLOW_GMODE;
349 tmp |= B43_TMSLOW_PHYRESET;
350 tmp |= SSB_TMSLOW_FGC;
351 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
Rafał Miłecki50c1b592014-05-17 23:24:55 +0200352 usleep_range(1000, 2000);
Rafał Miłeckib60c3c22014-05-17 23:24:54 +0200353
354 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
355 tmp &= ~SSB_TMSLOW_FGC;
Rafał Miłeckib60c3c22014-05-17 23:24:54 +0200356 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
Rafał Miłecki50c1b592014-05-17 23:24:55 +0200357 usleep_range(1000, 2000);
Rafał Miłeckib60c3c22014-05-17 23:24:54 +0200358
359 break;
360#endif
361 }
362}
363
Rafał Miłecki50c1b592014-05-17 23:24:55 +0200364void b43_phy_take_out_of_reset(struct b43_wldev *dev)
365{
366 u32 tmp;
367
368 switch (dev->dev->bus_type) {
369#ifdef CONFIG_B43_BCMA
370 case B43_BUS_BCMA:
371 /* Unset reset bit (with forcing clock) */
372 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
373 tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
374 tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
375 tmp |= BCMA_IOCTL_FGC;
376 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
377 udelay(1);
378
379 /* Do not force clock anymore */
380 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
381 tmp &= ~BCMA_IOCTL_FGC;
382 tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
383 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
384 udelay(1);
385 break;
386#endif
387#ifdef CONFIG_B43_SSB
388 case B43_BUS_SSB:
389 /* Unset reset bit (with forcing clock) */
390 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
391 tmp &= ~B43_TMSLOW_PHYRESET;
392 tmp &= ~B43_TMSLOW_PHYCLKEN;
393 tmp |= SSB_TMSLOW_FGC;
394 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
395 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
396 usleep_range(1000, 2000);
397
398 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
399 tmp &= ~SSB_TMSLOW_FGC;
400 tmp |= B43_TMSLOW_PHYCLKEN;
401 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
402 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
403 usleep_range(1000, 2000);
404 break;
405#endif
406 }
407}
408
Michael Bueschef1a6282008-08-27 18:53:02 +0200409int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
410{
411 struct b43_phy *phy = &(dev->phy);
412 u16 channelcookie, savedcookie;
413 int err;
414
Michael Bueschef1a6282008-08-27 18:53:02 +0200415 /* First we set the channel radio code to prevent the
416 * firmware from sending ghost packets.
417 */
418 channelcookie = new_channel;
419 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
Rafał Miłecki106cb092010-10-06 07:50:07 +0200420 channelcookie |= B43_SHM_SH_CHAN_5GHZ;
421 /* FIXME: set 40Mhz flag if required */
422 if (0)
423 channelcookie |= B43_SHM_SH_CHAN_40MHZ;
Michael Bueschef1a6282008-08-27 18:53:02 +0200424 savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
425 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
426
427 /* Now try to switch the PHY hardware channel. */
428 err = phy->ops->switch_channel(dev, new_channel);
429 if (err)
430 goto err_restore_cookie;
431
Michael Bueschef1a6282008-08-27 18:53:02 +0200432 /* Wait for the radio to tune to the channel and stabilize. */
433 msleep(8);
434
435 return 0;
436
437err_restore_cookie:
438 b43_shm_write16(dev, B43_SHM_SHARED,
439 B43_SHM_SH_CHAN, savedcookie);
440
441 return err;
442}
443
Johannes Berg19d337d2009-06-02 13:01:37 +0200444void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
Michael Bueschef1a6282008-08-27 18:53:02 +0200445{
446 struct b43_phy *phy = &dev->phy;
447
Michael Bueschb929ecf72008-12-19 18:40:00 +0100448 b43_mac_suspend(dev);
Johannes Berg19d337d2009-06-02 13:01:37 +0200449 phy->ops->software_rfkill(dev, blocked);
450 phy->radio_on = !blocked;
Michael Bueschb929ecf72008-12-19 18:40:00 +0100451 b43_mac_enable(dev);
Michael Bueschef1a6282008-08-27 18:53:02 +0200452}
Michael Buesch18c8ade2008-08-28 19:33:40 +0200453
454/**
455 * b43_phy_txpower_adjust_work - TX power workqueue.
456 *
457 * Workqueue for updating the TX power parameters in hardware.
458 */
459void b43_phy_txpower_adjust_work(struct work_struct *work)
460{
461 struct b43_wl *wl = container_of(work, struct b43_wl,
462 txpower_adjust_work);
463 struct b43_wldev *dev;
464
465 mutex_lock(&wl->mutex);
466 dev = wl->current_dev;
467
468 if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
469 dev->phy.ops->adjust_txpower(dev);
470
471 mutex_unlock(&wl->mutex);
472}
473
Michael Buesch18c8ade2008-08-28 19:33:40 +0200474void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
475{
476 struct b43_phy *phy = &dev->phy;
477 unsigned long now = jiffies;
478 enum b43_txpwr_result result;
479
480 if (!(flags & B43_TXPWR_IGNORE_TIME)) {
481 /* Check if it's time for a TXpower check. */
482 if (time_before(now, phy->next_txpwr_check_time))
483 return; /* Not yet */
484 }
485 /* The next check will be needed in two seconds, or later. */
486 phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
487
Rafał Miłecki79d22322011-05-18 02:06:42 +0200488 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
489 (dev->dev->board_type == SSB_BOARD_BU4306))
Michael Buesch18c8ade2008-08-28 19:33:40 +0200490 return; /* No software txpower adjustment needed */
491
492 result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
493 if (result == B43_TXPWR_RES_DONE)
494 return; /* We are done. */
495 B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
496 B43_WARN_ON(phy->ops->adjust_txpower == NULL);
497
498 /* We must adjust the transmission power in hardware.
499 * Schedule b43_phy_txpower_adjust_work(). */
Luis R. Rodriguez42935ec2009-07-29 20:08:07 -0400500 ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
Michael Buesch18c8ade2008-08-28 19:33:40 +0200501}
502
503int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
504{
505 const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
506 unsigned int a, b, c, d;
507 unsigned int average;
508 u32 tmp;
509
510 tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
511 a = tmp & 0xFF;
512 b = (tmp >> 8) & 0xFF;
513 c = (tmp >> 16) & 0xFF;
514 d = (tmp >> 24) & 0xFF;
515 if (a == 0 || a == B43_TSSI_MAX ||
516 b == 0 || b == B43_TSSI_MAX ||
517 c == 0 || c == B43_TSSI_MAX ||
518 d == 0 || d == B43_TSSI_MAX)
519 return -ENOENT;
520 /* The values are OK. Clear them. */
521 tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
522 (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
523 b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
524
525 if (is_ofdm) {
526 a = (a + 32) & 0x3F;
527 b = (b + 32) & 0x3F;
528 c = (c + 32) & 0x3F;
529 d = (d + 32) & 0x3F;
530 }
531
532 /* Get the average of the values with 0.5 added to each value. */
533 average = (a + b + c + d + 2) / 4;
534 if (is_ofdm) {
535 /* Adjust for CCK-boost */
Rafał Miłecki6e6a2cd2012-07-25 16:58:38 +0200536 if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
Michael Buesch18c8ade2008-08-28 19:33:40 +0200537 & B43_HF_CCKBOOST)
538 average = (average >= 13) ? (average - 13) : 0;
539 }
540
541 return average;
542}
Michael Bueschcb24f572008-09-03 12:12:20 +0200543
544void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
545{
546 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
547}
Rafał Miłecki98650452010-01-25 18:59:59 +0100548
Rafał Miłeckiabc1f7c2010-12-07 21:55:58 +0100549
550bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type)
551{
552 return (channel_type == NL80211_CHAN_HT40MINUS ||
553 channel_type == NL80211_CHAN_HT40PLUS);
554}
555
Rafał Miłeckibee6d4b2014-05-31 20:49:40 +0200556bool b43_is_40mhz(struct b43_wldev *dev)
557{
558 return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40;
559}
560
Rafał Miłeckif6a3e992011-08-12 00:03:26 +0200561/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
562void b43_phy_force_clock(struct b43_wldev *dev, bool force)
563{
564 u32 tmp;
565
566 WARN_ON(dev->phy.type != B43_PHYTYPE_N &&
567 dev->phy.type != B43_PHYTYPE_HT);
568
569 switch (dev->dev->bus_type) {
570#ifdef CONFIG_B43_BCMA
571 case B43_BUS_BCMA:
572 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
573 if (force)
574 tmp |= BCMA_IOCTL_FGC;
575 else
576 tmp &= ~BCMA_IOCTL_FGC;
577 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
578 break;
579#endif
580#ifdef CONFIG_B43_SSB
581 case B43_BUS_SSB:
582 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
583 if (force)
584 tmp |= SSB_TMSLOW_FGC;
585 else
586 tmp &= ~SSB_TMSLOW_FGC;
587 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
588 break;
589#endif
590 }
591}
592
Rafał Miłecki6f98e622010-01-25 19:00:00 +0100593/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
Rafał Miłecki98650452010-01-25 18:59:59 +0100594struct b43_c32 b43_cordic(int theta)
595{
Joe Perches5b4bc642010-11-20 18:38:56 -0800596 static const u32 arctg[] = {
597 2949120, 1740967, 919879, 466945, 234379, 117304,
598 58666, 29335, 14668, 7334, 3667, 1833,
599 917, 458, 229, 115, 57, 29,
600 };
Rafał Miłecki6f98e622010-01-25 19:00:00 +0100601 u8 i;
602 s32 tmp;
603 s8 signx = 1;
604 u32 angle = 0;
Rafał Miłecki98650452010-01-25 18:59:59 +0100605 struct b43_c32 ret = { .i = 39797, .q = 0, };
606
Rafał Miłecki6f98e622010-01-25 19:00:00 +0100607 while (theta > (180 << 16))
608 theta -= (360 << 16);
609 while (theta < -(180 << 16))
610 theta += (360 << 16);
Rafał Miłecki98650452010-01-25 18:59:59 +0100611
Rafał Miłecki6f98e622010-01-25 19:00:00 +0100612 if (theta > (90 << 16)) {
613 theta -= (180 << 16);
Rafał Miłecki98650452010-01-25 18:59:59 +0100614 signx = -1;
Rafał Miłecki6f98e622010-01-25 19:00:00 +0100615 } else if (theta < -(90 << 16)) {
616 theta += (180 << 16);
Rafał Miłecki98650452010-01-25 18:59:59 +0100617 signx = -1;
618 }
619
620 for (i = 0; i <= 17; i++) {
621 if (theta > angle) {
622 tmp = ret.i - (ret.q >> i);
623 ret.q += ret.i >> i;
624 ret.i = tmp;
625 angle += arctg[i];
626 } else {
627 tmp = ret.i + (ret.q >> i);
628 ret.q -= ret.i >> i;
629 ret.i = tmp;
630 angle -= arctg[i];
631 }
632 }
633
634 ret.i *= signx;
635 ret.q *= signx;
636
637 return ret;
638}