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Linus Walleijbb3cee22009-04-23 10:22:13 +01001/*
2 *
3 * arch/arm/mach-u300/core.c
4 *
5 *
Linus Walleijfcb28d22012-08-13 10:11:15 +02006 * Copyright (C) 2007-2012 ST-Ericsson SA
Linus Walleijbb3cee22009-04-23 10:22:13 +01007 * License terms: GNU General Public License (GPL) version 2
8 * Core platform support, IRQ handling and device definitions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/interrupt.h>
15#include <linux/bitops.h>
16#include <linux/device.h>
17#include <linux/mm.h>
18#include <linux/termios.h>
Linus Walleijec8f1252010-08-13 11:31:59 +020019#include <linux/dmaengine.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +010020#include <linux/amba/bus.h>
Linus Walleija64ae392012-02-20 21:26:30 +010021#include <linux/amba/mmci.h>
Linus Walleijec8f1252010-08-13 11:31:59 +020022#include <linux/amba/serial.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +010023#include <linux/platform_device.h>
24#include <linux/gpio.h>
Linus Walleijb7276b22010-08-05 07:58:58 +010025#include <linux/clk.h>
26#include <linux/err.h>
Linus Walleij93ac5a52010-09-13 00:35:37 +020027#include <linux/mtd/nand.h>
28#include <linux/mtd/fsmc.h>
Linus Walleij98da3522011-05-02 20:54:38 +020029#include <linux/pinctrl/machine.h>
Linus Walleij51dddfe2012-01-20 17:53:15 +010030#include <linux/pinctrl/pinconf-generic.h>
Jon Medhurstd70a5962011-08-04 15:41:42 +010031#include <linux/dma-mapping.h>
Linus Walleij50667d62012-06-19 23:44:25 +020032#include <linux/platform_data/clk-u300.h>
Linus Walleij65172852012-08-13 10:56:43 +020033#include <linux/platform_data/pinctrl-coh901.h>
Linus Walleij9f575d92013-01-04 10:35:06 +010034#include <linux/platform_data/dma-coh901318.h>
Rob Herring9e47b8b2013-01-07 09:45:59 -060035#include <linux/irqchip/arm-vic.h>
Linus Walleij978577e2013-04-08 11:38:50 +020036#include <linux/irqchip.h>
37#include <linux/of_platform.h>
38#include <linux/clocksource.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +010039
40#include <asm/types.h>
41#include <asm/setup.h>
42#include <asm/memory.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +010043#include <asm/mach/map.h>
Linus Walleij234323b2012-08-13 11:35:55 +020044#include <asm/mach-types.h>
45#include <asm/mach/arch.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +010046
47#include <mach/hardware.h>
48#include <mach/syscon.h>
Linus Walleija4fe2922012-08-13 13:49:45 +020049#include <mach/irqs.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +010050
Linus Walleij234323b2012-08-13 11:35:55 +020051#include "timer.h"
Linus Walleijc7c8c782009-08-14 10:59:05 +010052#include "spi.h"
Linus Walleij6be2a0c2009-08-13 21:42:01 +010053#include "i2c.h"
Linus Walleija64ae392012-02-20 21:26:30 +010054#include "u300-gpio.h"
Linus Walleijbb3cee22009-04-23 10:22:13 +010055
56/*
57 * Static I/O mappings that are needed for booting the U300 platforms. The
58 * only things we need are the areas where we find the timer, syscon and
59 * intcon, since the remaining device drivers will map their own memory
60 * physical to virtual as the need arise.
61 */
62static struct map_desc u300_io_desc[] __initdata = {
63 {
64 .virtual = U300_SLOW_PER_VIRT_BASE,
65 .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
66 .length = SZ_64K,
67 .type = MT_DEVICE,
68 },
69 {
70 .virtual = U300_AHB_PER_VIRT_BASE,
71 .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
72 .length = SZ_32K,
73 .type = MT_DEVICE,
74 },
75 {
76 .virtual = U300_FAST_PER_VIRT_BASE,
77 .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
78 .length = SZ_32K,
79 .type = MT_DEVICE,
80 },
Linus Walleijbb3cee22009-04-23 10:22:13 +010081};
82
Linus Walleij234323b2012-08-13 11:35:55 +020083static void __init u300_map_io(void)
Linus Walleijbb3cee22009-04-23 10:22:13 +010084{
85 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
86}
87
88/*
89 * Declaration of devices found on the U300 board and
90 * their respective memory locations.
91 */
Linus Walleijec8f1252010-08-13 11:31:59 +020092
93static struct amba_pl011_data uart0_plat_data = {
94#ifdef CONFIG_COH901318
95 .dma_filter = coh901318_filter_id,
96 .dma_rx_param = (void *) U300_DMA_UART0_RX,
97 .dma_tx_param = (void *) U300_DMA_UART0_TX,
98#endif
99};
100
Russell King6db2a452011-12-18 15:26:38 +0000101/* Slow device at 0x3000 offset */
102static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
103 { IRQ_U300_UART0 }, &uart0_plat_data);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100104
105/* The U335 have an additional UART1 on the APP CPU */
Linus Walleijec8f1252010-08-13 11:31:59 +0200106static struct amba_pl011_data uart1_plat_data = {
107#ifdef CONFIG_COH901318
108 .dma_filter = coh901318_filter_id,
109 .dma_rx_param = (void *) U300_DMA_UART1_RX,
110 .dma_tx_param = (void *) U300_DMA_UART1_TX,
111#endif
112};
113
Russell King6db2a452011-12-18 15:26:38 +0000114/* Fast device at 0x7000 offset */
115static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
116 { IRQ_U300_UART1 }, &uart1_plat_data);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100117
Russell King6db2a452011-12-18 15:26:38 +0000118/* AHB device at 0x4000 offset */
119static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100120
Russell King6db2a452011-12-18 15:26:38 +0000121/* Fast device at 0x6000 offset */
122static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
123 { IRQ_U300_SPI }, NULL);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100124
Russell King6db2a452011-12-18 15:26:38 +0000125/* Fast device at 0x1000 offset */
126#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
127
Linus Walleija64ae392012-02-20 21:26:30 +0100128static struct mmci_platform_data mmcsd_platform_data = {
129 /*
130 * Do not set ocr_mask or voltage translation function,
131 * we have a regulator we can control instead.
132 */
133 .f_max = 24000000,
134 .gpio_wp = -1,
135 .gpio_cd = U300_GPIO_PIN_MMC_CD,
136 .cd_invert = true,
137 .capabilities = MMC_CAP_MMC_HIGHSPEED |
138 MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
139#ifdef CONFIG_COH901318
140 .dma_filter = coh901318_filter_id,
141 .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
142 /* Don't specify a TX channel, this RX channel is bidirectional */
143#endif
144};
145
Russell King6db2a452011-12-18 15:26:38 +0000146static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
Linus Walleija64ae392012-02-20 21:26:30 +0100147 U300_MMCSD_IRQS, &mmcsd_platform_data);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100148
149/*
150 * The order of device declaration may be important, since some devices
151 * have dependencies on other devices being initialized first.
152 */
153static struct amba_device *amba_devs[] __initdata = {
154 &uart0_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100155 &uart1_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100156 &pl022_device,
157 &pl172_device,
158 &mmcsd_device,
159};
160
161/* Here follows a list of all hw resources that the platform devices
162 * allocate. Note, clock dependencies are not included
163 */
164
165static struct resource gpio_resources[] = {
166 {
167 .start = U300_GPIO_BASE,
168 .end = (U300_GPIO_BASE + SZ_4K - 1),
169 .flags = IORESOURCE_MEM,
170 },
171 {
172 .name = "gpio0",
173 .start = IRQ_U300_GPIO_PORT0,
174 .end = IRQ_U300_GPIO_PORT0,
175 .flags = IORESOURCE_IRQ,
176 },
177 {
178 .name = "gpio1",
179 .start = IRQ_U300_GPIO_PORT1,
180 .end = IRQ_U300_GPIO_PORT1,
181 .flags = IORESOURCE_IRQ,
182 },
183 {
184 .name = "gpio2",
185 .start = IRQ_U300_GPIO_PORT2,
186 .end = IRQ_U300_GPIO_PORT2,
187 .flags = IORESOURCE_IRQ,
188 },
Linus Walleijbb3cee22009-04-23 10:22:13 +0100189 {
190 .name = "gpio3",
191 .start = IRQ_U300_GPIO_PORT3,
192 .end = IRQ_U300_GPIO_PORT3,
193 .flags = IORESOURCE_IRQ,
194 },
195 {
196 .name = "gpio4",
197 .start = IRQ_U300_GPIO_PORT4,
198 .end = IRQ_U300_GPIO_PORT4,
199 .flags = IORESOURCE_IRQ,
200 },
Linus Walleijbb3cee22009-04-23 10:22:13 +0100201 {
202 .name = "gpio5",
203 .start = IRQ_U300_GPIO_PORT5,
204 .end = IRQ_U300_GPIO_PORT5,
205 .flags = IORESOURCE_IRQ,
206 },
207 {
208 .name = "gpio6",
209 .start = IRQ_U300_GPIO_PORT6,
210 .end = IRQ_U300_GPIO_PORT6,
211 .flags = IORESOURCE_IRQ,
212 },
Linus Walleijbb3cee22009-04-23 10:22:13 +0100213};
214
215static struct resource keypad_resources[] = {
216 {
217 .start = U300_KEYPAD_BASE,
218 .end = U300_KEYPAD_BASE + SZ_4K - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 {
222 .name = "coh901461-press",
223 .start = IRQ_U300_KEYPAD_KEYBF,
224 .end = IRQ_U300_KEYPAD_KEYBF,
225 .flags = IORESOURCE_IRQ,
226 },
227 {
228 .name = "coh901461-release",
229 .start = IRQ_U300_KEYPAD_KEYBR,
230 .end = IRQ_U300_KEYPAD_KEYBR,
231 .flags = IORESOURCE_IRQ,
232 },
233};
234
235static struct resource rtc_resources[] = {
236 {
237 .start = U300_RTC_BASE,
238 .end = U300_RTC_BASE + SZ_4K - 1,
239 .flags = IORESOURCE_MEM,
240 },
241 {
242 .start = IRQ_U300_RTC,
243 .end = IRQ_U300_RTC,
244 .flags = IORESOURCE_IRQ,
245 },
246};
247
248/*
249 * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
250 * but these are not yet used by the driver.
251 */
252static struct resource fsmc_resources[] = {
253 {
Jean-Christophe PLAGNIOL-VILLARD6d7b42a2012-10-04 15:14:16 +0200254 .name = "nand_addr",
255 .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
256 .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
257 .flags = IORESOURCE_MEM,
258 },
259 {
260 .name = "nand_cmd",
261 .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
262 .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
263 .flags = IORESOURCE_MEM,
264 },
265 {
Linus Walleij93ac5a52010-09-13 00:35:37 +0200266 .name = "nand_data",
267 .start = U300_NAND_CS0_PHYS_BASE,
268 .end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
269 .flags = IORESOURCE_MEM,
270 },
271 {
272 .name = "fsmc_regs",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100273 .start = U300_NAND_IF_PHYS_BASE,
274 .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
275 .flags = IORESOURCE_MEM,
276 },
277};
278
279static struct resource i2c0_resources[] = {
280 {
281 .start = U300_I2C0_BASE,
282 .end = U300_I2C0_BASE + SZ_4K - 1,
283 .flags = IORESOURCE_MEM,
284 },
285 {
286 .start = IRQ_U300_I2C0,
287 .end = IRQ_U300_I2C0,
288 .flags = IORESOURCE_IRQ,
289 },
290};
291
292static struct resource i2c1_resources[] = {
293 {
294 .start = U300_I2C1_BASE,
295 .end = U300_I2C1_BASE + SZ_4K - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 {
299 .start = IRQ_U300_I2C1,
300 .end = IRQ_U300_I2C1,
301 .flags = IORESOURCE_IRQ,
302 },
303
304};
305
306static struct resource wdog_resources[] = {
307 {
308 .start = U300_WDOG_BASE,
309 .end = U300_WDOG_BASE + SZ_4K - 1,
310 .flags = IORESOURCE_MEM,
311 },
312 {
313 .start = IRQ_U300_WDOG,
314 .end = IRQ_U300_WDOG,
315 .flags = IORESOURCE_IRQ,
316 }
317};
318
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100319static struct resource dma_resource[] = {
320 {
321 .start = U300_DMAC_BASE,
322 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
323 .flags = IORESOURCE_MEM,
324 },
325 {
326 .start = IRQ_U300_DMA,
327 .end = IRQ_U300_DMA,
328 .flags = IORESOURCE_IRQ,
329 }
330};
331
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100332
Linus Walleij128a06d2012-02-21 14:31:45 +0100333static struct resource pinctrl_resources[] = {
Linus Walleij98da3522011-05-02 20:54:38 +0200334 {
335 .start = U300_SYSCON_BASE,
336 .end = U300_SYSCON_BASE + SZ_4K - 1,
337 .flags = IORESOURCE_MEM,
338 },
339};
340
Linus Walleijbb3cee22009-04-23 10:22:13 +0100341static struct platform_device wdog_device = {
Linus Walleij633e81a2010-01-25 07:18:16 +0100342 .name = "coh901327_wdog",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100343 .id = -1,
344 .num_resources = ARRAY_SIZE(wdog_resources),
345 .resource = wdog_resources,
346};
347
348static struct platform_device i2c0_device = {
Linus Walleij6be2a0c2009-08-13 21:42:01 +0100349 .name = "stu300",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100350 .id = 0,
351 .num_resources = ARRAY_SIZE(i2c0_resources),
352 .resource = i2c0_resources,
353};
354
355static struct platform_device i2c1_device = {
Linus Walleij6be2a0c2009-08-13 21:42:01 +0100356 .name = "stu300",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100357 .id = 1,
358 .num_resources = ARRAY_SIZE(i2c1_resources),
359 .resource = i2c1_resources,
360};
361
Linus Walleij128a06d2012-02-21 14:31:45 +0100362static struct platform_device pinctrl_device = {
363 .name = "pinctrl-u300",
364 .id = -1,
365 .num_resources = ARRAY_SIZE(pinctrl_resources),
366 .resource = pinctrl_resources,
367};
368
Linus Walleijcc890cd2011-09-08 09:04:51 +0100369/*
370 * The different variants have a few different versions of the
371 * GPIO block, with different number of ports.
372 */
373static struct u300_gpio_platform u300_gpio_plat = {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100374 .ports = 7,
Linus Walleijcc890cd2011-09-08 09:04:51 +0100375 .gpio_base = 0,
Linus Walleijcc890cd2011-09-08 09:04:51 +0100376};
377
Linus Walleijbb3cee22009-04-23 10:22:13 +0100378static struct platform_device gpio_device = {
379 .name = "u300-gpio",
380 .id = -1,
381 .num_resources = ARRAY_SIZE(gpio_resources),
382 .resource = gpio_resources,
Linus Walleijcc890cd2011-09-08 09:04:51 +0100383 .dev = {
384 .platform_data = &u300_gpio_plat,
385 },
Linus Walleijbb3cee22009-04-23 10:22:13 +0100386};
387
388static struct platform_device keypad_device = {
389 .name = "keypad",
390 .id = -1,
391 .num_resources = ARRAY_SIZE(keypad_resources),
392 .resource = keypad_resources,
393};
394
395static struct platform_device rtc_device = {
Linus Walleij378ce742009-11-14 01:03:24 +0100396 .name = "rtc-coh901331",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100397 .id = -1,
398 .num_resources = ARRAY_SIZE(rtc_resources),
399 .resource = rtc_resources,
400};
401
Linus Walleij93ac5a52010-09-13 00:35:37 +0200402static struct mtd_partition u300_partitions[] = {
403 {
404 .name = "bootrecords",
405 .offset = 0,
406 .size = SZ_128K,
407 },
408 {
409 .name = "free",
410 .offset = SZ_128K,
411 .size = 8064 * SZ_1K,
412 },
413 {
414 .name = "platform",
415 .offset = 8192 * SZ_1K,
416 .size = 253952 * SZ_1K,
417 },
418};
419
420static struct fsmc_nand_platform_data nand_platform_data = {
421 .partitions = u300_partitions,
422 .nr_partitions = ARRAY_SIZE(u300_partitions),
423 .options = NAND_SKIP_BBTSCAN,
424 .width = FSMC_NAND_BW8,
425};
426
427static struct platform_device nand_device = {
428 .name = "fsmc-nand",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100429 .id = -1,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100430 .resource = fsmc_resources,
Linus Walleij93ac5a52010-09-13 00:35:37 +0200431 .num_resources = ARRAY_SIZE(fsmc_resources),
432 .dev = {
433 .platform_data = &nand_platform_data,
434 },
Linus Walleijbb3cee22009-04-23 10:22:13 +0100435};
436
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100437static struct platform_device dma_device = {
438 .name = "coh901318",
439 .id = -1,
440 .resource = dma_resource,
441 .num_resources = ARRAY_SIZE(dma_resource),
442 .dev = {
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100443 .coherent_dma_mask = ~0,
444 },
445};
446
Linus Walleij51dddfe2012-01-20 17:53:15 +0100447static unsigned long pin_pullup_conf[] = {
448 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
449};
450
451static unsigned long pin_highz_conf[] = {
452 PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
453};
454
455/* Pin control settings */
Linus Walleije93bcee2012-02-09 07:23:28 +0100456static struct pinctrl_map __initdata u300_pinmux_map[] = {
Linus Walleij98da3522011-05-02 20:54:38 +0200457 /* anonymous maps for chip power and EMIFs */
Stephen Warren1e2082b2012-03-02 13:05:48 -0700458 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
459 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
460 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
Linus Walleij98da3522011-05-02 20:54:38 +0200461 /* per-device maps for MMC/SD, SPI and UART */
Stephen Warren1e2082b2012-03-02 13:05:48 -0700462 PIN_MAP_MUX_GROUP_DEFAULT("mmci", "pinctrl-u300", NULL, "mmc0"),
463 PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
464 PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
Linus Walleij51dddfe2012-01-20 17:53:15 +0100465 /* This pin is used for clock return rather than GPIO */
466 PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
467 pin_pullup_conf),
468 /* This pin is used for card detect */
469 PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
470 pin_highz_conf),
Linus Walleij98da3522011-05-02 20:54:38 +0200471};
472
Linus Walleijbb3cee22009-04-23 10:22:13 +0100473/*
474 * Notice that AMBA devices are initialized before platform devices.
475 *
476 */
477static struct platform_device *platform_devs[] __initdata = {
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100478 &dma_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100479 &i2c0_device,
480 &i2c1_device,
481 &keypad_device,
482 &rtc_device,
Linus Walleij8604ac32012-11-20 14:42:47 +0100483 &pinctrl_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100484 &gpio_device,
Linus Walleij93ac5a52010-09-13 00:35:37 +0200485 &nand_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100486 &wdog_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100487};
488
Linus Walleijbb3cee22009-04-23 10:22:13 +0100489/*
490 * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
491 * together so some interrupts are connected to the first one and some
492 * to the second one.
493 */
Linus Walleij234323b2012-08-13 11:35:55 +0200494static void __init u300_init_irq(void)
Linus Walleijbb3cee22009-04-23 10:22:13 +0100495{
496 u32 mask[2] = {0, 0};
Linus Walleijb7276b22010-08-05 07:58:58 +0100497 struct clk *clk;
Linus Walleijbb3cee22009-04-23 10:22:13 +0100498 int i;
499
Linus Walleij379aae52010-08-05 07:58:13 +0100500 /* initialize clocking early, we want to clock the INTCON */
Linus Walleij50667d62012-06-19 23:44:25 +0200501 u300_clk_init(U300_SYSCON_VBASE);
502
503 /* Bootstrap EMIF and SEMI clocks */
504 clk = clk_get_sys("pl172", NULL);
505 BUG_ON(IS_ERR(clk));
506 clk_prepare_enable(clk);
507 clk = clk_get_sys("semi", NULL);
508 BUG_ON(IS_ERR(clk));
509 clk_prepare_enable(clk);
Linus Walleij379aae52010-08-05 07:58:13 +0100510
Linus Walleijb7276b22010-08-05 07:58:58 +0100511 /* Clock the interrupt controller */
512 clk = clk_get_sys("intcon", NULL);
513 BUG_ON(IS_ERR(clk));
Linus Walleij50667d62012-06-19 23:44:25 +0200514 clk_prepare_enable(clk);
Linus Walleijb7276b22010-08-05 07:58:58 +0100515
Linus Walleijcc890cd2011-09-08 09:04:51 +0100516 for (i = 0; i < U300_VIC_IRQS_END; i++)
Linus Walleijbb3cee22009-04-23 10:22:13 +0100517 set_bit(i, (unsigned long *) &mask[0]);
Linus Walleij13445002012-04-18 15:29:58 +0200518 vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
519 mask[0], mask[0]);
520 vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
521 mask[1], mask[1]);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100522}
523
524
525/*
526 * U300 platforms peripheral handling
527 */
528struct db_chip {
529 u16 chipid;
530 const char *name;
531};
532
533/*
534 * This is a list of the Digital Baseband chips used in the U300 platform.
535 */
536static struct db_chip db_chips[] __initdata = {
537 {
538 .chipid = 0xb800,
539 .name = "DB3000",
540 },
541 {
542 .chipid = 0xc000,
543 .name = "DB3100",
544 },
545 {
546 .chipid = 0xc800,
547 .name = "DB3150",
548 },
549 {
550 .chipid = 0xd800,
551 .name = "DB3200",
552 },
553 {
554 .chipid = 0xe000,
555 .name = "DB3250",
556 },
557 {
558 .chipid = 0xe800,
559 .name = "DB3210",
560 },
561 {
562 .chipid = 0xf000,
563 .name = "DB3350 P1x",
564 },
565 {
566 .chipid = 0xf100,
567 .name = "DB3350 P2x",
568 },
569 {
570 .chipid = 0x0000, /* List terminator */
571 .name = NULL,
572 }
573};
574
Linus Walleija2bb9f42009-08-13 21:57:22 +0100575static void __init u300_init_check_chip(void)
Linus Walleijbb3cee22009-04-23 10:22:13 +0100576{
577
578 u16 val;
579 struct db_chip *chip;
580 const char *chipname;
581 const char unknown[] = "UNKNOWN";
582
583 /* Read out and print chip ID */
584 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
585 /* This is in funky bigendian order... */
586 val = (val & 0xFFU) << 8 | (val >> 8);
587 chip = db_chips;
588 chipname = unknown;
589
590 for ( ; chip->chipid; chip++) {
591 if (chip->chipid == (val & 0xFF00U)) {
592 chipname = chip->name;
593 break;
594 }
595 }
596 printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
597 "(chip ID 0x%04x)\n", chipname, val);
598
Linus Walleijbb3cee22009-04-23 10:22:13 +0100599 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
Linus Walleijec8f1252010-08-13 11:31:59 +0200600 printk(KERN_ERR "Platform configured for BS335 " \
Linus Walleijbb3cee22009-04-23 10:22:13 +0100601 " with DB3350 but %s detected, expect problems!",
602 chipname);
603 }
Linus Walleijbb3cee22009-04-23 10:22:13 +0100604}
605
606/*
607 * Some devices and their resources require reserved physical memory from
608 * the end of the available RAM. This function traverses the list of devices
Daniel Mack3ad2f3f2010-02-03 08:01:28 +0800609 * and assigns actual addresses to these.
Linus Walleijbb3cee22009-04-23 10:22:13 +0100610 */
611static void __init u300_assign_physmem(void)
612{
613 unsigned long curr_start = __pa(high_memory);
614 int i, j;
615
616 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
617 for (j = 0; j < platform_devs[i]->num_resources; j++) {
618 struct resource *const res =
619 &platform_devs[i]->resource[j];
620
621 if (IORESOURCE_MEM == res->flags &&
622 0 == res->start) {
623 res->start = curr_start;
624 res->end += curr_start;
Joe Perches28f65c112011-06-09 09:13:32 -0700625 curr_start += resource_size(res);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100626
627 printk(KERN_INFO "core.c: Mapping RAM " \
628 "%#x-%#x to device %s:%s\n",
629 res->start, res->end,
630 platform_devs[i]->name, res->name);
631 }
632 }
633 }
634}
635
Linus Walleij234323b2012-08-13 11:35:55 +0200636static void __init u300_init_machine(void)
Linus Walleijbb3cee22009-04-23 10:22:13 +0100637{
638 int i;
639 u16 val;
640
641 /* Check what platform we run and print some status information */
642 u300_init_check_chip();
643
Linus Walleijc7c8c782009-08-14 10:59:05 +0100644 /* Initialize SPI device with some board specifics */
645 u300_spi_init(&pl022_device);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100646
647 /* Register the AMBA devices in the AMBA bus abstraction layer */
Linus Walleijbb3cee22009-04-23 10:22:13 +0100648 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
649 struct amba_device *d = amba_devs[i];
650 amba_device_register(d, &iomem_resource);
651 }
Linus Walleijbb3cee22009-04-23 10:22:13 +0100652
653 u300_assign_physmem();
654
Linus Walleij98da3522011-05-02 20:54:38 +0200655 /* Initialize pinmuxing */
Linus Walleije93bcee2012-02-09 07:23:28 +0100656 pinctrl_register_mappings(u300_pinmux_map,
657 ARRAY_SIZE(u300_pinmux_map));
Linus Walleij98da3522011-05-02 20:54:38 +0200658
Linus Walleij6be2a0c2009-08-13 21:42:01 +0100659 /* Register subdevices on the I2C buses */
660 u300_i2c_register_board_devices();
661
Linus Walleijbb3cee22009-04-23 10:22:13 +0100662 /* Register the platform devices */
663 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
664
Linus Walleijec8f1252010-08-13 11:31:59 +0200665 /* Register subdevices on the SPI bus */
666 u300_spi_register_board_devices();
667
Linus Walleijc43ed562011-08-09 21:30:01 +0200668 /* Enable SEMI self refresh */
Linus Walleijbb3cee22009-04-23 10:22:13 +0100669 val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
670 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
671 writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100672}
673
Russell King7e3974b2011-11-05 15:51:25 +0000674/* Forward declare this function from the watchdog */
675void coh901327_watchdog_reset(void);
676
Linus Walleij234323b2012-08-13 11:35:55 +0200677static void u300_restart(char mode, const char *cmd)
Russell King7e3974b2011-11-05 15:51:25 +0000678{
679 switch (mode) {
680 case 's':
681 case 'h':
Russell King7e3974b2011-11-05 15:51:25 +0000682#ifdef CONFIG_COH901327_WATCHDOG
683 coh901327_watchdog_reset();
684#endif
685 break;
686 default:
687 /* Do nothing */
688 break;
689 }
690 /* Wait for system do die/reset. */
691 while (1);
692}
Linus Walleij234323b2012-08-13 11:35:55 +0200693
694MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
695 /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
696 .atag_offset = 0x100,
697 .map_io = u300_map_io,
Linus Walleijd4a31ee2012-10-17 13:16:46 +0200698 .nr_irqs = 0,
Linus Walleij234323b2012-08-13 11:35:55 +0200699 .init_irq = u300_init_irq,
Stephen Warren6bb27d72012-11-08 12:40:59 -0700700 .init_time = u300_timer_init,
Linus Walleij234323b2012-08-13 11:35:55 +0200701 .init_machine = u300_init_machine,
702 .restart = u300_restart,
703MACHINE_END
Linus Walleij978577e2013-04-08 11:38:50 +0200704
705#ifdef CONFIG_OF
706
707/* These are mostly to get the right device names for the clock lookups */
708static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
709 OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
710 "pinctrl-u300", NULL),
711 OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
712 "u300-gpio", &u300_gpio_plat),
713 OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
714 "uart0", &uart0_plat_data),
715 OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
716 "uart1", &uart1_plat_data),
Linus Walleijc023b8b2013-04-11 15:13:39 +0200717 OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
718 "stu300.0", NULL),
719 OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
720 "stu300.1", NULL),
Linus Walleij978577e2013-04-08 11:38:50 +0200721 OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
722 "mmci", &mmcsd_platform_data),
723 { /* sentinel */ },
724};
725
726static void __init u300_init_irq_dt(void)
727{
728 struct clk *clk;
729
730 /* initialize clocking early, we want to clock the INTCON */
731 u300_clk_init(U300_SYSCON_VBASE);
732
733 /* Bootstrap EMIF and SEMI clocks */
734 clk = clk_get_sys("pl172", NULL);
735 BUG_ON(IS_ERR(clk));
736 clk_prepare_enable(clk);
737 clk = clk_get_sys("semi", NULL);
738 BUG_ON(IS_ERR(clk));
739 clk_prepare_enable(clk);
740
741 /* Clock the interrupt controller */
742 clk = clk_get_sys("intcon", NULL);
743 BUG_ON(IS_ERR(clk));
744 clk_prepare_enable(clk);
745
746 irqchip_init();
747}
748
749static void __init u300_init_machine_dt(void)
750{
751 u16 val;
752
753 /* Check what platform we run and print some status information */
754 u300_init_check_chip();
755
756 u300_assign_physmem();
757
758 /* Initialize pinmuxing */
759 pinctrl_register_mappings(u300_pinmux_map,
760 ARRAY_SIZE(u300_pinmux_map));
761
762 of_platform_populate(NULL, of_default_bus_match_table,
763 u300_auxdata_lookup, NULL);
764
765 /* Enable SEMI self refresh */
766 val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
767 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
768 writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
769}
770
771static const char * u300_board_compat[] = {
772 "stericsson,u300",
773 NULL,
774};
775
776DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
777 .map_io = u300_map_io,
778 .init_irq = u300_init_irq_dt,
779 .init_time = clocksource_of_init,
780 .init_machine = u300_init_machine_dt,
781 .restart = u300_restart,
782 .dt_compat = u300_board_compat,
783MACHINE_END
784
785#endif /* CONFIG_OF */