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Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001/* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *
9 * Copyright (c) 2011 by:
Mauro Carvalho Chehab37e59f82014-02-07 08:03:07 -020010 * Mauro Carvalho Chehab
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020011 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/pci_ids.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/edac.h>
20#include <linux/mmzone.h>
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020021#include <linux/smp.h>
22#include <linux/bitmap.h>
Mauro Carvalho Chehab5b889e32011-11-07 18:26:53 -030023#include <linux/math64.h>
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020024#include <asm/processor.h>
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -020025#include <asm/mce.h>
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020026
27#include "edac_core.h"
28
29/* Static vars */
30static LIST_HEAD(sbridge_edac_list);
31static DEFINE_MUTEX(sbridge_edac_lock);
32static int probed;
33
34/*
35 * Alter this version for the module when modifications are made
36 */
Tony Luck7d375bf2015-05-18 17:50:42 -030037#define SBRIDGE_REVISION " Ver: 1.1.1 "
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020038#define EDAC_MOD_STR "sbridge_edac"
39
40/*
41 * Debug macros
42 */
43#define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
45
46#define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
48
49/*
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 */
52#define GET_BITFIELD(v, lo, hi) \
Chen, Gong10ef6b02013-10-18 14:29:07 -070053 (((v) & GENMASK_ULL(hi, lo)) >> (lo))
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020054
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020055/* Devices 12 Function 6, Offsets 0x80 to 0xcc */
Aristeu Rozanski464f1d82013-10-30 13:27:00 -030056static const u32 sbridge_dram_rule[] = {
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020057 0x80, 0x88, 0x90, 0x98, 0xa0,
58 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
59};
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020060
Aristeu Rozanski4d715a82013-10-30 13:27:06 -030061static const u32 ibridge_dram_rule[] = {
62 0x60, 0x68, 0x70, 0x78, 0x80,
63 0x88, 0x90, 0x98, 0xa0, 0xa8,
64 0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
65 0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
66};
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020067
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020068#define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -030069#define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020070
Jim Snowc59f9c02015-12-03 10:48:52 +010071static char *show_dram_attr(u32 attr)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020072{
Jim Snowc59f9c02015-12-03 10:48:52 +010073 switch (attr) {
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020074 case 0:
75 return "DRAM";
76 case 1:
77 return "MMCFG";
78 case 2:
79 return "NXM";
80 default:
81 return "unknown";
82 }
83}
84
Aristeu Rozanskief1ce512013-10-30 13:27:01 -030085static const u32 sbridge_interleave_list[] = {
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020086 0x84, 0x8c, 0x94, 0x9c, 0xa4,
87 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
88};
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020089
Aristeu Rozanski4d715a82013-10-30 13:27:06 -030090static const u32 ibridge_interleave_list[] = {
91 0x64, 0x6c, 0x74, 0x7c, 0x84,
92 0x8c, 0x94, 0x9c, 0xa4, 0xac,
93 0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
94 0xdc, 0xe4, 0xec, 0xf4, 0xfc,
95};
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -020096
Aristeu Rozanskicc311992013-10-30 13:27:02 -030097struct interleave_pkg {
98 unsigned char start;
99 unsigned char end;
100};
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200101
Aristeu Rozanskicc311992013-10-30 13:27:02 -0300102static const struct interleave_pkg sbridge_interleave_pkg[] = {
103 { 0, 2 },
104 { 3, 5 },
105 { 8, 10 },
106 { 11, 13 },
107 { 16, 18 },
108 { 19, 21 },
109 { 24, 26 },
110 { 27, 29 },
111};
112
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300113static const struct interleave_pkg ibridge_interleave_pkg[] = {
114 { 0, 3 },
115 { 4, 7 },
116 { 8, 11 },
117 { 12, 15 },
118 { 16, 19 },
119 { 20, 23 },
120 { 24, 27 },
121 { 28, 31 },
122};
123
Aristeu Rozanskicc311992013-10-30 13:27:02 -0300124static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
125 int interleave)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200126{
Aristeu Rozanskicc311992013-10-30 13:27:02 -0300127 return GET_BITFIELD(reg, table[interleave].start,
128 table[interleave].end);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200129}
130
131/* Devices 12 Function 7 */
132
133#define TOLM 0x80
134#define TOHM 0x84
Tony Luckf7cf2a22014-10-29 10:36:50 -0700135#define HASWELL_TOLM 0xd0
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300136#define HASWELL_TOHM_0 0xd4
137#define HASWELL_TOHM_1 0xd8
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200138
139#define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
140#define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
141
142/* Device 13 Function 6 */
143
144#define SAD_TARGET 0xf0
145
146#define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
147
148#define SAD_CONTROL 0xf4
149
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200150/* Device 14 function 0 */
151
152static const u32 tad_dram_rule[] = {
153 0x40, 0x44, 0x48, 0x4c,
154 0x50, 0x54, 0x58, 0x5c,
155 0x60, 0x64, 0x68, 0x6c,
156};
157#define MAX_TAD ARRAY_SIZE(tad_dram_rule)
158
159#define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
160#define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
161#define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
162#define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
163#define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
164#define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
165#define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
166
167/* Device 15, function 0 */
168
169#define MCMTR 0x7c
170
171#define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
172#define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
173#define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
174
175/* Device 15, function 1 */
176
177#define RASENABLES 0xac
178#define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
179
180/* Device 15, functions 2-5 */
181
182static const int mtr_regs[] = {
183 0x80, 0x84, 0x88,
184};
185
186#define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
187#define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
188#define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
189#define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
190#define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
191
192static const u32 tad_ch_nilv_offset[] = {
193 0x90, 0x94, 0x98, 0x9c,
194 0xa0, 0xa4, 0xa8, 0xac,
195 0xb0, 0xb4, 0xb8, 0xbc,
196};
197#define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
198#define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
199
200static const u32 rir_way_limit[] = {
201 0x108, 0x10c, 0x110, 0x114, 0x118,
202};
203#define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
204
205#define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
206#define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200207
208#define MAX_RIR_WAY 8
209
210static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
211 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
212 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
213 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
214 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
215 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
216};
217
218#define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
219#define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
220
221/* Device 16, functions 2-7 */
222
223/*
224 * FIXME: Implement the error count reads directly
225 */
226
227static const u32 correrrcnt[] = {
228 0x104, 0x108, 0x10c, 0x110,
229};
230
231#define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
232#define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
233#define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
234#define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
235
236static const u32 correrrthrsld[] = {
237 0x11c, 0x120, 0x124, 0x128,
238};
239
240#define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
241#define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
242
243
244/* Device 17, function 0 */
245
Aristeu Rozanskief1e8d02013-10-30 13:26:56 -0300246#define SB_RANK_CFG_A 0x0328
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200247
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300248#define IB_RANK_CFG_A 0x0320
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200249
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200250/*
251 * sbridge structs
252 */
253
Tony Luck7d375bf2015-05-18 17:50:42 -0300254#define NUM_CHANNELS 8 /* 2MC per socket, four chan per MC */
Seth Jennings351fc4a2014-09-05 14:28:47 -0500255#define MAX_DIMMS 3 /* Max DIMMS per channel */
256#define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200257
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300258enum type {
259 SANDY_BRIDGE,
260 IVY_BRIDGE,
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300261 HASWELL,
Tony Luck1f395812014-12-02 09:27:30 -0800262 BROADWELL,
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300263};
264
Aristeu Rozanskifb79a502013-10-30 13:26:57 -0300265struct sbridge_pvt;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200266struct sbridge_info {
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300267 enum type type;
Aristeu Rozanski464f1d82013-10-30 13:27:00 -0300268 u32 mcmtr;
269 u32 rankcfgr;
270 u64 (*get_tolm)(struct sbridge_pvt *pvt);
271 u64 (*get_tohm)(struct sbridge_pvt *pvt);
Aristeu Rozanskib976bcf2014-06-02 15:15:24 -0300272 u64 (*rir_limit)(u32 reg);
Jim Snowc59f9c02015-12-03 10:48:52 +0100273 u64 (*sad_limit)(u32 reg);
274 u32 (*interleave_mode)(u32 reg);
275 char* (*show_interleave_mode)(u32 reg);
276 u32 (*dram_attr)(u32 reg);
Aristeu Rozanski464f1d82013-10-30 13:27:00 -0300277 const u32 *dram_rule;
Aristeu Rozanskief1ce512013-10-30 13:27:01 -0300278 const u32 *interleave_list;
Aristeu Rozanskicc311992013-10-30 13:27:02 -0300279 const struct interleave_pkg *interleave_pkg;
Aristeu Rozanski464f1d82013-10-30 13:27:00 -0300280 u8 max_sad;
Aristeu Rozanskief1ce512013-10-30 13:27:01 -0300281 u8 max_interleave;
Aristeu Rozanskif14d6892014-06-02 15:15:23 -0300282 u8 (*get_node_id)(struct sbridge_pvt *pvt);
Aristeu Rozanski9e375442014-06-02 15:15:22 -0300283 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
Aristeu Rozanski12f07212015-06-12 15:08:17 -0400284 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300285 struct pci_dev *pci_vtd;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200286};
287
288struct sbridge_channel {
289 u32 ranks;
290 u32 dimms;
291};
292
293struct pci_id_descr {
Mauro Carvalho Chehabc41afdc2014-06-26 15:35:14 -0300294 int dev_id;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200295 int optional;
296};
297
298struct pci_id_table {
299 const struct pci_id_descr *descr;
300 int n_devs;
301};
302
303struct sbridge_dev {
304 struct list_head list;
305 u8 bus, mc;
306 u8 node_id, source_id;
307 struct pci_dev **pdev;
308 int n_devs;
309 struct mem_ctl_info *mci;
310};
311
312struct sbridge_pvt {
313 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300314 struct pci_dev *pci_sad0, *pci_sad1;
315 struct pci_dev *pci_ha0, *pci_ha1;
316 struct pci_dev *pci_br0, *pci_br1;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300317 struct pci_dev *pci_ha1_ta;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200318 struct pci_dev *pci_tad[NUM_CHANNELS];
319
320 struct sbridge_dev *sbridge_dev;
321
322 struct sbridge_info info;
323 struct sbridge_channel channel[NUM_CHANNELS];
324
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200325 /* Memory type detection */
326 bool is_mirrored, is_lockstep, is_close_pg;
327
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200328 /* Fifo double buffers */
329 struct mce mce_entry[MCE_LOG_LEN];
330 struct mce mce_outentry[MCE_LOG_LEN];
331
332 /* Fifo in/out counters */
333 unsigned mce_in, mce_out;
334
335 /* Count indicator to show errors not got */
336 unsigned mce_overrun;
337
338 /* Memory description */
339 u64 tolm, tohm;
340};
341
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300342#define PCI_DESCR(device_id, opt) \
343 .dev_id = (device_id), \
Luck, Tonyde4772c2013-03-28 09:59:15 -0700344 .optional = opt
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200345
346static const struct pci_id_descr pci_dev_descr_sbridge[] = {
347 /* Processor Home Agent */
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300348 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) },
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200349
350 /* Memory controller */
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300351 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) },
352 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) },
353 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) },
354 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) },
355 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) },
356 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) },
357 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) },
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200358
359 /* System Address Decoder */
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300360 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) },
361 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) },
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200362
363 /* Broadcast Registers */
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300364 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) },
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200365};
366
367#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
368static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
369 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
370 {0,} /* 0 terminated list. */
371};
372
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300373/* This changes depending if 1HA or 2HA:
374 * 1HA:
375 * 0x0eb8 (17.0) is DDRIO0
376 * 2HA:
377 * 0x0ebc (17.4) is DDRIO0
378 */
379#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
380#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
381
382/* pci ids */
383#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
384#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
385#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
386#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
387#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
388#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
389#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
390#define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
391#define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
392#define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
393#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
394#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
395#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
396#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
397#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
Tony Luck7d375bf2015-05-18 17:50:42 -0300398#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c
399#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300400
401static const struct pci_id_descr pci_dev_descr_ibridge[] = {
402 /* Processor Home Agent */
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300403 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) },
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300404
405 /* Memory controller */
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300406 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) },
407 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) },
408 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) },
409 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) },
410 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) },
411 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) },
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300412
413 /* System Address Decoder */
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300414 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) },
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300415
416 /* Broadcast Registers */
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300417 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) },
418 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) },
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300419
420 /* Optional, mode 2HA */
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300421 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) },
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300422#if 0
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300423 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) },
424 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300425#endif
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300426 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) },
427 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) },
Tony Luck7d375bf2015-05-18 17:50:42 -0300428 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1) },
429 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1) },
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300430
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300431 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) },
432 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) },
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300433};
434
435static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
436 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
437 {0,} /* 0 terminated list. */
438};
439
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300440/* Haswell support */
441/* EN processor:
442 * - 1 IMC
443 * - 3 DDR3 channels, 2 DPC per channel
444 * EP processor:
445 * - 1 or 2 IMC
446 * - 4 DDR4 channels, 3 DPC per channel
447 * EP 4S processor:
448 * - 2 IMC
449 * - 4 DDR4 channels, 3 DPC per channel
450 * EX processor:
451 * - 2 IMC
452 * - each IMC interfaces with a SMI 2 channel
453 * - each SMI channel interfaces with a scalable memory buffer
454 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
455 */
Tony Luck1f395812014-12-02 09:27:30 -0800456#define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300457#define HASWELL_HASYSDEFEATURE2 0x84
458#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
459#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
460#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
461#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
462#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
463#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
464#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
465#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
466#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
467#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
468#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
469#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
470#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
471#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
472#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
473#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
474#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
475#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
Aristeu Rozanski71793852015-06-12 09:44:52 -0400476#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
477#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
478#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300479static const struct pci_id_descr pci_dev_descr_haswell[] = {
480 /* first item must be the HA */
481 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) },
482
483 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) },
484 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) },
485
486 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) },
487
488 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) },
489 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) },
490 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) },
491 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) },
492 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) },
493 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) },
494
495 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) },
Aristeu Rozanski71793852015-06-12 09:44:52 -0400496 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1) },
497 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1) },
498 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1) },
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300499
500 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) },
501 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) },
502 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) },
503 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) },
504 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) },
505 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) },
506};
507
508static const struct pci_id_table pci_dev_descr_haswell_table[] = {
509 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
510 {0,} /* 0 terminated list. */
511};
512
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200513/*
Tony Luck1f395812014-12-02 09:27:30 -0800514 * Broadwell support
515 *
516 * DE processor:
517 * - 1 IMC
518 * - 2 DDR3 channels, 2 DPC per channel
Tony Luckfa2ce642015-05-20 19:10:35 -0300519 * EP processor:
520 * - 1 or 2 IMC
521 * - 4 DDR4 channels, 3 DPC per channel
522 * EP 4S processor:
523 * - 2 IMC
524 * - 4 DDR4 channels, 3 DPC per channel
525 * EX processor:
526 * - 2 IMC
527 * - each IMC interfaces with a SMI 2 channel
528 * - each SMI channel interfaces with a scalable memory buffer
529 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
Tony Luck1f395812014-12-02 09:27:30 -0800530 */
531#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
532#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
Tony Luckfa2ce642015-05-20 19:10:35 -0300533#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60
Tony Luck1f395812014-12-02 09:27:30 -0800534#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
535#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
Tony Luckfa2ce642015-05-20 19:10:35 -0300536#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68
537#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79
Tony Luck1f395812014-12-02 09:27:30 -0800538#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
539#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
540#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
541#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
542#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
543#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
Tony Luckfa2ce642015-05-20 19:10:35 -0300544#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
545#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
546#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
547#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
Tony Luck1f395812014-12-02 09:27:30 -0800548#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
549
550static const struct pci_id_descr pci_dev_descr_broadwell[] = {
551 /* first item must be the HA */
552 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) },
553
554 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) },
555 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) },
556
Tony Luckfa2ce642015-05-20 19:10:35 -0300557 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1) },
558
Tony Luck1f395812014-12-02 09:27:30 -0800559 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) },
560 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) },
561 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) },
562 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) },
Tony Luckfa2ce642015-05-20 19:10:35 -0300563 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1) },
564 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1) },
565
Tony Luck1f395812014-12-02 09:27:30 -0800566 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) },
Tony Luckfa2ce642015-05-20 19:10:35 -0300567
568 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1) },
569 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1) },
570 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1) },
571 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1) },
572 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1) },
573 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1) },
Tony Luck1f395812014-12-02 09:27:30 -0800574};
575
576static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
577 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
578 {0,} /* 0 terminated list. */
579};
580
581/*
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200582 * pci_device_id table for which devices we are looking for
583 */
Jingoo Hanba935f42013-12-06 10:23:08 +0100584static const struct pci_device_id sbridge_pci_tbl[] = {
Andy Lutomirskid0585cd2014-08-14 14:45:41 -0700585 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300586 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300587 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
Tony Luck1f395812014-12-02 09:27:30 -0800588 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)},
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200589 {0,} /* 0 terminated list. */
590};
591
592
593/****************************************************************************
David Mackey15ed1032012-04-17 11:30:52 -0700594 Ancillary status routines
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200595 ****************************************************************************/
596
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300597static inline int numrank(enum type type, u32 mtr)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200598{
599 int ranks = (1 << RANK_CNT_BITS(mtr));
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300600 int max = 4;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200601
Tony Luckfa2ce642015-05-20 19:10:35 -0300602 if (type == HASWELL || type == BROADWELL)
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300603 max = 8;
604
605 if (ranks > max) {
606 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
607 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200608 return -EINVAL;
609 }
610
611 return ranks;
612}
613
614static inline int numrow(u32 mtr)
615{
616 int rows = (RANK_WIDTH_BITS(mtr) + 12);
617
618 if (rows < 13 || rows > 18) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300619 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
620 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200621 return -EINVAL;
622 }
623
624 return 1 << rows;
625}
626
627static inline int numcol(u32 mtr)
628{
629 int cols = (COL_WIDTH_BITS(mtr) + 10);
630
631 if (cols > 12) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300632 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
633 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200634 return -EINVAL;
635 }
636
637 return 1 << cols;
638}
639
Jim Snowc1979ba2015-12-03 10:48:53 +0100640static struct sbridge_dev *get_sbridge_dev(u8 bus, int multi_bus)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200641{
642 struct sbridge_dev *sbridge_dev;
643
Jim Snowc1979ba2015-12-03 10:48:53 +0100644 /*
645 * If we have devices scattered across several busses that pertain
646 * to the same memory controller, we'll lump them all together.
647 */
648 if (multi_bus) {
649 return list_first_entry_or_null(&sbridge_edac_list,
650 struct sbridge_dev, list);
651 }
652
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200653 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
654 if (sbridge_dev->bus == bus)
655 return sbridge_dev;
656 }
657
658 return NULL;
659}
660
661static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
662 const struct pci_id_table *table)
663{
664 struct sbridge_dev *sbridge_dev;
665
666 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
667 if (!sbridge_dev)
668 return NULL;
669
670 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
671 GFP_KERNEL);
672 if (!sbridge_dev->pdev) {
673 kfree(sbridge_dev);
674 return NULL;
675 }
676
677 sbridge_dev->bus = bus;
678 sbridge_dev->n_devs = table->n_devs;
679 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
680
681 return sbridge_dev;
682}
683
684static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
685{
686 list_del(&sbridge_dev->list);
687 kfree(sbridge_dev->pdev);
688 kfree(sbridge_dev);
689}
690
Aristeu Rozanskifb79a502013-10-30 13:26:57 -0300691static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
692{
693 u32 reg;
694
695 /* Address range is 32:28 */
696 pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
697 return GET_TOLM(reg);
698}
699
Aristeu Rozanski8fd6a432013-10-30 13:26:59 -0300700static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
701{
702 u32 reg;
703
704 pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
705 return GET_TOHM(reg);
706}
707
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300708static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
709{
710 u32 reg;
711
712 pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
713
714 return GET_TOLM(reg);
715}
716
717static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
718{
719 u32 reg;
720
721 pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
722
723 return GET_TOHM(reg);
724}
725
Aristeu Rozanskib976bcf2014-06-02 15:15:24 -0300726static u64 rir_limit(u32 reg)
727{
728 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
729}
730
Jim Snowc59f9c02015-12-03 10:48:52 +0100731static u64 sad_limit(u32 reg)
732{
733 return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
734}
735
736static u32 interleave_mode(u32 reg)
737{
738 return GET_BITFIELD(reg, 1, 1);
739}
740
741char *show_interleave_mode(u32 reg)
742{
743 return interleave_mode(reg) ? "8:6" : "[8:6]XOR[18:16]";
744}
745
746static u32 dram_attr(u32 reg)
747{
748 return GET_BITFIELD(reg, 2, 3);
749}
750
Aristeu Rozanski9e375442014-06-02 15:15:22 -0300751static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
752{
753 u32 reg;
754 enum mem_type mtype;
755
756 if (pvt->pci_ddrio) {
757 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
758 &reg);
759 if (GET_BITFIELD(reg, 11, 11))
760 /* FIXME: Can also be LRDIMM */
761 mtype = MEM_RDDR3;
762 else
763 mtype = MEM_DDR3;
764 } else
765 mtype = MEM_UNKNOWN;
766
767 return mtype;
768}
769
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300770static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
771{
772 u32 reg;
773 bool registered = false;
774 enum mem_type mtype = MEM_UNKNOWN;
775
776 if (!pvt->pci_ddrio)
777 goto out;
778
779 pci_read_config_dword(pvt->pci_ddrio,
780 HASWELL_DDRCRCLKCONTROLS, &reg);
781 /* Is_Rdimm */
782 if (GET_BITFIELD(reg, 16, 16))
783 registered = true;
784
785 pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
786 if (GET_BITFIELD(reg, 14, 14)) {
787 if (registered)
788 mtype = MEM_RDDR4;
789 else
790 mtype = MEM_DDR4;
791 } else {
792 if (registered)
793 mtype = MEM_RDDR3;
794 else
795 mtype = MEM_DDR3;
796 }
797
798out:
799 return mtype;
800}
801
Aristeu Rozanski12f07212015-06-12 15:08:17 -0400802static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
803{
804 /* there's no way to figure out */
805 return DEV_UNKNOWN;
806}
807
808static enum dev_type __ibridge_get_width(u32 mtr)
809{
810 enum dev_type type;
811
812 switch (mtr) {
813 case 3:
814 type = DEV_UNKNOWN;
815 break;
816 case 2:
817 type = DEV_X16;
818 break;
819 case 1:
820 type = DEV_X8;
821 break;
822 case 0:
823 type = DEV_X4;
824 break;
825 }
826
827 return type;
828}
829
830static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
831{
832 /*
833 * ddr3_width on the documentation but also valid for DDR4 on
834 * Haswell
835 */
836 return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
837}
838
839static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
840{
841 /* ddr3_width on the documentation but also valid for DDR4 */
842 return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
843}
844
Aristeu Rozanskif14d6892014-06-02 15:15:23 -0300845static u8 get_node_id(struct sbridge_pvt *pvt)
846{
847 u32 reg;
848 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
849 return GET_BITFIELD(reg, 0, 2);
850}
851
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300852static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
853{
854 u32 reg;
855
856 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
857 return GET_BITFIELD(reg, 0, 3);
858}
859
860static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
861{
862 u32 reg;
863
Tony Luckf7cf2a22014-10-29 10:36:50 -0700864 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
865 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300866}
867
868static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
869{
870 u64 rc;
871 u32 reg;
872
873 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
874 rc = GET_BITFIELD(reg, 26, 31);
875 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
876 rc = ((reg << 6) | rc) << 26;
877
878 return rc | 0x1ffffff;
879}
880
881static u64 haswell_rir_limit(u32 reg)
882{
883 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
884}
885
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300886static inline u8 sad_pkg_socket(u8 pkg)
887{
888 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
Aristeu Rozanski2ff3a302014-06-02 15:15:27 -0300889 return ((pkg >> 3) << 2) | (pkg & 0x3);
Aristeu Rozanski4d715a82013-10-30 13:27:06 -0300890}
891
892static inline u8 sad_pkg_ha(u8 pkg)
893{
894 return (pkg >> 2) & 0x1;
895}
896
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200897/****************************************************************************
898 Memory check routines
899 ****************************************************************************/
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300900static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200901{
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300902 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200903
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300904 do {
905 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
906 if (pdev && pdev->bus->number == bus)
907 break;
908 } while (pdev);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200909
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300910 return pdev;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200911}
912
913/**
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -0300914 * check_if_ecc_is_active() - Checks if ECC is active
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300915 * @bus: Device bus
916 * @type: Memory controller type
917 * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
918 * disabled
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200919 */
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300920static int check_if_ecc_is_active(const u8 bus, enum type type)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200921{
922 struct pci_dev *pdev = NULL;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300923 u32 mcmtr, id;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200924
Tony Luck1f395812014-12-02 09:27:30 -0800925 switch (type) {
926 case IVY_BRIDGE:
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300927 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
Tony Luck1f395812014-12-02 09:27:30 -0800928 break;
929 case HASWELL:
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300930 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
Tony Luck1f395812014-12-02 09:27:30 -0800931 break;
932 case SANDY_BRIDGE:
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300933 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
Tony Luck1f395812014-12-02 09:27:30 -0800934 break;
935 case BROADWELL:
936 id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
937 break;
938 default:
939 return -ENODEV;
940 }
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300941
942 pdev = get_pdev_same_bus(bus, id);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200943 if (!pdev) {
944 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -0300945 "%04x:%04x! on bus %02d\n",
946 PCI_VENDOR_ID_INTEL, id, bus);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200947 return -ENODEV;
948 }
949
950 pci_read_config_dword(pdev, MCMTR, &mcmtr);
951 if (!IS_ECC_ENABLED(mcmtr)) {
952 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
953 return -ENODEV;
954 }
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200955 return 0;
956}
957
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300958static int get_dimm_config(struct mem_ctl_info *mci)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200959{
960 struct sbridge_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -0300961 struct dimm_info *dimm;
Mauro Carvalho Chehabdeb09dd2012-09-20 12:09:30 -0300962 unsigned i, j, banks, ranks, rows, cols, npages;
963 u64 size;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200964 u32 reg;
965 enum edac_type mode;
Mark A. Grondonac6e13b52011-10-18 11:02:58 -0200966 enum mem_type mtype;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200967
Tony Luck1f395812014-12-02 09:27:30 -0800968 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL)
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300969 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
970 else
971 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
972
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200973 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
974
Aristeu Rozanskif14d6892014-06-02 15:15:23 -0300975 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
Joe Perches956b9ba2012-04-29 17:08:39 -0300976 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
977 pvt->sbridge_dev->mc,
978 pvt->sbridge_dev->node_id,
979 pvt->sbridge_dev->source_id);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200980
981 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
982 if (IS_MIRROR_ENABLED(reg)) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300983 edac_dbg(0, "Memory mirror is enabled\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200984 pvt->is_mirrored = true;
985 } else {
Joe Perches956b9ba2012-04-29 17:08:39 -0300986 edac_dbg(0, "Memory mirror is disabled\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200987 pvt->is_mirrored = false;
988 }
989
990 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
991 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300992 edac_dbg(0, "Lockstep is enabled\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200993 mode = EDAC_S8ECD8ED;
994 pvt->is_lockstep = true;
995 } else {
Joe Perches956b9ba2012-04-29 17:08:39 -0300996 edac_dbg(0, "Lockstep is disabled\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -0200997 mode = EDAC_S4ECD4ED;
998 pvt->is_lockstep = false;
999 }
1000 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
Joe Perches956b9ba2012-04-29 17:08:39 -03001001 edac_dbg(0, "address map is on closed page mode\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001002 pvt->is_close_pg = true;
1003 } else {
Joe Perches956b9ba2012-04-29 17:08:39 -03001004 edac_dbg(0, "address map is on open page mode\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001005 pvt->is_close_pg = false;
1006 }
1007
Aristeu Rozanski9e375442014-06-02 15:15:22 -03001008 mtype = pvt->info.get_memory_type(pvt);
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001009 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
Aristeu Rozanski9e375442014-06-02 15:15:22 -03001010 edac_dbg(0, "Memory is registered\n");
1011 else if (mtype == MEM_UNKNOWN)
Luck, Tonyde4772c2013-03-28 09:59:15 -07001012 edac_dbg(0, "Cannot determine memory type\n");
Aristeu Rozanski9e375442014-06-02 15:15:22 -03001013 else
1014 edac_dbg(0, "Memory is unregistered\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001015
Tony Luckfec53af2014-12-02 09:41:58 -08001016 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001017 banks = 16;
1018 else
1019 banks = 8;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001020
1021 for (i = 0; i < NUM_CHANNELS; i++) {
1022 u32 mtr;
1023
Tony Luck7d375bf2015-05-18 17:50:42 -03001024 if (!pvt->pci_tad[i])
1025 continue;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001026 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03001027 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
1028 i, j, 0);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001029 pci_read_config_dword(pvt->pci_tad[i],
1030 mtr_regs[j], &mtr);
Joe Perches956b9ba2012-04-29 17:08:39 -03001031 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001032 if (IS_DIMM_PRESENT(mtr)) {
1033 pvt->channel[i].dimms++;
1034
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001035 ranks = numrank(pvt->info.type, mtr);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001036 rows = numrow(mtr);
1037 cols = numcol(mtr);
1038
Mauro Carvalho Chehabdeb09dd2012-09-20 12:09:30 -03001039 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001040 npages = MiB_TO_PAGES(size);
1041
Tony Luck7d375bf2015-05-18 17:50:42 -03001042 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1043 pvt->sbridge_dev->mc, i/4, i%4, j,
Joe Perches956b9ba2012-04-29 17:08:39 -03001044 size, npages,
1045 banks, ranks, rows, cols);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001046
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -03001047 dimm->nr_pages = npages;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -03001048 dimm->grain = 32;
Aristeu Rozanski12f07212015-06-12 15:08:17 -04001049 dimm->dtype = pvt->info.get_width(pvt, mtr);
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -03001050 dimm->mtype = mtype;
1051 dimm->edac_mode = mode;
1052 snprintf(dimm->label, sizeof(dimm->label),
Tony Luck7d375bf2015-05-18 17:50:42 -03001053 "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1054 pvt->sbridge_dev->source_id, i/4, i%4, j);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001055 }
1056 }
1057 }
1058
1059 return 0;
1060}
1061
1062static void get_memory_layout(const struct mem_ctl_info *mci)
1063{
1064 struct sbridge_pvt *pvt = mci->pvt_info;
1065 int i, j, k, n_sads, n_tads, sad_interl;
1066 u32 reg;
1067 u64 limit, prv = 0;
1068 u64 tmp_mb;
Jim Snow8c009102014-11-18 14:51:09 +01001069 u32 gb, mb;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001070 u32 rir_way;
1071
1072 /*
1073 * Step 1) Get TOLM/TOHM ranges
1074 */
1075
Aristeu Rozanskifb79a502013-10-30 13:26:57 -03001076 pvt->tolm = pvt->info.get_tolm(pvt);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001077 tmp_mb = (1 + pvt->tolm) >> 20;
1078
Jim Snow8c009102014-11-18 14:51:09 +01001079 gb = div_u64_rem(tmp_mb, 1024, &mb);
1080 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1081 gb, (mb*1000)/1024, (u64)pvt->tolm);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001082
1083 /* Address range is already 45:25 */
Aristeu Rozanski8fd6a432013-10-30 13:26:59 -03001084 pvt->tohm = pvt->info.get_tohm(pvt);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001085 tmp_mb = (1 + pvt->tohm) >> 20;
1086
Jim Snow8c009102014-11-18 14:51:09 +01001087 gb = div_u64_rem(tmp_mb, 1024, &mb);
1088 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1089 gb, (mb*1000)/1024, (u64)pvt->tohm);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001090
1091 /*
1092 * Step 2) Get SAD range and SAD Interleave list
1093 * TAD registers contain the interleave wayness. However, it
1094 * seems simpler to just discover it indirectly, with the
1095 * algorithm bellow.
1096 */
1097 prv = 0;
Aristeu Rozanski464f1d82013-10-30 13:27:00 -03001098 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001099 /* SAD_LIMIT Address range is 45:26 */
Aristeu Rozanski464f1d82013-10-30 13:27:00 -03001100 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001101 &reg);
Jim Snowc59f9c02015-12-03 10:48:52 +01001102 limit = pvt->info.sad_limit(reg);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001103
1104 if (!DRAM_RULE_ENABLE(reg))
1105 continue;
1106
1107 if (limit <= prv)
1108 break;
1109
1110 tmp_mb = (limit + 1) >> 20;
Jim Snow8c009102014-11-18 14:51:09 +01001111 gb = div_u64_rem(tmp_mb, 1024, &mb);
Joe Perches956b9ba2012-04-29 17:08:39 -03001112 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1113 n_sads,
Jim Snowc59f9c02015-12-03 10:48:52 +01001114 show_dram_attr(pvt->info.dram_attr(reg)),
Jim Snow8c009102014-11-18 14:51:09 +01001115 gb, (mb*1000)/1024,
Joe Perches956b9ba2012-04-29 17:08:39 -03001116 ((u64)tmp_mb) << 20L,
Jim Snowc59f9c02015-12-03 10:48:52 +01001117 pvt->info.show_interleave_mode(reg),
Joe Perches956b9ba2012-04-29 17:08:39 -03001118 reg);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001119 prv = limit;
1120
Aristeu Rozanskief1ce512013-10-30 13:27:01 -03001121 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001122 &reg);
Aristeu Rozanskicc311992013-10-30 13:27:02 -03001123 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001124 for (j = 0; j < 8; j++) {
Aristeu Rozanskicc311992013-10-30 13:27:02 -03001125 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1126 if (j > 0 && sad_interl == pkg)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001127 break;
1128
Joe Perches956b9ba2012-04-29 17:08:39 -03001129 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
Aristeu Rozanskicc311992013-10-30 13:27:02 -03001130 n_sads, j, pkg);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001131 }
1132 }
1133
1134 /*
1135 * Step 3) Get TAD range
1136 */
1137 prv = 0;
1138 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1139 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1140 &reg);
1141 limit = TAD_LIMIT(reg);
1142 if (limit <= prv)
1143 break;
1144 tmp_mb = (limit + 1) >> 20;
1145
Jim Snow8c009102014-11-18 14:51:09 +01001146 gb = div_u64_rem(tmp_mb, 1024, &mb);
Joe Perches956b9ba2012-04-29 17:08:39 -03001147 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
Jim Snow8c009102014-11-18 14:51:09 +01001148 n_tads, gb, (mb*1000)/1024,
Joe Perches956b9ba2012-04-29 17:08:39 -03001149 ((u64)tmp_mb) << 20L,
1150 (u32)TAD_SOCK(reg),
1151 (u32)TAD_CH(reg),
1152 (u32)TAD_TGT0(reg),
1153 (u32)TAD_TGT1(reg),
1154 (u32)TAD_TGT2(reg),
1155 (u32)TAD_TGT3(reg),
1156 reg);
Hui Wang7fae0db2012-02-06 04:11:01 -03001157 prv = limit;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001158 }
1159
1160 /*
1161 * Step 4) Get TAD offsets, per each channel
1162 */
1163 for (i = 0; i < NUM_CHANNELS; i++) {
1164 if (!pvt->channel[i].dimms)
1165 continue;
1166 for (j = 0; j < n_tads; j++) {
1167 pci_read_config_dword(pvt->pci_tad[i],
1168 tad_ch_nilv_offset[j],
1169 &reg);
1170 tmp_mb = TAD_OFFSET(reg) >> 20;
Jim Snow8c009102014-11-18 14:51:09 +01001171 gb = div_u64_rem(tmp_mb, 1024, &mb);
Joe Perches956b9ba2012-04-29 17:08:39 -03001172 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1173 i, j,
Jim Snow8c009102014-11-18 14:51:09 +01001174 gb, (mb*1000)/1024,
Joe Perches956b9ba2012-04-29 17:08:39 -03001175 ((u64)tmp_mb) << 20L,
1176 reg);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001177 }
1178 }
1179
1180 /*
1181 * Step 6) Get RIR Wayness/Limit, per each channel
1182 */
1183 for (i = 0; i < NUM_CHANNELS; i++) {
1184 if (!pvt->channel[i].dimms)
1185 continue;
1186 for (j = 0; j < MAX_RIR_RANGES; j++) {
1187 pci_read_config_dword(pvt->pci_tad[i],
1188 rir_way_limit[j],
1189 &reg);
1190
1191 if (!IS_RIR_VALID(reg))
1192 continue;
1193
Aristeu Rozanskib976bcf2014-06-02 15:15:24 -03001194 tmp_mb = pvt->info.rir_limit(reg) >> 20;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001195 rir_way = 1 << RIR_WAY(reg);
Jim Snow8c009102014-11-18 14:51:09 +01001196 gb = div_u64_rem(tmp_mb, 1024, &mb);
Joe Perches956b9ba2012-04-29 17:08:39 -03001197 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1198 i, j,
Jim Snow8c009102014-11-18 14:51:09 +01001199 gb, (mb*1000)/1024,
Joe Perches956b9ba2012-04-29 17:08:39 -03001200 ((u64)tmp_mb) << 20L,
1201 rir_way,
1202 reg);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001203
1204 for (k = 0; k < rir_way; k++) {
1205 pci_read_config_dword(pvt->pci_tad[i],
1206 rir_offset[j][k],
1207 &reg);
1208 tmp_mb = RIR_OFFSET(reg) << 6;
1209
Jim Snow8c009102014-11-18 14:51:09 +01001210 gb = div_u64_rem(tmp_mb, 1024, &mb);
Joe Perches956b9ba2012-04-29 17:08:39 -03001211 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1212 i, j, k,
Jim Snow8c009102014-11-18 14:51:09 +01001213 gb, (mb*1000)/1024,
Joe Perches956b9ba2012-04-29 17:08:39 -03001214 ((u64)tmp_mb) << 20L,
1215 (u32)RIR_RNK_TGT(reg),
1216 reg);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001217 }
1218 }
1219 }
1220}
1221
Rashika Kheria8112c0c2013-12-14 19:32:09 +05301222static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001223{
1224 struct sbridge_dev *sbridge_dev;
1225
1226 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1227 if (sbridge_dev->node_id == node_id)
1228 return sbridge_dev->mci;
1229 }
1230 return NULL;
1231}
1232
1233static int get_memory_error_data(struct mem_ctl_info *mci,
1234 u64 addr,
Tony Luck7d375bf2015-05-18 17:50:42 -03001235 u8 *socket, u8 *ha,
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001236 long *channel_mask,
1237 u8 *rank,
Mauro Carvalho Chehabe17a2f42a2012-05-11 11:41:45 -03001238 char **area_type, char *msg)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001239{
1240 struct mem_ctl_info *new_mci;
1241 struct sbridge_pvt *pvt = mci->pvt_info;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001242 struct pci_dev *pci_ha;
Mauro Carvalho Chehabc41afdc2014-06-26 15:35:14 -03001243 int n_rir, n_sads, n_tads, sad_way, sck_xch;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001244 int sad_interl, idx, base_ch;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001245 int interleave_mode, shiftup = 0;
Aristeu Rozanskief1ce512013-10-30 13:27:01 -03001246 unsigned sad_interleave[pvt->info.max_interleave];
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001247 u32 reg, dram_rule;
Tony Luck7d375bf2015-05-18 17:50:42 -03001248 u8 ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001249 u32 tad_offset;
1250 u32 rir_way;
Jim Snow8c009102014-11-18 14:51:09 +01001251 u32 mb, gb;
Aristeu Rozanskibd4b9682013-11-21 09:08:03 -05001252 u64 ch_addr, offset, limit = 0, prv = 0;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001253
1254
1255 /*
1256 * Step 0) Check if the address is at special memory ranges
1257 * The check bellow is probably enough to fill all cases where
1258 * the error is not inside a memory, except for the legacy
1259 * range (e. g. VGA addresses). It is unlikely, however, that the
1260 * memory controller would generate an error on that range.
1261 */
Mauro Carvalho Chehab5b889e32011-11-07 18:26:53 -03001262 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001263 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001264 return -EINVAL;
1265 }
1266 if (addr >= (u64)pvt->tohm) {
1267 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001268 return -EINVAL;
1269 }
1270
1271 /*
1272 * Step 1) Get socket
1273 */
Aristeu Rozanski464f1d82013-10-30 13:27:00 -03001274 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1275 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001276 &reg);
1277
1278 if (!DRAM_RULE_ENABLE(reg))
1279 continue;
1280
Jim Snowc59f9c02015-12-03 10:48:52 +01001281 limit = pvt->info.sad_limit(reg);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001282 if (limit <= prv) {
1283 sprintf(msg, "Can't discover the memory socket");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001284 return -EINVAL;
1285 }
1286 if (addr <= limit)
1287 break;
1288 prv = limit;
1289 }
Aristeu Rozanski464f1d82013-10-30 13:27:00 -03001290 if (n_sads == pvt->info.max_sad) {
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001291 sprintf(msg, "Can't discover the memory socket");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001292 return -EINVAL;
1293 }
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001294 dram_rule = reg;
Jim Snowc59f9c02015-12-03 10:48:52 +01001295 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1296 interleave_mode = pvt->info.interleave_mode(dram_rule);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001297
Aristeu Rozanskief1ce512013-10-30 13:27:01 -03001298 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001299 &reg);
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001300
1301 if (pvt->info.type == SANDY_BRIDGE) {
1302 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1303 for (sad_way = 0; sad_way < 8; sad_way++) {
1304 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1305 if (sad_way > 0 && sad_interl == pkg)
1306 break;
1307 sad_interleave[sad_way] = pkg;
1308 edac_dbg(0, "SAD interleave #%d: %d\n",
1309 sad_way, sad_interleave[sad_way]);
1310 }
1311 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
1312 pvt->sbridge_dev->mc,
1313 n_sads,
1314 addr,
1315 limit,
1316 sad_way + 7,
1317 !interleave_mode ? "" : "XOR[18:16]");
1318 if (interleave_mode)
1319 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
1320 else
1321 idx = (addr >> 6) & 7;
1322 switch (sad_way) {
1323 case 1:
1324 idx = 0;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001325 break;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001326 case 2:
1327 idx = idx & 1;
1328 break;
1329 case 4:
1330 idx = idx & 3;
1331 break;
1332 case 8:
1333 break;
1334 default:
1335 sprintf(msg, "Can't discover socket interleave");
1336 return -EINVAL;
1337 }
1338 *socket = sad_interleave[idx];
1339 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
1340 idx, sad_way, *socket);
Tony Luck1f395812014-12-02 09:27:30 -08001341 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001342 int bits, a7mode = A7MODE(dram_rule);
1343
1344 if (a7mode) {
1345 /* A7 mode swaps P9 with P6 */
1346 bits = GET_BITFIELD(addr, 7, 8) << 1;
1347 bits |= GET_BITFIELD(addr, 9, 9);
1348 } else
Tony Luckbb89e712015-05-18 17:39:06 -03001349 bits = GET_BITFIELD(addr, 6, 8);
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001350
Tony Luckbb89e712015-05-18 17:39:06 -03001351 if (interleave_mode == 0) {
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001352 /* interleave mode will XOR {8,7,6} with {18,17,16} */
1353 idx = GET_BITFIELD(addr, 16, 18);
1354 idx ^= bits;
1355 } else
1356 idx = bits;
1357
1358 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1359 *socket = sad_pkg_socket(pkg);
1360 sad_ha = sad_pkg_ha(pkg);
Tony Luck7d375bf2015-05-18 17:50:42 -03001361 if (sad_ha)
1362 ch_add = 4;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001363
1364 if (a7mode) {
1365 /* MCChanShiftUpEnable */
1366 pci_read_config_dword(pvt->pci_ha0,
1367 HASWELL_HASYSDEFEATURE2, &reg);
1368 shiftup = GET_BITFIELD(reg, 22, 22);
1369 }
1370
1371 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
1372 idx, *socket, sad_ha, shiftup);
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001373 } else {
1374 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001375 idx = (addr >> 6) & 7;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001376 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
1377 *socket = sad_pkg_socket(pkg);
1378 sad_ha = sad_pkg_ha(pkg);
Tony Luck7d375bf2015-05-18 17:50:42 -03001379 if (sad_ha)
1380 ch_add = 4;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001381 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
1382 idx, *socket, sad_ha);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001383 }
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001384
Tony Luck7d375bf2015-05-18 17:50:42 -03001385 *ha = sad_ha;
1386
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001387 /*
1388 * Move to the proper node structure, in order to access the
1389 * right PCI registers
1390 */
1391 new_mci = get_mci_for_node_id(*socket);
1392 if (!new_mci) {
1393 sprintf(msg, "Struct for socket #%u wasn't initialized",
1394 *socket);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001395 return -EINVAL;
1396 }
1397 mci = new_mci;
1398 pvt = mci->pvt_info;
1399
1400 /*
1401 * Step 2) Get memory channel
1402 */
1403 prv = 0;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001404 if (pvt->info.type == SANDY_BRIDGE)
1405 pci_ha = pvt->pci_ha0;
1406 else {
1407 if (sad_ha)
1408 pci_ha = pvt->pci_ha1;
1409 else
1410 pci_ha = pvt->pci_ha0;
1411 }
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001412 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001413 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001414 limit = TAD_LIMIT(reg);
1415 if (limit <= prv) {
1416 sprintf(msg, "Can't discover the memory channel");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001417 return -EINVAL;
1418 }
1419 if (addr <= limit)
1420 break;
1421 prv = limit;
1422 }
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001423 if (n_tads == MAX_TAD) {
1424 sprintf(msg, "Can't discover the memory channel");
1425 return -EINVAL;
1426 }
1427
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001428 ch_way = TAD_CH(reg) + 1;
1429 sck_way = TAD_SOCK(reg) + 1;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001430
1431 if (ch_way == 3)
1432 idx = addr >> 6;
1433 else
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001434 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001435 idx = idx % ch_way;
1436
1437 /*
1438 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
1439 */
1440 switch (idx) {
1441 case 0:
1442 base_ch = TAD_TGT0(reg);
1443 break;
1444 case 1:
1445 base_ch = TAD_TGT1(reg);
1446 break;
1447 case 2:
1448 base_ch = TAD_TGT2(reg);
1449 break;
1450 case 3:
1451 base_ch = TAD_TGT3(reg);
1452 break;
1453 default:
1454 sprintf(msg, "Can't discover the TAD target");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001455 return -EINVAL;
1456 }
1457 *channel_mask = 1 << base_ch;
1458
Tony Luck7d375bf2015-05-18 17:50:42 -03001459 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001460 tad_ch_nilv_offset[n_tads],
1461 &tad_offset);
1462
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001463 if (pvt->is_mirrored) {
1464 *channel_mask |= 1 << ((base_ch + 2) % 4);
1465 switch(ch_way) {
1466 case 2:
1467 case 4:
1468 sck_xch = 1 << sck_way * (ch_way >> 1);
1469 break;
1470 default:
1471 sprintf(msg, "Invalid mirror set. Can't decode addr");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001472 return -EINVAL;
1473 }
1474 } else
1475 sck_xch = (1 << sck_way) * ch_way;
1476
1477 if (pvt->is_lockstep)
1478 *channel_mask |= 1 << ((base_ch + 1) % 4);
1479
1480 offset = TAD_OFFSET(tad_offset);
1481
Joe Perches956b9ba2012-04-29 17:08:39 -03001482 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1483 n_tads,
1484 addr,
1485 limit,
1486 (u32)TAD_SOCK(reg),
1487 ch_way,
1488 offset,
1489 idx,
1490 base_ch,
1491 *channel_mask);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001492
1493 /* Calculate channel address */
1494 /* Remove the TAD offset */
1495
1496 if (offset > addr) {
1497 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1498 offset, addr);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001499 return -EINVAL;
1500 }
1501 addr -= offset;
1502 /* Store the low bits [0:6] of the addr */
1503 ch_addr = addr & 0x7f;
1504 /* Remove socket wayness and remove 6 bits */
1505 addr >>= 6;
Mauro Carvalho Chehab5b889e32011-11-07 18:26:53 -03001506 addr = div_u64(addr, sck_xch);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001507#if 0
1508 /* Divide by channel way */
1509 addr = addr / ch_way;
1510#endif
1511 /* Recover the last 6 bits */
1512 ch_addr |= addr << 6;
1513
1514 /*
1515 * Step 3) Decode rank
1516 */
1517 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
Tony Luck7d375bf2015-05-18 17:50:42 -03001518 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001519 rir_way_limit[n_rir],
1520 &reg);
1521
1522 if (!IS_RIR_VALID(reg))
1523 continue;
1524
Aristeu Rozanskib976bcf2014-06-02 15:15:24 -03001525 limit = pvt->info.rir_limit(reg);
Jim Snow8c009102014-11-18 14:51:09 +01001526 gb = div_u64_rem(limit >> 20, 1024, &mb);
Joe Perches956b9ba2012-04-29 17:08:39 -03001527 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1528 n_rir,
Jim Snow8c009102014-11-18 14:51:09 +01001529 gb, (mb*1000)/1024,
Joe Perches956b9ba2012-04-29 17:08:39 -03001530 limit,
1531 1 << RIR_WAY(reg));
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001532 if (ch_addr <= limit)
1533 break;
1534 }
1535 if (n_rir == MAX_RIR_RANGES) {
1536 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1537 ch_addr);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001538 return -EINVAL;
1539 }
1540 rir_way = RIR_WAY(reg);
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001541
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001542 if (pvt->is_close_pg)
1543 idx = (ch_addr >> 6);
1544 else
1545 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1546 idx %= 1 << rir_way;
1547
Tony Luck7d375bf2015-05-18 17:50:42 -03001548 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001549 rir_offset[n_rir][idx],
1550 &reg);
1551 *rank = RIR_RNK_TGT(reg);
1552
Joe Perches956b9ba2012-04-29 17:08:39 -03001553 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1554 n_rir,
1555 ch_addr,
1556 limit,
1557 rir_way,
1558 idx);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001559
1560 return 0;
1561}
1562
1563/****************************************************************************
1564 Device initialization routines: put/get, init/exit
1565 ****************************************************************************/
1566
1567/*
1568 * sbridge_put_all_devices 'put' all the devices that we have
1569 * reserved via 'get'
1570 */
1571static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1572{
1573 int i;
1574
Joe Perches956b9ba2012-04-29 17:08:39 -03001575 edac_dbg(0, "\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001576 for (i = 0; i < sbridge_dev->n_devs; i++) {
1577 struct pci_dev *pdev = sbridge_dev->pdev[i];
1578 if (!pdev)
1579 continue;
Joe Perches956b9ba2012-04-29 17:08:39 -03001580 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1581 pdev->bus->number,
1582 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001583 pci_dev_put(pdev);
1584 }
1585}
1586
1587static void sbridge_put_all_devices(void)
1588{
1589 struct sbridge_dev *sbridge_dev, *tmp;
1590
1591 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1592 sbridge_put_devices(sbridge_dev);
1593 free_sbridge_dev(sbridge_dev);
1594 }
1595}
1596
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001597static int sbridge_get_onedevice(struct pci_dev **prev,
1598 u8 *num_mc,
1599 const struct pci_id_table *table,
Jim Snowc1979ba2015-12-03 10:48:53 +01001600 const unsigned devno,
1601 const int multi_bus)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001602{
1603 struct sbridge_dev *sbridge_dev;
1604 const struct pci_id_descr *dev_descr = &table->descr[devno];
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001605 struct pci_dev *pdev = NULL;
1606 u8 bus = 0;
1607
Jiang Liuec5a0b32014-02-17 13:10:23 +08001608 sbridge_printk(KERN_DEBUG,
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001609 "Seeking for: PCI ID %04x:%04x\n",
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001610 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1611
1612 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1613 dev_descr->dev_id, *prev);
1614
1615 if (!pdev) {
1616 if (*prev) {
1617 *prev = pdev;
1618 return 0;
1619 }
1620
1621 if (dev_descr->optional)
1622 return 0;
1623
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001624 /* if the HA wasn't found */
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001625 if (devno == 0)
1626 return -ENODEV;
1627
1628 sbridge_printk(KERN_INFO,
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001629 "Device not found: %04x:%04x\n",
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001630 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1631
1632 /* End of list, leave */
1633 return -ENODEV;
1634 }
1635 bus = pdev->bus->number;
1636
Jim Snowc1979ba2015-12-03 10:48:53 +01001637 sbridge_dev = get_sbridge_dev(bus, multi_bus);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001638 if (!sbridge_dev) {
1639 sbridge_dev = alloc_sbridge_dev(bus, table);
1640 if (!sbridge_dev) {
1641 pci_dev_put(pdev);
1642 return -ENOMEM;
1643 }
1644 (*num_mc)++;
1645 }
1646
1647 if (sbridge_dev->pdev[devno]) {
1648 sbridge_printk(KERN_ERR,
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001649 "Duplicated device for %04x:%04x\n",
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001650 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1651 pci_dev_put(pdev);
1652 return -ENODEV;
1653 }
1654
1655 sbridge_dev->pdev[devno] = pdev;
1656
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001657 /* Be sure that the device is enabled */
1658 if (unlikely(pci_enable_device(pdev) < 0)) {
1659 sbridge_printk(KERN_ERR,
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001660 "Couldn't enable %04x:%04x\n",
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001661 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1662 return -ENODEV;
1663 }
1664
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001665 edac_dbg(0, "Detected %04x:%04x\n",
Joe Perches956b9ba2012-04-29 17:08:39 -03001666 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001667
1668 /*
1669 * As stated on drivers/pci/search.c, the reference count for
1670 * @from is always decremented if it is not %NULL. So, as we need
1671 * to get all devices up to null, we need to do a get for the device
1672 */
1673 pci_dev_get(pdev);
1674
1675 *prev = pdev;
1676
1677 return 0;
1678}
1679
Aristeu Rozanski5153a0f2013-10-30 13:27:03 -03001680/*
1681 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001682 * devices we want to reference for this driver.
Aristeu Rozanski5153a0f2013-10-30 13:27:03 -03001683 * @num_mc: pointer to the memory controllers count, to be incremented in case
Mauro Carvalho Chehabc41afdc2014-06-26 15:35:14 -03001684 * of success.
Aristeu Rozanski5153a0f2013-10-30 13:27:03 -03001685 * @table: model specific table
Jim Snowc1979ba2015-12-03 10:48:53 +01001686 * @allow_dups: allow for multiple devices to exist with the same device id
1687 * (as implemented, this isn't expected to work correctly in the
1688 * multi-socket case).
1689 * @multi_bus: don't assume devices on different buses belong to different
1690 * memory controllers.
Aristeu Rozanski5153a0f2013-10-30 13:27:03 -03001691 *
1692 * returns 0 in case of success or error code
1693 */
Jim Snowc1979ba2015-12-03 10:48:53 +01001694static int sbridge_get_all_devices_full(u8 *num_mc,
1695 const struct pci_id_table *table,
1696 int allow_dups,
1697 int multi_bus)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001698{
1699 int i, rc;
1700 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001701
1702 while (table && table->descr) {
1703 for (i = 0; i < table->n_devs; i++) {
Jim Snowc1979ba2015-12-03 10:48:53 +01001704 if (!allow_dups || i == 0 ||
1705 table->descr[i].dev_id !=
1706 table->descr[i-1].dev_id) {
1707 pdev = NULL;
1708 }
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001709 do {
1710 rc = sbridge_get_onedevice(&pdev, num_mc,
Jim Snowc1979ba2015-12-03 10:48:53 +01001711 table, i, multi_bus);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001712 if (rc < 0) {
1713 if (i == 0) {
1714 i = table->n_devs;
1715 break;
1716 }
1717 sbridge_put_all_devices();
1718 return -ENODEV;
1719 }
Jim Snowc1979ba2015-12-03 10:48:53 +01001720 } while (pdev && !allow_dups);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001721 }
1722 table++;
1723 }
1724
1725 return 0;
1726}
1727
Jim Snowc1979ba2015-12-03 10:48:53 +01001728#define sbridge_get_all_devices(num_mc, table) \
1729 sbridge_get_all_devices_full(num_mc, table, 0, 0)
1730
Aristeu Rozanskiea779b52013-10-30 13:27:04 -03001731static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
1732 struct sbridge_dev *sbridge_dev)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001733{
1734 struct sbridge_pvt *pvt = mci->pvt_info;
1735 struct pci_dev *pdev;
Seth Jennings2900ea62015-08-05 13:16:01 -05001736 u8 saw_chan_mask = 0;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001737 int i;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001738
1739 for (i = 0; i < sbridge_dev->n_devs; i++) {
1740 pdev = sbridge_dev->pdev[i];
1741 if (!pdev)
1742 continue;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001743
1744 switch (pdev->device) {
1745 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
1746 pvt->pci_sad0 = pdev;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001747 break;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001748 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
1749 pvt->pci_sad1 = pdev;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001750 break;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001751 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
1752 pvt->pci_br0 = pdev;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001753 break;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001754 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
1755 pvt->pci_ha0 = pdev;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001756 break;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001757 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
1758 pvt->pci_ta = pdev;
1759 break;
1760 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
1761 pvt->pci_ras = pdev;
1762 break;
1763 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
1764 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
1765 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
1766 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
1767 {
1768 int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
1769 pvt->pci_tad[id] = pdev;
Seth Jennings2900ea62015-08-05 13:16:01 -05001770 saw_chan_mask |= 1 << id;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001771 }
1772 break;
1773 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
1774 pvt->pci_ddrio = pdev;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001775 break;
1776 default:
1777 goto error;
1778 }
1779
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001780 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
1781 pdev->vendor, pdev->device,
Joe Perches956b9ba2012-04-29 17:08:39 -03001782 sbridge_dev->bus,
Joe Perches956b9ba2012-04-29 17:08:39 -03001783 pdev);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001784 }
1785
1786 /* Check if everything were registered */
1787 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
Luck, Tonyde4772c2013-03-28 09:59:15 -07001788 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001789 goto enodev;
1790
Seth Jennings2900ea62015-08-05 13:16:01 -05001791 if (saw_chan_mask != 0x0f)
1792 goto enodev;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001793 return 0;
1794
1795enodev:
1796 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1797 return -ENODEV;
1798
1799error:
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001800 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
1801 PCI_VENDOR_ID_INTEL, pdev->device);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02001802 return -EINVAL;
1803}
1804
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001805static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
1806 struct sbridge_dev *sbridge_dev)
1807{
1808 struct sbridge_pvt *pvt = mci->pvt_info;
Tony Luck7d375bf2015-05-18 17:50:42 -03001809 struct pci_dev *pdev;
1810 u8 saw_chan_mask = 0;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001811 int i;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001812
1813 for (i = 0; i < sbridge_dev->n_devs; i++) {
1814 pdev = sbridge_dev->pdev[i];
1815 if (!pdev)
1816 continue;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001817
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001818 switch (pdev->device) {
1819 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
1820 pvt->pci_ha0 = pdev;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001821 break;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001822 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
1823 pvt->pci_ta = pdev;
1824 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
1825 pvt->pci_ras = pdev;
1826 break;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001827 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
1828 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
Tony Luck7d375bf2015-05-18 17:50:42 -03001829 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
1830 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001831 {
1832 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
1833 pvt->pci_tad[id] = pdev;
Tony Luck7d375bf2015-05-18 17:50:42 -03001834 saw_chan_mask |= 1 << id;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001835 }
1836 break;
1837 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
1838 pvt->pci_ddrio = pdev;
1839 break;
1840 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
Tony Luck7d375bf2015-05-18 17:50:42 -03001841 pvt->pci_ddrio = pdev;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001842 break;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001843 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
1844 pvt->pci_sad0 = pdev;
1845 break;
1846 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
1847 pvt->pci_br0 = pdev;
1848 break;
1849 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
1850 pvt->pci_br1 = pdev;
1851 break;
1852 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
1853 pvt->pci_ha1 = pdev;
1854 break;
1855 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
1856 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
Tony Luck7d375bf2015-05-18 17:50:42 -03001857 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
1858 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001859 {
Tony Luck7d375bf2015-05-18 17:50:42 -03001860 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001861 pvt->pci_tad[id] = pdev;
Tony Luck7d375bf2015-05-18 17:50:42 -03001862 saw_chan_mask |= 1 << id;
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001863 }
1864 break;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001865 default:
1866 goto error;
1867 }
1868
1869 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1870 sbridge_dev->bus,
1871 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1872 pdev);
1873 }
1874
1875 /* Check if everything were registered */
1876 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
1877 !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras ||
1878 !pvt->pci_ta)
1879 goto enodev;
1880
Tony Luck7d375bf2015-05-18 17:50:42 -03001881 if (saw_chan_mask != 0x0f && /* -EN */
1882 saw_chan_mask != 0x33 && /* -EP */
1883 saw_chan_mask != 0xff) /* -EX */
1884 goto enodev;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001885 return 0;
1886
1887enodev:
1888 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1889 return -ENODEV;
1890
1891error:
1892 sbridge_printk(KERN_ERR,
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03001893 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
1894 pdev->device);
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03001895 return -EINVAL;
1896}
1897
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001898static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
1899 struct sbridge_dev *sbridge_dev)
1900{
1901 struct sbridge_pvt *pvt = mci->pvt_info;
Tony Luck7d375bf2015-05-18 17:50:42 -03001902 struct pci_dev *pdev;
1903 u8 saw_chan_mask = 0;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001904 int i;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001905
1906 /* there's only one device per system; not tied to any bus */
1907 if (pvt->info.pci_vtd == NULL)
1908 /* result will be checked later */
1909 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
1910 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
1911 NULL);
1912
1913 for (i = 0; i < sbridge_dev->n_devs; i++) {
1914 pdev = sbridge_dev->pdev[i];
1915 if (!pdev)
1916 continue;
1917
1918 switch (pdev->device) {
1919 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
1920 pvt->pci_sad0 = pdev;
1921 break;
1922 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
1923 pvt->pci_sad1 = pdev;
1924 break;
1925 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
1926 pvt->pci_ha0 = pdev;
1927 break;
1928 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
1929 pvt->pci_ta = pdev;
1930 break;
1931 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
1932 pvt->pci_ras = pdev;
1933 break;
1934 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001935 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001936 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001937 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
Tony Luck7d375bf2015-05-18 17:50:42 -03001938 {
1939 int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0;
1940
1941 pvt->pci_tad[id] = pdev;
1942 saw_chan_mask |= 1 << id;
1943 }
1944 break;
1945 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
1946 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
1947 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
1948 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
1949 {
1950 int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4;
1951
1952 pvt->pci_tad[id] = pdev;
1953 saw_chan_mask |= 1 << id;
1954 }
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001955 break;
1956 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
Aristeu Rozanski71793852015-06-12 09:44:52 -04001957 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
1958 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
1959 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
1960 if (!pvt->pci_ddrio)
1961 pvt->pci_ddrio = pdev;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001962 break;
1963 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
1964 pvt->pci_ha1 = pdev;
1965 break;
1966 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
1967 pvt->pci_ha1_ta = pdev;
1968 break;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001969 default:
1970 break;
1971 }
1972
1973 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1974 sbridge_dev->bus,
1975 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1976 pdev);
1977 }
1978
1979 /* Check if everything were registered */
1980 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
1981 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
1982 goto enodev;
1983
Tony Luck7d375bf2015-05-18 17:50:42 -03001984 if (saw_chan_mask != 0x0f && /* -EN */
1985 saw_chan_mask != 0x33 && /* -EP */
1986 saw_chan_mask != 0xff) /* -EX */
1987 goto enodev;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03001988 return 0;
1989
1990enodev:
1991 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1992 return -ENODEV;
1993}
1994
Tony Luck1f395812014-12-02 09:27:30 -08001995static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
1996 struct sbridge_dev *sbridge_dev)
1997{
1998 struct sbridge_pvt *pvt = mci->pvt_info;
1999 struct pci_dev *pdev;
Tony Luckfa2ce642015-05-20 19:10:35 -03002000 u8 saw_chan_mask = 0;
Tony Luck1f395812014-12-02 09:27:30 -08002001 int i;
2002
2003 /* there's only one device per system; not tied to any bus */
2004 if (pvt->info.pci_vtd == NULL)
2005 /* result will be checked later */
2006 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2007 PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
2008 NULL);
2009
2010 for (i = 0; i < sbridge_dev->n_devs; i++) {
2011 pdev = sbridge_dev->pdev[i];
2012 if (!pdev)
2013 continue;
2014
2015 switch (pdev->device) {
2016 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
2017 pvt->pci_sad0 = pdev;
2018 break;
2019 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
2020 pvt->pci_sad1 = pdev;
2021 break;
2022 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2023 pvt->pci_ha0 = pdev;
2024 break;
2025 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
2026 pvt->pci_ta = pdev;
2027 break;
2028 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
2029 pvt->pci_ras = pdev;
2030 break;
2031 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
Tony Luck1f395812014-12-02 09:27:30 -08002032 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
Tony Luck1f395812014-12-02 09:27:30 -08002033 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
Tony Luck1f395812014-12-02 09:27:30 -08002034 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
Tony Luckfa2ce642015-05-20 19:10:35 -03002035 {
2036 int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0;
2037 pvt->pci_tad[id] = pdev;
2038 saw_chan_mask |= 1 << id;
2039 }
2040 break;
2041 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
2042 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
2043 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
2044 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
2045 {
2046 int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4;
2047 pvt->pci_tad[id] = pdev;
2048 saw_chan_mask |= 1 << id;
2049 }
Tony Luck1f395812014-12-02 09:27:30 -08002050 break;
2051 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2052 pvt->pci_ddrio = pdev;
2053 break;
Tony Luckfa2ce642015-05-20 19:10:35 -03002054 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2055 pvt->pci_ha1 = pdev;
2056 break;
2057 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2058 pvt->pci_ha1_ta = pdev;
2059 break;
Tony Luck1f395812014-12-02 09:27:30 -08002060 default:
2061 break;
2062 }
2063
2064 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2065 sbridge_dev->bus,
2066 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2067 pdev);
2068 }
2069
2070 /* Check if everything were registered */
2071 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2072 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2073 goto enodev;
2074
Tony Luckfa2ce642015-05-20 19:10:35 -03002075 if (saw_chan_mask != 0x0f && /* -EN */
2076 saw_chan_mask != 0x33 && /* -EP */
2077 saw_chan_mask != 0xff) /* -EX */
2078 goto enodev;
Tony Luck1f395812014-12-02 09:27:30 -08002079 return 0;
2080
2081enodev:
2082 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2083 return -ENODEV;
2084}
2085
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002086/****************************************************************************
2087 Error check routines
2088 ****************************************************************************/
2089
2090/*
2091 * While Sandy Bridge has error count registers, SMI BIOS read values from
2092 * and resets the counters. So, they are not reliable for the OS to read
2093 * from them. So, we have no option but to just trust on whatever MCE is
2094 * telling us about the errors.
2095 */
2096static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2097 const struct mce *m)
2098{
2099 struct mem_ctl_info *new_mci;
2100 struct sbridge_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002101 enum hw_event_mc_err_type tp_event;
Mauro Carvalho Chehabe17a2f42a2012-05-11 11:41:45 -03002102 char *type, *optype, msg[256];
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002103 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2104 bool overflow = GET_BITFIELD(m->status, 62, 62);
2105 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002106 bool recoverable;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002107 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2108 u32 mscod = GET_BITFIELD(m->status, 16, 31);
2109 u32 errcode = GET_BITFIELD(m->status, 0, 15);
2110 u32 channel = GET_BITFIELD(m->status, 0, 3);
2111 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2112 long channel_mask, first_channel;
Tony Luck7d375bf2015-05-18 17:50:42 -03002113 u8 rank, socket, ha;
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002114 int rc, dimm;
Mauro Carvalho Chehabe17a2f42a2012-05-11 11:41:45 -03002115 char *area_type = NULL;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002116
Tony Luckfa2ce642015-05-20 19:10:35 -03002117 if (pvt->info.type != SANDY_BRIDGE)
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002118 recoverable = true;
2119 else
2120 recoverable = GET_BITFIELD(m->status, 56, 56);
2121
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002122 if (uncorrected_error) {
2123 if (ripv) {
2124 type = "FATAL";
2125 tp_event = HW_EVENT_ERR_FATAL;
2126 } else {
2127 type = "NON_FATAL";
2128 tp_event = HW_EVENT_ERR_UNCORRECTED;
2129 }
2130 } else {
2131 type = "CORRECTED";
2132 tp_event = HW_EVENT_ERR_CORRECTED;
2133 }
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002134
2135 /*
David Mackey15ed1032012-04-17 11:30:52 -07002136 * According with Table 15-9 of the Intel Architecture spec vol 3A,
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002137 * memory errors should fit in this mask:
2138 * 000f 0000 1mmm cccc (binary)
2139 * where:
2140 * f = Correction Report Filtering Bit. If 1, subsequent errors
2141 * won't be shown
2142 * mmm = error type
2143 * cccc = channel
2144 * If the mask doesn't match, report an error to the parsing logic
2145 */
2146 if (! ((errcode & 0xef80) == 0x80)) {
2147 optype = "Can't parse: it is not a mem";
2148 } else {
2149 switch (optypenum) {
2150 case 0:
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002151 optype = "generic undef request error";
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002152 break;
2153 case 1:
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002154 optype = "memory read error";
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002155 break;
2156 case 2:
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002157 optype = "memory write error";
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002158 break;
2159 case 3:
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002160 optype = "addr/cmd error";
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002161 break;
2162 case 4:
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002163 optype = "memory scrubbing error";
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002164 break;
2165 default:
2166 optype = "reserved";
2167 break;
2168 }
2169 }
2170
Aristeu Rozanskibe3036d2013-10-30 13:27:05 -03002171 /* Only decode errors with an valid address (ADDRV) */
2172 if (!GET_BITFIELD(m->status, 58, 58))
2173 return;
2174
Tony Luck7d375bf2015-05-18 17:50:42 -03002175 rc = get_memory_error_data(mci, m->addr, &socket, &ha,
Mauro Carvalho Chehabe17a2f42a2012-05-11 11:41:45 -03002176 &channel_mask, &rank, &area_type, msg);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002177 if (rc < 0)
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002178 goto err_parsing;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002179 new_mci = get_mci_for_node_id(socket);
2180 if (!new_mci) {
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002181 strcpy(msg, "Error: socket got corrupted!");
2182 goto err_parsing;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002183 }
2184 mci = new_mci;
2185 pvt = mci->pvt_info;
2186
2187 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
2188
2189 if (rank < 4)
2190 dimm = 0;
2191 else if (rank < 8)
2192 dimm = 1;
2193 else
2194 dimm = 2;
2195
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002196
2197 /*
Mauro Carvalho Chehabe17a2f42a2012-05-11 11:41:45 -03002198 * FIXME: On some memory configurations (mirror, lockstep), the
2199 * Memory Controller can't point the error to a single DIMM. The
2200 * EDAC core should be handling the channel mask, in order to point
2201 * to the group of dimm's where the error may be happening.
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002202 */
Aristeu Rozanskid7c660b2014-06-02 15:15:28 -03002203 if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
2204 channel = first_channel;
2205
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002206 snprintf(msg, sizeof(msg),
Tony Luck7d375bf2015-05-18 17:50:42 -03002207 "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
Mauro Carvalho Chehabe17a2f42a2012-05-11 11:41:45 -03002208 overflow ? " OVERFLOW" : "",
2209 (uncorrected_error && recoverable) ? " recoverable" : "",
2210 area_type,
2211 mscod, errcode,
Tony Luck7d375bf2015-05-18 17:50:42 -03002212 socket, ha,
Mauro Carvalho Chehabe17a2f42a2012-05-11 11:41:45 -03002213 channel_mask,
2214 rank);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002215
Joe Perches956b9ba2012-04-29 17:08:39 -03002216 edac_dbg(0, "%s\n", msg);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002217
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002218 /* FIXME: need support for channel mask */
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002219
Seth Jennings351fc4a2014-09-05 14:28:47 -05002220 if (channel == CHANNEL_UNSPECIFIED)
2221 channel = -1;
2222
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002223 /* Call the helper to output message */
Mauro Carvalho Chehabc1053832012-06-04 13:40:05 -03002224 edac_mc_handle_error(tp_event, mci, core_err_cnt,
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002225 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
Tony Luck7d375bf2015-05-18 17:50:42 -03002226 4*ha+channel, dimm, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -03002227 optype, msg);
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002228 return;
2229err_parsing:
Mauro Carvalho Chehabc1053832012-06-04 13:40:05 -03002230 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002231 -1, -1, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -03002232 msg, "");
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002233
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002234}
2235
2236/*
2237 * sbridge_check_error Retrieve and process errors reported by the
2238 * hardware. Called by the Core module.
2239 */
2240static void sbridge_check_error(struct mem_ctl_info *mci)
2241{
2242 struct sbridge_pvt *pvt = mci->pvt_info;
2243 int i;
2244 unsigned count = 0;
2245 struct mce *m;
2246
2247 /*
2248 * MCE first step: Copy all mce errors into a temporary buffer
2249 * We use a double buffering here, to reduce the risk of
2250 * loosing an error.
2251 */
2252 smp_rmb();
2253 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
2254 % MCE_LOG_LEN;
2255 if (!count)
2256 return;
2257
2258 m = pvt->mce_outentry;
2259 if (pvt->mce_in + count > MCE_LOG_LEN) {
2260 unsigned l = MCE_LOG_LEN - pvt->mce_in;
2261
2262 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
2263 smp_wmb();
2264 pvt->mce_in = 0;
2265 count -= l;
2266 m += l;
2267 }
2268 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
2269 smp_wmb();
2270 pvt->mce_in += count;
2271
2272 smp_rmb();
2273 if (pvt->mce_overrun) {
2274 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
2275 pvt->mce_overrun);
2276 smp_wmb();
2277 pvt->mce_overrun = 0;
2278 }
2279
2280 /*
2281 * MCE second step: parse errors and display
2282 */
2283 for (i = 0; i < count; i++)
2284 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
2285}
2286
2287/*
2288 * sbridge_mce_check_error Replicates mcelog routine to get errors
2289 * This routine simply queues mcelog errors, and
2290 * return. The error itself should be handled later
2291 * by sbridge_check_error.
2292 * WARNING: As this routine should be called at NMI time, extra care should
2293 * be taken to avoid deadlocks, and to be as fast as possible.
2294 */
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -02002295static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
2296 void *data)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002297{
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -02002298 struct mce *mce = (struct mce *)data;
2299 struct mem_ctl_info *mci;
2300 struct sbridge_pvt *pvt;
Aristeu Rozanskicf40f802014-03-11 15:45:41 -04002301 char *type;
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -02002302
Chen, Gongfd521032013-12-06 01:17:09 -05002303 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2304 return NOTIFY_DONE;
2305
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -02002306 mci = get_mci_for_node_id(mce->socketid);
2307 if (!mci)
2308 return NOTIFY_BAD;
2309 pvt = mci->pvt_info;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002310
2311 /*
2312 * Just let mcelog handle it if the error is
2313 * outside the memory controller. A memory error
2314 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
2315 * bit 12 has an special meaning.
2316 */
2317 if ((mce->status & 0xefff) >> 7 != 1)
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -02002318 return NOTIFY_DONE;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002319
Aristeu Rozanskicf40f802014-03-11 15:45:41 -04002320 if (mce->mcgstatus & MCG_STATUS_MCIP)
2321 type = "Exception";
2322 else
2323 type = "Event";
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002324
Aristeu Rozanski49856dc2014-03-11 15:45:42 -04002325 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002326
Aristeu Rozanski49856dc2014-03-11 15:45:42 -04002327 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
2328 "Bank %d: %016Lx\n", mce->extcpu, type,
2329 mce->mcgstatus, mce->bank, mce->status);
2330 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
2331 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
2332 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002333
Aristeu Rozanski49856dc2014-03-11 15:45:42 -04002334 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
2335 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
2336 mce->time, mce->socketid, mce->apicid);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002337
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002338 smp_rmb();
2339 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
2340 smp_wmb();
2341 pvt->mce_overrun++;
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -02002342 return NOTIFY_DONE;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002343 }
2344
2345 /* Copy memory error at the ringbuffer */
2346 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
2347 smp_wmb();
2348 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
2349
2350 /* Handle fatal errors immediately */
2351 if (mce->mcgstatus & 1)
2352 sbridge_check_error(mci);
2353
2354 /* Advice mcelog that the error were handled */
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -02002355 return NOTIFY_STOP;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002356}
2357
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -02002358static struct notifier_block sbridge_mce_dec = {
2359 .notifier_call = sbridge_mce_check_error,
2360};
2361
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002362/****************************************************************************
2363 EDAC register/unregister logic
2364 ****************************************************************************/
2365
2366static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
2367{
2368 struct mem_ctl_info *mci = sbridge_dev->mci;
2369 struct sbridge_pvt *pvt;
2370
2371 if (unlikely(!mci || !mci->pvt_info)) {
Joe Perches956b9ba2012-04-29 17:08:39 -03002372 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002373
2374 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
2375 return;
2376 }
2377
2378 pvt = mci->pvt_info;
2379
Joe Perches956b9ba2012-04-29 17:08:39 -03002380 edac_dbg(0, "MC: mci = %p, dev = %p\n",
2381 mci, &sbridge_dev->pdev[0]->dev);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002382
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002383 /* Remove MC sysfs nodes */
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -03002384 edac_mc_del_mc(mci->pdev);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002385
Joe Perches956b9ba2012-04-29 17:08:39 -03002386 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002387 kfree(mci->ctl_name);
2388 edac_mc_free(mci);
2389 sbridge_dev->mci = NULL;
2390}
2391
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002392static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002393{
2394 struct mem_ctl_info *mci;
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002395 struct edac_mc_layer layers[2];
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002396 struct sbridge_pvt *pvt;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002397 struct pci_dev *pdev = sbridge_dev->pdev[0];
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002398 int rc;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002399
2400 /* Check the number of active and not disabled channels */
Aristeu Rozanskidbc954d2014-06-02 15:15:25 -03002401 rc = check_if_ecc_is_active(sbridge_dev->bus, type);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002402 if (unlikely(rc < 0))
2403 return rc;
2404
2405 /* allocate a new MC control structure */
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002406 layers[0].type = EDAC_MC_LAYER_CHANNEL;
2407 layers[0].size = NUM_CHANNELS;
2408 layers[0].is_virt_csrow = false;
2409 layers[1].type = EDAC_MC_LAYER_SLOT;
2410 layers[1].size = MAX_DIMMS;
2411 layers[1].is_virt_csrow = true;
Mauro Carvalho Chehabca0907b2012-05-02 14:37:00 -03002412 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
Mauro Carvalho Chehabc36e3e72012-04-16 15:12:22 -03002413 sizeof(*pvt));
2414
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002415 if (unlikely(!mci))
2416 return -ENOMEM;
2417
Joe Perches956b9ba2012-04-29 17:08:39 -03002418 edac_dbg(0, "MC: mci = %p, dev = %p\n",
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002419 mci, &pdev->dev);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002420
2421 pvt = mci->pvt_info;
2422 memset(pvt, 0, sizeof(*pvt));
2423
2424 /* Associate sbridge_dev and mci for future usage */
2425 pvt->sbridge_dev = sbridge_dev;
2426 sbridge_dev->mci = mci;
2427
2428 mci->mtype_cap = MEM_FLAG_DDR3;
2429 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2430 mci->edac_cap = EDAC_FLAG_NONE;
2431 mci->mod_name = "sbridge_edac.c";
2432 mci->mod_ver = SBRIDGE_REVISION;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002433 mci->dev_name = pci_name(pdev);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002434 mci->ctl_page_to_phys = NULL;
2435
2436 /* Set the function pointer to an actual operation function */
2437 mci->edac_check = sbridge_check_error;
2438
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002439 pvt->info.type = type;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002440 switch (type) {
2441 case IVY_BRIDGE:
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002442 pvt->info.rankcfgr = IB_RANK_CFG_A;
2443 pvt->info.get_tolm = ibridge_get_tolm;
2444 pvt->info.get_tohm = ibridge_get_tohm;
2445 pvt->info.dram_rule = ibridge_dram_rule;
Aristeu Rozanski9e375442014-06-02 15:15:22 -03002446 pvt->info.get_memory_type = get_memory_type;
Aristeu Rozanskif14d6892014-06-02 15:15:23 -03002447 pvt->info.get_node_id = get_node_id;
Aristeu Rozanskib976bcf2014-06-02 15:15:24 -03002448 pvt->info.rir_limit = rir_limit;
Jim Snowc59f9c02015-12-03 10:48:52 +01002449 pvt->info.sad_limit = sad_limit;
2450 pvt->info.interleave_mode = interleave_mode;
2451 pvt->info.show_interleave_mode = show_interleave_mode;
2452 pvt->info.dram_attr = dram_attr;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002453 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2454 pvt->info.interleave_list = ibridge_interleave_list;
2455 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2456 pvt->info.interleave_pkg = ibridge_interleave_pkg;
Aristeu Rozanski12f07212015-06-12 15:08:17 -04002457 pvt->info.get_width = ibridge_get_width;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002458 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
2459
2460 /* Store pci devices at mci for faster access */
2461 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
2462 if (unlikely(rc < 0))
2463 goto fail0;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002464 break;
2465 case SANDY_BRIDGE:
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002466 pvt->info.rankcfgr = SB_RANK_CFG_A;
2467 pvt->info.get_tolm = sbridge_get_tolm;
2468 pvt->info.get_tohm = sbridge_get_tohm;
2469 pvt->info.dram_rule = sbridge_dram_rule;
Aristeu Rozanski9e375442014-06-02 15:15:22 -03002470 pvt->info.get_memory_type = get_memory_type;
Aristeu Rozanskif14d6892014-06-02 15:15:23 -03002471 pvt->info.get_node_id = get_node_id;
Aristeu Rozanskib976bcf2014-06-02 15:15:24 -03002472 pvt->info.rir_limit = rir_limit;
Jim Snowc59f9c02015-12-03 10:48:52 +01002473 pvt->info.sad_limit = sad_limit;
2474 pvt->info.interleave_mode = interleave_mode;
2475 pvt->info.show_interleave_mode = show_interleave_mode;
2476 pvt->info.dram_attr = dram_attr;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002477 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
2478 pvt->info.interleave_list = sbridge_interleave_list;
2479 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
2480 pvt->info.interleave_pkg = sbridge_interleave_pkg;
Aristeu Rozanski12f07212015-06-12 15:08:17 -04002481 pvt->info.get_width = sbridge_get_width;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002482 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
2483
2484 /* Store pci devices at mci for faster access */
2485 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
2486 if (unlikely(rc < 0))
2487 goto fail0;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002488 break;
2489 case HASWELL:
2490 /* rankcfgr isn't used */
2491 pvt->info.get_tolm = haswell_get_tolm;
2492 pvt->info.get_tohm = haswell_get_tohm;
2493 pvt->info.dram_rule = ibridge_dram_rule;
2494 pvt->info.get_memory_type = haswell_get_memory_type;
2495 pvt->info.get_node_id = haswell_get_node_id;
2496 pvt->info.rir_limit = haswell_rir_limit;
Jim Snowc59f9c02015-12-03 10:48:52 +01002497 pvt->info.sad_limit = sad_limit;
2498 pvt->info.interleave_mode = interleave_mode;
2499 pvt->info.show_interleave_mode = show_interleave_mode;
2500 pvt->info.dram_attr = dram_attr;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002501 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2502 pvt->info.interleave_list = ibridge_interleave_list;
2503 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2504 pvt->info.interleave_pkg = ibridge_interleave_pkg;
Aristeu Rozanski12f07212015-06-12 15:08:17 -04002505 pvt->info.get_width = ibridge_get_width;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002506 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002507
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002508 /* Store pci devices at mci for faster access */
2509 rc = haswell_mci_bind_devs(mci, sbridge_dev);
2510 if (unlikely(rc < 0))
2511 goto fail0;
2512 break;
Tony Luck1f395812014-12-02 09:27:30 -08002513 case BROADWELL:
2514 /* rankcfgr isn't used */
2515 pvt->info.get_tolm = haswell_get_tolm;
2516 pvt->info.get_tohm = haswell_get_tohm;
2517 pvt->info.dram_rule = ibridge_dram_rule;
2518 pvt->info.get_memory_type = haswell_get_memory_type;
2519 pvt->info.get_node_id = haswell_get_node_id;
2520 pvt->info.rir_limit = haswell_rir_limit;
Jim Snowc59f9c02015-12-03 10:48:52 +01002521 pvt->info.sad_limit = sad_limit;
2522 pvt->info.interleave_mode = interleave_mode;
2523 pvt->info.show_interleave_mode = show_interleave_mode;
2524 pvt->info.dram_attr = dram_attr;
Tony Luck1f395812014-12-02 09:27:30 -08002525 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
2526 pvt->info.interleave_list = ibridge_interleave_list;
2527 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
2528 pvt->info.interleave_pkg = ibridge_interleave_pkg;
Aristeu Rozanski12f07212015-06-12 15:08:17 -04002529 pvt->info.get_width = broadwell_get_width;
Tony Luck1f395812014-12-02 09:27:30 -08002530 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
2531
2532 /* Store pci devices at mci for faster access */
2533 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
2534 if (unlikely(rc < 0))
2535 goto fail0;
2536 break;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002537 }
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002538
2539 /* Get dimm basic config and the memory layout */
2540 get_dimm_config(mci);
2541 get_memory_layout(mci);
2542
2543 /* record ptr to the generic device */
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002544 mci->pdev = &pdev->dev;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002545
2546 /* add this new MC control structure to EDAC's list of MCs */
2547 if (unlikely(edac_mc_add_mc(mci))) {
Joe Perches956b9ba2012-04-29 17:08:39 -03002548 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002549 rc = -EINVAL;
2550 goto fail0;
2551 }
2552
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002553 return 0;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002554
2555fail0:
2556 kfree(mci->ctl_name);
2557 edac_mc_free(mci);
2558 sbridge_dev->mci = NULL;
2559 return rc;
2560}
2561
2562/*
2563 * sbridge_probe Probe for ONE instance of device to see if it is
2564 * present.
2565 * return:
2566 * 0 for FOUND a device
2567 * < 0 for error code
2568 */
2569
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08002570static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002571{
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002572 int rc = -ENODEV;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002573 u8 mc, num_mc = 0;
2574 struct sbridge_dev *sbridge_dev;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002575 enum type type = SANDY_BRIDGE;
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002576
2577 /* get the pci devices we want to reserve for our use */
2578 mutex_lock(&sbridge_edac_lock);
2579
2580 /*
2581 * All memory controllers are allocated at the first pass.
2582 */
2583 if (unlikely(probed >= 1)) {
2584 mutex_unlock(&sbridge_edac_lock);
2585 return -ENODEV;
2586 }
2587 probed++;
2588
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002589 switch (pdev->device) {
2590 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002591 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table);
2592 type = IVY_BRIDGE;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002593 break;
Borislav Petkov11249e72015-02-05 12:39:36 +01002594 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002595 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
2596 type = SANDY_BRIDGE;
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002597 break;
2598 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2599 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table);
2600 type = HASWELL;
2601 break;
Tony Luck1f395812014-12-02 09:27:30 -08002602 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2603 rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_broadwell_table);
2604 type = BROADWELL;
2605 break;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002606 }
Borislav Petkov11249e72015-02-05 12:39:36 +01002607 if (unlikely(rc < 0)) {
2608 edac_dbg(0, "couldn't get all devices for 0x%x\n", pdev->device);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002609 goto fail0;
Borislav Petkov11249e72015-02-05 12:39:36 +01002610 }
2611
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002612 mc = 0;
2613
2614 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
Joe Perches956b9ba2012-04-29 17:08:39 -03002615 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
2616 mc, mc + 1, num_mc);
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -03002617
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002618 sbridge_dev->mc = mc++;
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002619 rc = sbridge_register_mci(sbridge_dev, type);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002620 if (unlikely(rc < 0))
2621 goto fail1;
2622 }
2623
Borislav Petkov11249e72015-02-05 12:39:36 +01002624 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002625
2626 mutex_unlock(&sbridge_edac_lock);
2627 return 0;
2628
2629fail1:
2630 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2631 sbridge_unregister_mci(sbridge_dev);
2632
2633 sbridge_put_all_devices();
2634fail0:
2635 mutex_unlock(&sbridge_edac_lock);
2636 return rc;
2637}
2638
2639/*
2640 * sbridge_remove destructor for one instance of device
2641 *
2642 */
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08002643static void sbridge_remove(struct pci_dev *pdev)
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002644{
2645 struct sbridge_dev *sbridge_dev;
2646
Joe Perches956b9ba2012-04-29 17:08:39 -03002647 edac_dbg(0, "\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002648
2649 /*
2650 * we have a trouble here: pdev value for removal will be wrong, since
2651 * it will point to the X58 register used to detect that the machine
2652 * is a Nehalem or upper design. However, due to the way several PCI
2653 * devices are grouped together to provide MC functionality, we need
2654 * to use a different method for releasing the devices
2655 */
2656
2657 mutex_lock(&sbridge_edac_lock);
2658
2659 if (unlikely(!probed)) {
2660 mutex_unlock(&sbridge_edac_lock);
2661 return;
2662 }
2663
2664 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
2665 sbridge_unregister_mci(sbridge_dev);
2666
2667 /* Release PCI resources */
2668 sbridge_put_all_devices();
2669
2670 probed--;
2671
2672 mutex_unlock(&sbridge_edac_lock);
2673}
2674
2675MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
2676
2677/*
2678 * sbridge_driver pci_driver structure for this module
2679 *
2680 */
2681static struct pci_driver sbridge_driver = {
2682 .name = "sbridge_edac",
2683 .probe = sbridge_probe,
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08002684 .remove = sbridge_remove,
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002685 .id_table = sbridge_pci_tbl,
2686};
2687
2688/*
2689 * sbridge_init Module entry function
2690 * Try to initialize this module for its devices
2691 */
2692static int __init sbridge_init(void)
2693{
2694 int pci_rc;
2695
Joe Perches956b9ba2012-04-29 17:08:39 -03002696 edac_dbg(2, "\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002697
2698 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2699 opstate_init();
2700
2701 pci_rc = pci_register_driver(&sbridge_driver);
Chen Gonge35fca42012-05-08 20:40:12 -03002702 if (pci_rc >= 0) {
2703 mce_register_decode_chain(&sbridge_mce_dec);
Chen, Gongfd521032013-12-06 01:17:09 -05002704 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
2705 sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002706 return 0;
Chen Gonge35fca42012-05-08 20:40:12 -03002707 }
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002708
2709 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
2710 pci_rc);
2711
2712 return pci_rc;
2713}
2714
2715/*
2716 * sbridge_exit() Module exit function
2717 * Unregister the driver
2718 */
2719static void __exit sbridge_exit(void)
2720{
Joe Perches956b9ba2012-04-29 17:08:39 -03002721 edac_dbg(2, "\n");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002722 pci_unregister_driver(&sbridge_driver);
Chen Gonge35fca42012-05-08 20:40:12 -03002723 mce_unregister_decode_chain(&sbridge_mce_dec);
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002724}
2725
2726module_init(sbridge_init);
2727module_exit(sbridge_exit);
2728
2729module_param(edac_op_state, int, 0444);
2730MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
2731
2732MODULE_LICENSE("GPL");
Mauro Carvalho Chehab37e59f82014-02-07 08:03:07 -02002733MODULE_AUTHOR("Mauro Carvalho Chehab");
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002734MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
Aristeu Rozanski4d715a82013-10-30 13:27:06 -03002735MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
Mauro Carvalho Chehabeebf11a2011-10-20 19:18:01 -02002736 SBRIDGE_REVISION);