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gerrit-public.fairphone.software / kernel / msm-4.19 / c311864310ae04fe6c6588911f62fa747984864a / . / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
blob: e89a7ecdc5677076572b125079ad5a1e1b545119 [file] [log] [blame]
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
Andreas Fenkart55143432014-11-08 15:33:09 +0100[diff] [blame]22#include <linux/platform_data/hsmmc-omap.h>
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]23#include <linux/power/smartreflex.h>
24#include <linux/i2c-omap.h>
25
26#include <linux/omap-dma.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/asoc-ti-mcbsp.h>
29#include <plat/dmtimer.h>
30
31#include "omap_hwmod.h"
32#include "omap_hwmod_common_data.h"
33#include "cm1_7xx.h"
34#include "cm2_7xx.h"
35#include "prm7xx.h"
36#include "i2c.h"
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]37#include "wd_timer.h"
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]38#include "soc.h"
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]39
40/* Base offset for all DRA7XX interrupts external to MPUSS */
41#define DRA7XX_IRQ_GIC_START 32
42
43/* Base offset for all DRA7XX dma requests */
44#define DRA7XX_DMA_REQ_START 1
45
46
47/*
48 * IP blocks
49 */
50
51/*
Tomi Valkeinen42121682014-09-15 13:12:18 -0500[diff] [blame]52 * 'dmm' class
53 * instance(s): dmm
54 */
55static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
56 .name = "dmm",
57};
58
59/* dmm */
60static struct omap_hwmod dra7xx_dmm_hwmod = {
61 .name = "dmm",
62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 },
69 },
70};
71
72/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2
75 */
76static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
77 .name = "l3",
78};
79
80/* l3_instr */
81static struct omap_hwmod dra7xx_l3_instr_hwmod = {
82 .name = "l3_instr",
83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
90 },
91 },
92};
93
94/* l3_main_1 */
95static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
96 .name = "l3_main_1",
97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
99 .prcm = {
100 .omap4 = {
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 },
104 },
105};
106
107/* l3_main_2 */
108static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
109 .name = "l3_main_2",
110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL,
117 },
118 },
119};
120
121/*
122 * 'l4' class
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
124 */
125static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
126 .name = "l4",
127};
128
129/* l4_cfg */
130static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
131 .name = "l4_cfg",
132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
138 },
139 },
140};
141
142/* l4_per1 */
143static struct omap_hwmod dra7xx_l4_per1_hwmod = {
144 .name = "l4_per1",
145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 },
152 },
153};
154
155/* l4_per2 */
156static struct omap_hwmod dra7xx_l4_per2_hwmod = {
157 .name = "l4_per2",
158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
164 },
165 },
166};
167
168/* l4_per3 */
169static struct omap_hwmod dra7xx_l4_per3_hwmod = {
170 .name = "l4_per3",
171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
177 },
178 },
179};
180
181/* l4_wkup */
182static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
183 .name = "l4_wkup",
184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = {
187 .omap4 = {
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 },
191 },
192};
193
194/*
195 * 'atl' class
196 *
197 */
198
199static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
200 .name = "atl",
201};
202
203/* atl */
204static struct omap_hwmod dra7xx_atl_hwmod = {
205 .name = "atl",
206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
214 },
215 },
216};
217
218/*
219 * 'bb2d' class
220 *
221 */
222
223static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
224 .name = "bb2d",
225};
226
227/* bb2d */
228static struct omap_hwmod dra7xx_bb2d_hwmod = {
229 .name = "bb2d",
230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
238 },
239 },
240};
241
242/*
243 * 'counter' class
244 *
245 */
246
247static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
248 .rev_offs = 0x0000,
249 .sysc_offs = 0x0010,
250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
252 SIDLE_SMART_WKUP),
253 .sysc_fields = &omap_hwmod_sysc_type1,
254};
255
256static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
257 .name = "counter",
258 .sysc = &dra7xx_counter_sysc,
259};
260
261/* counter_32k */
262static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
272 },
273 },
274};
275
276/*
277 * 'ctrl_module' class
278 *
279 */
280
281static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module",
283};
284
285/* ctrl_module_wkup */
286static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm",
290 .prcm = {
291 .omap4 = {
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
293 },
294 },
295};
296
297/*
Mugunthan V N077c42f2014-07-08 18:46:39 +0530[diff] [blame]298 * 'gmac' class
299 * cpsw/gmac sub system
300 */
301static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
302 .rev_offs = 0x0,
303 .sysc_offs = 0x8,
304 .syss_offs = 0x4,
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
308 MSTANDBY_NO),
309 .sysc_fields = &omap_hwmod_sysc_type3,
310};
311
312static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
313 .name = "gmac",
314 .sysc = &dra7xx_gmac_sysc,
315};
316
317static struct omap_hwmod dra7xx_gmac_hwmod = {
318 .name = "gmac",
319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck",
323 .mpu_rt_idx = 1,
324 .prcm = {
325 .omap4 = {
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
329 },
330 },
331};
332
333/*
334 * 'mdio' class
335 */
336static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio",
338};
339
340static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck",
345};
346
347/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]348 * 'dcan' class
349 *
350 */
351
352static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
353 .name = "dcan",
354};
355
356/* dcan1 */
357static struct omap_hwmod dra7xx_dcan1_hwmod = {
358 .name = "dcan1",
359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux",
362 .prcm = {
363 .omap4 = {
364 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
366 .modulemode = MODULEMODE_SWCTRL,
367 },
368 },
369};
370
371/* dcan2 */
372static struct omap_hwmod dra7xx_dcan2_hwmod = {
373 .name = "dcan2",
374 .class = &dra7xx_dcan_hwmod_class,
375 .clkdm_name = "l4per2_clkdm",
376 .main_clk = "sys_clkin1",
377 .prcm = {
378 .omap4 = {
379 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
381 .modulemode = MODULEMODE_SWCTRL,
382 },
383 },
384};
385
Vignesh Rb05ff3c2016-04-10 13:20:09 -0600[diff] [blame]386/* pwmss */
387static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
388 .rev_offs = 0x0,
389 .sysc_offs = 0x4,
390 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
391 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
392 .sysc_fields = &omap_hwmod_sysc_type2,
393};
394
395/*
396 * epwmss class
397 */
398static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
399 .name = "epwmss",
400 .sysc = &dra7xx_epwmss_sysc,
401};
402
403/* epwmss0 */
404static struct omap_hwmod dra7xx_epwmss0_hwmod = {
405 .name = "epwmss0",
406 .class = &dra7xx_epwmss_hwmod_class,
407 .clkdm_name = "l4per2_clkdm",
408 .main_clk = "l4_root_clk_div",
409 .prcm = {
410 .omap4 = {
411 .modulemode = MODULEMODE_SWCTRL,
412 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
413 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
414 },
415 },
416};
417
418/* epwmss1 */
419static struct omap_hwmod dra7xx_epwmss1_hwmod = {
420 .name = "epwmss1",
421 .class = &dra7xx_epwmss_hwmod_class,
422 .clkdm_name = "l4per2_clkdm",
423 .main_clk = "l4_root_clk_div",
424 .prcm = {
425 .omap4 = {
426 .modulemode = MODULEMODE_SWCTRL,
427 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
428 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
429 },
430 },
431};
432
433/* epwmss2 */
434static struct omap_hwmod dra7xx_epwmss2_hwmod = {
435 .name = "epwmss2",
436 .class = &dra7xx_epwmss_hwmod_class,
437 .clkdm_name = "l4per2_clkdm",
438 .main_clk = "l4_root_clk_div",
439 .prcm = {
440 .omap4 = {
441 .modulemode = MODULEMODE_SWCTRL,
442 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
443 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
444 },
445 },
446};
447
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]448/*
449 * 'dma' class
450 *
451 */
452
453static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
454 .rev_offs = 0x0000,
455 .sysc_offs = 0x002c,
456 .syss_offs = 0x0028,
457 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
458 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
459 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
460 SYSS_HAS_RESET_STATUS),
461 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
462 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
463 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
464 .sysc_fields = &omap_hwmod_sysc_type1,
465};
466
467static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
468 .name = "dma",
469 .sysc = &dra7xx_dma_sysc,
470};
471
472/* dma dev_attr */
473static struct omap_dma_dev_attr dma_dev_attr = {
474 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
475 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
476 .lch_count = 32,
477};
478
479/* dma_system */
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]480static struct omap_hwmod dra7xx_dma_system_hwmod = {
481 .name = "dma_system",
482 .class = &dra7xx_dma_hwmod_class,
483 .clkdm_name = "dma_clkdm",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]484 .main_clk = "l3_iclk_div",
485 .prcm = {
486 .omap4 = {
487 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
488 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
489 },
490 },
491 .dev_attr = &dma_dev_attr,
492};
493
494/*
Peter Ujfalusi34b41822016-02-25 16:50:18 +0200[diff] [blame]495 * 'tpcc' class
496 *
497 */
498static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
499 .name = "tpcc",
500};
501
502static struct omap_hwmod dra7xx_tpcc_hwmod = {
503 .name = "tpcc",
504 .class = &dra7xx_tpcc_hwmod_class,
505 .clkdm_name = "l3main1_clkdm",
506 .main_clk = "l3_iclk_div",
507 .prcm = {
508 .omap4 = {
509 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
510 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
511 },
512 },
513};
514
515/*
516 * 'tptc' class
517 *
518 */
519static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
520 .name = "tptc",
521};
522
523/* tptc0 */
524static struct omap_hwmod dra7xx_tptc0_hwmod = {
525 .name = "tptc0",
526 .class = &dra7xx_tptc_hwmod_class,
527 .clkdm_name = "l3main1_clkdm",
528 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
529 .main_clk = "l3_iclk_div",
530 .prcm = {
531 .omap4 = {
532 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
533 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
534 .modulemode = MODULEMODE_HWCTRL,
535 },
536 },
537};
538
539/* tptc1 */
540static struct omap_hwmod dra7xx_tptc1_hwmod = {
541 .name = "tptc1",
542 .class = &dra7xx_tptc_hwmod_class,
543 .clkdm_name = "l3main1_clkdm",
544 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
545 .main_clk = "l3_iclk_div",
546 .prcm = {
547 .omap4 = {
548 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
549 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
550 .modulemode = MODULEMODE_HWCTRL,
551 },
552 },
553};
554
555/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]556 * 'dss' class
557 *
558 */
559
560static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
561 .rev_offs = 0x0000,
562 .syss_offs = 0x0014,
563 .sysc_flags = SYSS_HAS_RESET_STATUS,
564};
565
566static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
567 .name = "dss",
568 .sysc = &dra7xx_dss_sysc,
569 .reset = omap_dss_reset,
570};
571
572/* dss */
573static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
574 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
575 { .dma_req = -1 }
576};
577
578static struct omap_hwmod_opt_clk dss_opt_clks[] = {
579 { .role = "dss_clk", .clk = "dss_dss_clk" },
580 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
581 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
582 { .role = "video2_clk", .clk = "dss_video2_clk" },
583 { .role = "video1_clk", .clk = "dss_video1_clk" },
584 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
Tomi Valkeinen2d5a3c82015-02-23 12:53:56 +0200[diff] [blame]585 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]586};
587
588static struct omap_hwmod dra7xx_dss_hwmod = {
589 .name = "dss_core",
590 .class = &dra7xx_dss_hwmod_class,
591 .clkdm_name = "dss_clkdm",
592 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
593 .sdma_reqs = dra7xx_dss_sdma_reqs,
594 .main_clk = "dss_dss_clk",
595 .prcm = {
596 .omap4 = {
597 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
598 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
599 .modulemode = MODULEMODE_SWCTRL,
600 },
601 },
602 .opt_clks = dss_opt_clks,
603 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
604};
605
606/*
607 * 'dispc' class
608 * display controller
609 */
610
611static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
612 .rev_offs = 0x0000,
613 .sysc_offs = 0x0010,
614 .syss_offs = 0x0014,
615 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
616 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
617 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
618 SYSS_HAS_RESET_STATUS),
619 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
620 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
621 .sysc_fields = &omap_hwmod_sysc_type1,
622};
623
624static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
625 .name = "dispc",
626 .sysc = &dra7xx_dispc_sysc,
627};
628
629/* dss_dispc */
630/* dss_dispc dev_attr */
631static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
632 .has_framedonetv_irq = 1,
633 .manager_count = 4,
634};
635
636static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
637 .name = "dss_dispc",
638 .class = &dra7xx_dispc_hwmod_class,
639 .clkdm_name = "dss_clkdm",
640 .main_clk = "dss_dss_clk",
641 .prcm = {
642 .omap4 = {
643 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
644 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
645 },
646 },
647 .dev_attr = &dss_dispc_dev_attr,
Tomi Valkeinena3818c62014-10-09 16:45:56 +0300[diff] [blame]648 .parent_hwmod = &dra7xx_dss_hwmod,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]649};
650
651/*
652 * 'hdmi' class
653 * hdmi controller
654 */
655
656static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
657 .rev_offs = 0x0000,
658 .sysc_offs = 0x0010,
659 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
660 SYSC_HAS_SOFTRESET),
661 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
662 SIDLE_SMART_WKUP),
663 .sysc_fields = &omap_hwmod_sysc_type2,
664};
665
666static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
667 .name = "hdmi",
668 .sysc = &dra7xx_hdmi_sysc,
669};
670
671/* dss_hdmi */
672
673static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
674 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
675};
676
677static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
678 .name = "dss_hdmi",
679 .class = &dra7xx_hdmi_hwmod_class,
680 .clkdm_name = "dss_clkdm",
681 .main_clk = "dss_48mhz_clk",
682 .prcm = {
683 .omap4 = {
684 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
685 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
686 },
687 },
688 .opt_clks = dss_hdmi_opt_clks,
689 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
Tomi Valkeinena3818c62014-10-09 16:45:56 +0300[diff] [blame]690 .parent_hwmod = &dra7xx_dss_hwmod,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]691};
692
693/*
694 * 'elm' class
695 *
696 */
697
698static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
699 .rev_offs = 0x0000,
700 .sysc_offs = 0x0010,
701 .syss_offs = 0x0014,
702 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
703 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
704 SYSS_HAS_RESET_STATUS),
705 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
706 SIDLE_SMART_WKUP),
707 .sysc_fields = &omap_hwmod_sysc_type1,
708};
709
710static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
711 .name = "elm",
712 .sysc = &dra7xx_elm_sysc,
713};
714
715/* elm */
716
717static struct omap_hwmod dra7xx_elm_hwmod = {
718 .name = "elm",
719 .class = &dra7xx_elm_hwmod_class,
720 .clkdm_name = "l4per_clkdm",
721 .main_clk = "l3_iclk_div",
722 .prcm = {
723 .omap4 = {
724 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
725 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
726 },
727 },
728};
729
730/*
731 * 'gpio' class
732 *
733 */
734
735static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
736 .rev_offs = 0x0000,
737 .sysc_offs = 0x0010,
738 .syss_offs = 0x0114,
739 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
740 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
741 SYSS_HAS_RESET_STATUS),
742 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
743 SIDLE_SMART_WKUP),
744 .sysc_fields = &omap_hwmod_sysc_type1,
745};
746
747static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
748 .name = "gpio",
749 .sysc = &dra7xx_gpio_sysc,
750 .rev = 2,
751};
752
753/* gpio dev_attr */
754static struct omap_gpio_dev_attr gpio_dev_attr = {
755 .bank_width = 32,
756 .dbck_flag = true,
757};
758
759/* gpio1 */
760static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
761 { .role = "dbclk", .clk = "gpio1_dbclk" },
762};
763
764static struct omap_hwmod dra7xx_gpio1_hwmod = {
765 .name = "gpio1",
766 .class = &dra7xx_gpio_hwmod_class,
767 .clkdm_name = "wkupaon_clkdm",
768 .main_clk = "wkupaon_iclk_mux",
769 .prcm = {
770 .omap4 = {
771 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
772 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
773 .modulemode = MODULEMODE_HWCTRL,
774 },
775 },
776 .opt_clks = gpio1_opt_clks,
777 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
778 .dev_attr = &gpio_dev_attr,
779};
780
781/* gpio2 */
782static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
783 { .role = "dbclk", .clk = "gpio2_dbclk" },
784};
785
786static struct omap_hwmod dra7xx_gpio2_hwmod = {
787 .name = "gpio2",
788 .class = &dra7xx_gpio_hwmod_class,
789 .clkdm_name = "l4per_clkdm",
790 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
791 .main_clk = "l3_iclk_div",
792 .prcm = {
793 .omap4 = {
794 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
795 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
796 .modulemode = MODULEMODE_HWCTRL,
797 },
798 },
799 .opt_clks = gpio2_opt_clks,
800 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
801 .dev_attr = &gpio_dev_attr,
802};
803
804/* gpio3 */
805static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
806 { .role = "dbclk", .clk = "gpio3_dbclk" },
807};
808
809static struct omap_hwmod dra7xx_gpio3_hwmod = {
810 .name = "gpio3",
811 .class = &dra7xx_gpio_hwmod_class,
812 .clkdm_name = "l4per_clkdm",
813 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
814 .main_clk = "l3_iclk_div",
815 .prcm = {
816 .omap4 = {
817 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
818 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
819 .modulemode = MODULEMODE_HWCTRL,
820 },
821 },
822 .opt_clks = gpio3_opt_clks,
823 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
824 .dev_attr = &gpio_dev_attr,
825};
826
827/* gpio4 */
828static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
829 { .role = "dbclk", .clk = "gpio4_dbclk" },
830};
831
832static struct omap_hwmod dra7xx_gpio4_hwmod = {
833 .name = "gpio4",
834 .class = &dra7xx_gpio_hwmod_class,
835 .clkdm_name = "l4per_clkdm",
836 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
837 .main_clk = "l3_iclk_div",
838 .prcm = {
839 .omap4 = {
840 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
841 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
842 .modulemode = MODULEMODE_HWCTRL,
843 },
844 },
845 .opt_clks = gpio4_opt_clks,
846 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
847 .dev_attr = &gpio_dev_attr,
848};
849
850/* gpio5 */
851static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
852 { .role = "dbclk", .clk = "gpio5_dbclk" },
853};
854
855static struct omap_hwmod dra7xx_gpio5_hwmod = {
856 .name = "gpio5",
857 .class = &dra7xx_gpio_hwmod_class,
858 .clkdm_name = "l4per_clkdm",
859 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
860 .main_clk = "l3_iclk_div",
861 .prcm = {
862 .omap4 = {
863 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
864 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
865 .modulemode = MODULEMODE_HWCTRL,
866 },
867 },
868 .opt_clks = gpio5_opt_clks,
869 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
870 .dev_attr = &gpio_dev_attr,
871};
872
873/* gpio6 */
874static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
875 { .role = "dbclk", .clk = "gpio6_dbclk" },
876};
877
878static struct omap_hwmod dra7xx_gpio6_hwmod = {
879 .name = "gpio6",
880 .class = &dra7xx_gpio_hwmod_class,
881 .clkdm_name = "l4per_clkdm",
882 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
883 .main_clk = "l3_iclk_div",
884 .prcm = {
885 .omap4 = {
886 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
887 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
888 .modulemode = MODULEMODE_HWCTRL,
889 },
890 },
891 .opt_clks = gpio6_opt_clks,
892 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
893 .dev_attr = &gpio_dev_attr,
894};
895
896/* gpio7 */
897static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
898 { .role = "dbclk", .clk = "gpio7_dbclk" },
899};
900
901static struct omap_hwmod dra7xx_gpio7_hwmod = {
902 .name = "gpio7",
903 .class = &dra7xx_gpio_hwmod_class,
904 .clkdm_name = "l4per_clkdm",
905 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
906 .main_clk = "l3_iclk_div",
907 .prcm = {
908 .omap4 = {
909 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
910 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
911 .modulemode = MODULEMODE_HWCTRL,
912 },
913 },
914 .opt_clks = gpio7_opt_clks,
915 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
916 .dev_attr = &gpio_dev_attr,
917};
918
919/* gpio8 */
920static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
921 { .role = "dbclk", .clk = "gpio8_dbclk" },
922};
923
924static struct omap_hwmod dra7xx_gpio8_hwmod = {
925 .name = "gpio8",
926 .class = &dra7xx_gpio_hwmod_class,
927 .clkdm_name = "l4per_clkdm",
928 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
929 .main_clk = "l3_iclk_div",
930 .prcm = {
931 .omap4 = {
932 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
933 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
934 .modulemode = MODULEMODE_HWCTRL,
935 },
936 },
937 .opt_clks = gpio8_opt_clks,
938 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
939 .dev_attr = &gpio_dev_attr,
940};
941
942/*
943 * 'gpmc' class
944 *
945 */
946
947static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
948 .rev_offs = 0x0000,
949 .sysc_offs = 0x0010,
950 .syss_offs = 0x0014,
951 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
952 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
Roger Quadros91a57732015-07-08 17:34:43 +0300[diff] [blame]953 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]954 .sysc_fields = &omap_hwmod_sysc_type1,
955};
956
957static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
958 .name = "gpmc",
959 .sysc = &dra7xx_gpmc_sysc,
960};
961
962/* gpmc */
963
964static struct omap_hwmod dra7xx_gpmc_hwmod = {
965 .name = "gpmc",
966 .class = &dra7xx_gpmc_hwmod_class,
967 .clkdm_name = "l3main1_clkdm",
Tony Lindgren63aa9452015-06-01 19:22:10 -0600[diff] [blame]968 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
Roger Quadros91a57732015-07-08 17:34:43 +0300[diff] [blame]969 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]970 .main_clk = "l3_iclk_div",
971 .prcm = {
972 .omap4 = {
973 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
974 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
975 .modulemode = MODULEMODE_HWCTRL,
976 },
977 },
978};
979
980/*
981 * 'hdq1w' class
982 *
983 */
984
985static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
986 .rev_offs = 0x0000,
987 .sysc_offs = 0x0014,
988 .syss_offs = 0x0018,
989 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
990 SYSS_HAS_RESET_STATUS),
991 .sysc_fields = &omap_hwmod_sysc_type1,
992};
993
994static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
995 .name = "hdq1w",
996 .sysc = &dra7xx_hdq1w_sysc,
997};
998
999/* hdq1w */
1000
1001static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1002 .name = "hdq1w",
1003 .class = &dra7xx_hdq1w_hwmod_class,
1004 .clkdm_name = "l4per_clkdm",
1005 .flags = HWMOD_INIT_NO_RESET,
1006 .main_clk = "func_12m_fclk",
1007 .prcm = {
1008 .omap4 = {
1009 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1010 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1011 .modulemode = MODULEMODE_SWCTRL,
1012 },
1013 },
1014};
1015
1016/*
1017 * 'i2c' class
1018 *
1019 */
1020
1021static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1022 .sysc_offs = 0x0010,
1023 .syss_offs = 0x0090,
1024 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1025 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1026 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1027 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1028 SIDLE_SMART_WKUP),
1029 .clockact = CLOCKACT_TEST_ICLK,
1030 .sysc_fields = &omap_hwmod_sysc_type1,
1031};
1032
1033static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1034 .name = "i2c",
1035 .sysc = &dra7xx_i2c_sysc,
1036 .reset = &omap_i2c_reset,
1037 .rev = OMAP_I2C_IP_VERSION_2,
1038};
1039
1040/* i2c dev_attr */
1041static struct omap_i2c_dev_attr i2c_dev_attr = {
1042 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1043};
1044
1045/* i2c1 */
1046static struct omap_hwmod dra7xx_i2c1_hwmod = {
1047 .name = "i2c1",
1048 .class = &dra7xx_i2c_hwmod_class,
1049 .clkdm_name = "l4per_clkdm",
1050 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1051 .main_clk = "func_96m_fclk",
1052 .prcm = {
1053 .omap4 = {
1054 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1055 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1056 .modulemode = MODULEMODE_SWCTRL,
1057 },
1058 },
1059 .dev_attr = &i2c_dev_attr,
1060};
1061
1062/* i2c2 */
1063static struct omap_hwmod dra7xx_i2c2_hwmod = {
1064 .name = "i2c2",
1065 .class = &dra7xx_i2c_hwmod_class,
1066 .clkdm_name = "l4per_clkdm",
1067 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1068 .main_clk = "func_96m_fclk",
1069 .prcm = {
1070 .omap4 = {
1071 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1072 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1073 .modulemode = MODULEMODE_SWCTRL,
1074 },
1075 },
1076 .dev_attr = &i2c_dev_attr,
1077};
1078
1079/* i2c3 */
1080static struct omap_hwmod dra7xx_i2c3_hwmod = {
1081 .name = "i2c3",
1082 .class = &dra7xx_i2c_hwmod_class,
1083 .clkdm_name = "l4per_clkdm",
1084 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1085 .main_clk = "func_96m_fclk",
1086 .prcm = {
1087 .omap4 = {
1088 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1089 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1090 .modulemode = MODULEMODE_SWCTRL,
1091 },
1092 },
1093 .dev_attr = &i2c_dev_attr,
1094};
1095
1096/* i2c4 */
1097static struct omap_hwmod dra7xx_i2c4_hwmod = {
1098 .name = "i2c4",
1099 .class = &dra7xx_i2c_hwmod_class,
1100 .clkdm_name = "l4per_clkdm",
1101 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1102 .main_clk = "func_96m_fclk",
1103 .prcm = {
1104 .omap4 = {
1105 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1106 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1107 .modulemode = MODULEMODE_SWCTRL,
1108 },
1109 },
1110 .dev_attr = &i2c_dev_attr,
1111};
1112
1113/* i2c5 */
1114static struct omap_hwmod dra7xx_i2c5_hwmod = {
1115 .name = "i2c5",
1116 .class = &dra7xx_i2c_hwmod_class,
1117 .clkdm_name = "ipu_clkdm",
1118 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1119 .main_clk = "func_96m_fclk",
1120 .prcm = {
1121 .omap4 = {
1122 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1123 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1124 .modulemode = MODULEMODE_SWCTRL,
1125 },
1126 },
1127 .dev_attr = &i2c_dev_attr,
1128};
1129
1130/*
Suman Anna067395d2014-07-11 16:44:39 -0500[diff] [blame]1131 * 'mailbox' class
1132 *
1133 */
1134
1135static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1136 .rev_offs = 0x0000,
1137 .sysc_offs = 0x0010,
1138 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1139 SYSC_HAS_SOFTRESET),
1140 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1141 .sysc_fields = &omap_hwmod_sysc_type2,
1142};
1143
1144static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1145 .name = "mailbox",
1146 .sysc = &dra7xx_mailbox_sysc,
1147};
1148
1149/* mailbox1 */
1150static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1151 .name = "mailbox1",
1152 .class = &dra7xx_mailbox_hwmod_class,
1153 .clkdm_name = "l4cfg_clkdm",
1154 .prcm = {
1155 .omap4 = {
1156 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1157 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1158 },
1159 },
1160};
1161
1162/* mailbox2 */
1163static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1164 .name = "mailbox2",
1165 .class = &dra7xx_mailbox_hwmod_class,
1166 .clkdm_name = "l4cfg_clkdm",
1167 .prcm = {
1168 .omap4 = {
1169 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1170 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1171 },
1172 },
1173};
1174
1175/* mailbox3 */
1176static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1177 .name = "mailbox3",
1178 .class = &dra7xx_mailbox_hwmod_class,
1179 .clkdm_name = "l4cfg_clkdm",
1180 .prcm = {
1181 .omap4 = {
1182 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1183 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1184 },
1185 },
1186};
1187
1188/* mailbox4 */
1189static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1190 .name = "mailbox4",
1191 .class = &dra7xx_mailbox_hwmod_class,
1192 .clkdm_name = "l4cfg_clkdm",
1193 .prcm = {
1194 .omap4 = {
1195 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1196 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1197 },
1198 },
1199};
1200
1201/* mailbox5 */
1202static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1203 .name = "mailbox5",
1204 .class = &dra7xx_mailbox_hwmod_class,
1205 .clkdm_name = "l4cfg_clkdm",
1206 .prcm = {
1207 .omap4 = {
1208 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1209 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1210 },
1211 },
1212};
1213
1214/* mailbox6 */
1215static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1216 .name = "mailbox6",
1217 .class = &dra7xx_mailbox_hwmod_class,
1218 .clkdm_name = "l4cfg_clkdm",
1219 .prcm = {
1220 .omap4 = {
1221 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1222 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1223 },
1224 },
1225};
1226
1227/* mailbox7 */
1228static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1229 .name = "mailbox7",
1230 .class = &dra7xx_mailbox_hwmod_class,
1231 .clkdm_name = "l4cfg_clkdm",
1232 .prcm = {
1233 .omap4 = {
1234 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1235 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1236 },
1237 },
1238};
1239
1240/* mailbox8 */
1241static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1242 .name = "mailbox8",
1243 .class = &dra7xx_mailbox_hwmod_class,
1244 .clkdm_name = "l4cfg_clkdm",
1245 .prcm = {
1246 .omap4 = {
1247 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1248 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1249 },
1250 },
1251};
1252
1253/* mailbox9 */
1254static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1255 .name = "mailbox9",
1256 .class = &dra7xx_mailbox_hwmod_class,
1257 .clkdm_name = "l4cfg_clkdm",
1258 .prcm = {
1259 .omap4 = {
1260 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1261 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1262 },
1263 },
1264};
1265
1266/* mailbox10 */
1267static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1268 .name = "mailbox10",
1269 .class = &dra7xx_mailbox_hwmod_class,
1270 .clkdm_name = "l4cfg_clkdm",
1271 .prcm = {
1272 .omap4 = {
1273 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1274 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1275 },
1276 },
1277};
1278
1279/* mailbox11 */
1280static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1281 .name = "mailbox11",
1282 .class = &dra7xx_mailbox_hwmod_class,
1283 .clkdm_name = "l4cfg_clkdm",
1284 .prcm = {
1285 .omap4 = {
1286 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1287 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1288 },
1289 },
1290};
1291
1292/* mailbox12 */
1293static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1294 .name = "mailbox12",
1295 .class = &dra7xx_mailbox_hwmod_class,
1296 .clkdm_name = "l4cfg_clkdm",
1297 .prcm = {
1298 .omap4 = {
1299 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1300 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1301 },
1302 },
1303};
1304
1305/* mailbox13 */
1306static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1307 .name = "mailbox13",
1308 .class = &dra7xx_mailbox_hwmod_class,
1309 .clkdm_name = "l4cfg_clkdm",
1310 .prcm = {
1311 .omap4 = {
1312 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1313 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1314 },
1315 },
1316};
1317
1318/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1319 * 'mcspi' class
1320 *
1321 */
1322
1323static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1324 .rev_offs = 0x0000,
1325 .sysc_offs = 0x0010,
1326 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1327 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1328 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1329 SIDLE_SMART_WKUP),
1330 .sysc_fields = &omap_hwmod_sysc_type2,
1331};
1332
1333static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1334 .name = "mcspi",
1335 .sysc = &dra7xx_mcspi_sysc,
1336 .rev = OMAP4_MCSPI_REV,
1337};
1338
1339/* mcspi1 */
1340/* mcspi1 dev_attr */
1341static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1342 .num_chipselect = 4,
1343};
1344
1345static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1346 .name = "mcspi1",
1347 .class = &dra7xx_mcspi_hwmod_class,
1348 .clkdm_name = "l4per_clkdm",
1349 .main_clk = "func_48m_fclk",
1350 .prcm = {
1351 .omap4 = {
1352 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1353 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1354 .modulemode = MODULEMODE_SWCTRL,
1355 },
1356 },
1357 .dev_attr = &mcspi1_dev_attr,
1358};
1359
1360/* mcspi2 */
1361/* mcspi2 dev_attr */
1362static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1363 .num_chipselect = 2,
1364};
1365
1366static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1367 .name = "mcspi2",
1368 .class = &dra7xx_mcspi_hwmod_class,
1369 .clkdm_name = "l4per_clkdm",
1370 .main_clk = "func_48m_fclk",
1371 .prcm = {
1372 .omap4 = {
1373 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1374 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1375 .modulemode = MODULEMODE_SWCTRL,
1376 },
1377 },
1378 .dev_attr = &mcspi2_dev_attr,
1379};
1380
1381/* mcspi3 */
1382/* mcspi3 dev_attr */
1383static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1384 .num_chipselect = 2,
1385};
1386
1387static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1388 .name = "mcspi3",
1389 .class = &dra7xx_mcspi_hwmod_class,
1390 .clkdm_name = "l4per_clkdm",
1391 .main_clk = "func_48m_fclk",
1392 .prcm = {
1393 .omap4 = {
1394 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1395 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1396 .modulemode = MODULEMODE_SWCTRL,
1397 },
1398 },
1399 .dev_attr = &mcspi3_dev_attr,
1400};
1401
1402/* mcspi4 */
1403/* mcspi4 dev_attr */
1404static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1405 .num_chipselect = 1,
1406};
1407
1408static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1409 .name = "mcspi4",
1410 .class = &dra7xx_mcspi_hwmod_class,
1411 .clkdm_name = "l4per_clkdm",
1412 .main_clk = "func_48m_fclk",
1413 .prcm = {
1414 .omap4 = {
1415 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1416 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1417 .modulemode = MODULEMODE_SWCTRL,
1418 },
1419 },
1420 .dev_attr = &mcspi4_dev_attr,
1421};
1422
1423/*
Peter Ujfalusi469689a452015-11-12 09:32:59 +0200[diff] [blame]1424 * 'mcasp' class
1425 *
1426 */
1427static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1428 .sysc_offs = 0x0004,
1429 .sysc_flags = SYSC_HAS_SIDLEMODE,
1430 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1431 .sysc_fields = &omap_hwmod_sysc_type3,
1432};
1433
1434static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1435 .name = "mcasp",
1436 .sysc = &dra7xx_mcasp_sysc,
1437};
1438
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]1439/* mcasp1 */
1440static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1441 { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1442 { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1443};
1444
1445static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1446 .name = "mcasp1",
1447 .class = &dra7xx_mcasp_hwmod_class,
1448 .clkdm_name = "ipu_clkdm",
1449 .main_clk = "mcasp1_aux_gfclk_mux",
1450 .flags = HWMOD_OPT_CLKS_NEEDED,
1451 .prcm = {
1452 .omap4 = {
1453 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1454 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1455 .modulemode = MODULEMODE_SWCTRL,
1456 },
1457 },
1458 .opt_clks = mcasp1_opt_clks,
1459 .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks),
1460};
1461
1462/* mcasp2 */
1463static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1464 { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1465 { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1466};
1467
1468static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1469 .name = "mcasp2",
1470 .class = &dra7xx_mcasp_hwmod_class,
1471 .clkdm_name = "l4per2_clkdm",
1472 .main_clk = "mcasp2_aux_gfclk_mux",
1473 .flags = HWMOD_OPT_CLKS_NEEDED,
1474 .prcm = {
1475 .omap4 = {
1476 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1477 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1478 .modulemode = MODULEMODE_SWCTRL,
1479 },
1480 },
1481 .opt_clks = mcasp2_opt_clks,
1482 .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks),
1483};
1484
Peter Ujfalusi469689a452015-11-12 09:32:59 +0200[diff] [blame]1485/* mcasp3 */
1486static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1487 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1488};
1489
1490static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1491 .name = "mcasp3",
1492 .class = &dra7xx_mcasp_hwmod_class,
1493 .clkdm_name = "l4per2_clkdm",
1494 .main_clk = "mcasp3_aux_gfclk_mux",
1495 .flags = HWMOD_OPT_CLKS_NEEDED,
1496 .prcm = {
1497 .omap4 = {
1498 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1499 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1500 .modulemode = MODULEMODE_SWCTRL,
1501 },
1502 },
1503 .opt_clks = mcasp3_opt_clks,
1504 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1505};
1506
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]1507/* mcasp4 */
1508static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1509 { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1510};
1511
1512static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1513 .name = "mcasp4",
1514 .class = &dra7xx_mcasp_hwmod_class,
1515 .clkdm_name = "l4per2_clkdm",
1516 .main_clk = "mcasp4_aux_gfclk_mux",
1517 .flags = HWMOD_OPT_CLKS_NEEDED,
1518 .prcm = {
1519 .omap4 = {
1520 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1521 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1522 .modulemode = MODULEMODE_SWCTRL,
1523 },
1524 },
1525 .opt_clks = mcasp4_opt_clks,
1526 .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks),
1527};
1528
1529/* mcasp5 */
1530static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1531 { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1532};
1533
1534static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1535 .name = "mcasp5",
1536 .class = &dra7xx_mcasp_hwmod_class,
1537 .clkdm_name = "l4per2_clkdm",
1538 .main_clk = "mcasp5_aux_gfclk_mux",
1539 .flags = HWMOD_OPT_CLKS_NEEDED,
1540 .prcm = {
1541 .omap4 = {
1542 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1543 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1544 .modulemode = MODULEMODE_SWCTRL,
1545 },
1546 },
1547 .opt_clks = mcasp5_opt_clks,
1548 .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks),
1549};
1550
1551/* mcasp6 */
1552static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1553 { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1554};
1555
1556static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1557 .name = "mcasp6",
1558 .class = &dra7xx_mcasp_hwmod_class,
1559 .clkdm_name = "l4per2_clkdm",
1560 .main_clk = "mcasp6_aux_gfclk_mux",
1561 .flags = HWMOD_OPT_CLKS_NEEDED,
1562 .prcm = {
1563 .omap4 = {
1564 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1565 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1566 .modulemode = MODULEMODE_SWCTRL,
1567 },
1568 },
1569 .opt_clks = mcasp6_opt_clks,
1570 .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks),
1571};
1572
1573/* mcasp7 */
1574static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1575 { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1576};
1577
1578static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1579 .name = "mcasp7",
1580 .class = &dra7xx_mcasp_hwmod_class,
1581 .clkdm_name = "l4per2_clkdm",
1582 .main_clk = "mcasp7_aux_gfclk_mux",
1583 .flags = HWMOD_OPT_CLKS_NEEDED,
1584 .prcm = {
1585 .omap4 = {
1586 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1587 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1588 .modulemode = MODULEMODE_SWCTRL,
1589 },
1590 },
1591 .opt_clks = mcasp7_opt_clks,
1592 .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks),
1593};
1594
1595/* mcasp8 */
1596static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1597 { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1598};
1599
1600static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1601 .name = "mcasp8",
1602 .class = &dra7xx_mcasp_hwmod_class,
1603 .clkdm_name = "l4per2_clkdm",
1604 .main_clk = "mcasp8_aux_gfclk_mux",
1605 .flags = HWMOD_OPT_CLKS_NEEDED,
1606 .prcm = {
1607 .omap4 = {
1608 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1609 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1610 .modulemode = MODULEMODE_SWCTRL,
1611 },
1612 },
1613 .opt_clks = mcasp8_opt_clks,
1614 .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks),
1615};
1616
Peter Ujfalusi469689a452015-11-12 09:32:59 +0200[diff] [blame]1617/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1618 * 'mmc' class
1619 *
1620 */
1621
1622static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1623 .rev_offs = 0x0000,
1624 .sysc_offs = 0x0010,
1625 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1626 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1627 SYSC_HAS_SOFTRESET),
1628 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1629 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1630 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1631 .sysc_fields = &omap_hwmod_sysc_type2,
1632};
1633
1634static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1635 .name = "mmc",
1636 .sysc = &dra7xx_mmc_sysc,
1637};
1638
1639/* mmc1 */
1640static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1641 { .role = "clk32k", .clk = "mmc1_clk32k" },
1642};
1643
1644/* mmc1 dev_attr */
Andreas Fenkart55143432014-11-08 15:33:09 +0100[diff] [blame]1645static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1646 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1647};
1648
1649static struct omap_hwmod dra7xx_mmc1_hwmod = {
1650 .name = "mmc1",
1651 .class = &dra7xx_mmc_hwmod_class,
1652 .clkdm_name = "l3init_clkdm",
1653 .main_clk = "mmc1_fclk_div",
1654 .prcm = {
1655 .omap4 = {
1656 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1657 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1658 .modulemode = MODULEMODE_SWCTRL,
1659 },
1660 },
1661 .opt_clks = mmc1_opt_clks,
1662 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1663 .dev_attr = &mmc1_dev_attr,
1664};
1665
1666/* mmc2 */
1667static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1668 { .role = "clk32k", .clk = "mmc2_clk32k" },
1669};
1670
1671static struct omap_hwmod dra7xx_mmc2_hwmod = {
1672 .name = "mmc2",
1673 .class = &dra7xx_mmc_hwmod_class,
1674 .clkdm_name = "l3init_clkdm",
1675 .main_clk = "mmc2_fclk_div",
1676 .prcm = {
1677 .omap4 = {
1678 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1679 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1680 .modulemode = MODULEMODE_SWCTRL,
1681 },
1682 },
1683 .opt_clks = mmc2_opt_clks,
1684 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1685};
1686
1687/* mmc3 */
1688static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1689 { .role = "clk32k", .clk = "mmc3_clk32k" },
1690};
1691
1692static struct omap_hwmod dra7xx_mmc3_hwmod = {
1693 .name = "mmc3",
1694 .class = &dra7xx_mmc_hwmod_class,
1695 .clkdm_name = "l4per_clkdm",
1696 .main_clk = "mmc3_gfclk_div",
1697 .prcm = {
1698 .omap4 = {
1699 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1700 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1701 .modulemode = MODULEMODE_SWCTRL,
1702 },
1703 },
1704 .opt_clks = mmc3_opt_clks,
1705 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1706};
1707
1708/* mmc4 */
1709static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1710 { .role = "clk32k", .clk = "mmc4_clk32k" },
1711};
1712
1713static struct omap_hwmod dra7xx_mmc4_hwmod = {
1714 .name = "mmc4",
1715 .class = &dra7xx_mmc_hwmod_class,
1716 .clkdm_name = "l4per_clkdm",
1717 .main_clk = "mmc4_gfclk_div",
1718 .prcm = {
1719 .omap4 = {
1720 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1721 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1722 .modulemode = MODULEMODE_SWCTRL,
1723 },
1724 },
1725 .opt_clks = mmc4_opt_clks,
1726 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1727};
1728
1729/*
1730 * 'mpu' class
1731 *
1732 */
1733
1734static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1735 .name = "mpu",
1736};
1737
1738/* mpu */
1739static struct omap_hwmod dra7xx_mpu_hwmod = {
1740 .name = "mpu",
1741 .class = &dra7xx_mpu_hwmod_class,
1742 .clkdm_name = "mpu_clkdm",
1743 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1744 .main_clk = "dpll_mpu_m2_ck",
1745 .prcm = {
1746 .omap4 = {
1747 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1748 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1749 },
1750 },
1751};
1752
1753/*
1754 * 'ocp2scp' class
1755 *
1756 */
1757
1758static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1759 .rev_offs = 0x0000,
1760 .sysc_offs = 0x0010,
1761 .syss_offs = 0x0014,
1762 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1763 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
Kishon Vijay Abraham I4965be12016-02-09 14:35:43 +0530[diff] [blame]1764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1765 .sysc_fields = &omap_hwmod_sysc_type1,
1766};
1767
1768static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1769 .name = "ocp2scp",
1770 .sysc = &dra7xx_ocp2scp_sysc,
1771};
1772
1773/* ocp2scp1 */
1774static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1775 .name = "ocp2scp1",
1776 .class = &dra7xx_ocp2scp_hwmod_class,
1777 .clkdm_name = "l3init_clkdm",
1778 .main_clk = "l4_root_clk_div",
1779 .prcm = {
1780 .omap4 = {
1781 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1782 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1783 .modulemode = MODULEMODE_HWCTRL,
1784 },
1785 },
1786};
1787
Roger Quadrosdf0d0f12014-07-05 17:44:58 -0600[diff] [blame]1788/* ocp2scp3 */
1789static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1790 .name = "ocp2scp3",
1791 .class = &dra7xx_ocp2scp_hwmod_class,
1792 .clkdm_name = "l3init_clkdm",
1793 .main_clk = "l4_root_clk_div",
1794 .prcm = {
1795 .omap4 = {
1796 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1797 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1798 .modulemode = MODULEMODE_HWCTRL,
1799 },
1800 },
1801};
1802
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1803/*
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1804 * 'PCIE' class
1805 *
1806 */
1807
Sekhar Nori1c96bee2016-02-18 16:49:56 +0530[diff] [blame]1808/*
1809 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1810 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1811 * associated with an IP automatically leaving the driver to handle that
1812 * by itself. This does not work for PCIeSS which needs the reset lines
1813 * deasserted for the driver to start accessing registers.
1814 *
1815 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1816 * lines after asserting them.
1817 */
1818static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1819{
1820 int i;
1821
1822 for (i = 0; i < oh->rst_lines_cnt; i++) {
1823 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1824 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1825 }
1826
1827 return 0;
1828}
1829
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1830static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1831 .name = "pcie",
Sekhar Nori1c96bee2016-02-18 16:49:56 +0530[diff] [blame]1832 .reset = dra7xx_pciess_reset,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1833};
1834
1835/* pcie1 */
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1836static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1837 { .name = "pcie", .rst_shift = 0 },
1838};
1839
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1840static struct omap_hwmod dra7xx_pciess1_hwmod = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1841 .name = "pcie1",
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1842 .class = &dra7xx_pciess_hwmod_class,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1843 .clkdm_name = "pcie_clkdm",
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1844 .rst_lines = dra7xx_pciess1_resets,
1845 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]1846 .main_clk = "l4_root_clk_div",
1847 .prcm = {
1848 .omap4 = {
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]1849 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1850 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]1851 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1852 .modulemode = MODULEMODE_SWCTRL,
1853 },
1854 },
1855};
1856
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1857/* pcie2 */
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1858static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1859 { .name = "pcie", .rst_shift = 1 },
1860};
1861
1862/* pcie2 */
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]1863static struct omap_hwmod dra7xx_pciess2_hwmod = {
1864 .name = "pcie2",
1865 .class = &dra7xx_pciess_hwmod_class,
1866 .clkdm_name = "pcie_clkdm",
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1867 .rst_lines = dra7xx_pciess2_resets,
1868 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]1869 .main_clk = "l4_root_clk_div",
1870 .prcm = {
1871 .omap4 = {
1872 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
Kishon Vijay Abraham I8fe097a2016-01-14 19:41:10 +0530[diff] [blame]1873 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]1874 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1875 .modulemode = MODULEMODE_SWCTRL,
1876 },
1877 },
1878};
1879
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1880/*
1881 * 'qspi' class
1882 *
1883 */
1884
1885static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1886 .sysc_offs = 0x0010,
1887 .sysc_flags = SYSC_HAS_SIDLEMODE,
1888 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1889 SIDLE_SMART_WKUP),
1890 .sysc_fields = &omap_hwmod_sysc_type2,
1891};
1892
1893static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1894 .name = "qspi",
1895 .sysc = &dra7xx_qspi_sysc,
1896};
1897
1898/* qspi */
1899static struct omap_hwmod dra7xx_qspi_hwmod = {
1900 .name = "qspi",
1901 .class = &dra7xx_qspi_hwmod_class,
1902 .clkdm_name = "l4per2_clkdm",
1903 .main_clk = "qspi_gfclk_div",
1904 .prcm = {
1905 .omap4 = {
1906 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1907 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1908 .modulemode = MODULEMODE_SWCTRL,
1909 },
1910 },
1911};
1912
1913/*
Lokesh Vutlac913c8a2014-07-22 13:15:57 -0600[diff] [blame]1914 * 'rtcss' class
1915 *
1916 */
1917static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1918 .sysc_offs = 0x0078,
1919 .sysc_flags = SYSC_HAS_SIDLEMODE,
1920 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1921 SIDLE_SMART_WKUP),
1922 .sysc_fields = &omap_hwmod_sysc_type3,
1923};
1924
1925static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1926 .name = "rtcss",
1927 .sysc = &dra7xx_rtcss_sysc,
Lokesh Vutlad7d31b82016-04-10 13:20:10 -0600[diff] [blame]1928 .unlock = &omap_hwmod_rtc_unlock,
1929 .lock = &omap_hwmod_rtc_lock,
Lokesh Vutlac913c8a2014-07-22 13:15:57 -0600[diff] [blame]1930};
1931
1932/* rtcss */
1933static struct omap_hwmod dra7xx_rtcss_hwmod = {
1934 .name = "rtcss",
1935 .class = &dra7xx_rtcss_hwmod_class,
1936 .clkdm_name = "rtc_clkdm",
1937 .main_clk = "sys_32k_ck",
1938 .prcm = {
1939 .omap4 = {
1940 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1941 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1942 .modulemode = MODULEMODE_SWCTRL,
1943 },
1944 },
1945};
1946
1947/*
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1948 * 'sata' class
1949 *
1950 */
1951
1952static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1953 .sysc_offs = 0x0000,
1954 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1955 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1956 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1957 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1958 .sysc_fields = &omap_hwmod_sysc_type2,
1959};
1960
1961static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1962 .name = "sata",
1963 .sysc = &dra7xx_sata_sysc,
1964};
1965
1966/* sata */
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1967
1968static struct omap_hwmod dra7xx_sata_hwmod = {
1969 .name = "sata",
1970 .class = &dra7xx_sata_hwmod_class,
1971 .clkdm_name = "l3init_clkdm",
1972 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1973 .main_clk = "func_48m_fclk",
Roger Quadros1ea09992014-07-06 15:51:24 -0600[diff] [blame]1974 .mpu_rt_idx = 1,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1975 .prcm = {
1976 .omap4 = {
1977 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1978 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1979 .modulemode = MODULEMODE_SWCTRL,
1980 },
1981 },
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]1982};
1983
1984/*
1985 * 'smartreflex' class
1986 *
1987 */
1988
1989/* The IP is not compliant to type1 / type2 scheme */
1990static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1991 .sidle_shift = 24,
1992 .enwkup_shift = 26,
1993};
1994
1995static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1996 .sysc_offs = 0x0038,
1997 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1998 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1999 SIDLE_SMART_WKUP),
2000 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2001};
2002
2003static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2004 .name = "smartreflex",
2005 .sysc = &dra7xx_smartreflex_sysc,
2006 .rev = 2,
2007};
2008
2009/* smartreflex_core */
2010/* smartreflex_core dev_attr */
2011static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2012 .sensor_voltdm_name = "core",
2013};
2014
2015static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2016 .name = "smartreflex_core",
2017 .class = &dra7xx_smartreflex_hwmod_class,
2018 .clkdm_name = "coreaon_clkdm",
2019 .main_clk = "wkupaon_iclk_mux",
2020 .prcm = {
2021 .omap4 = {
2022 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2023 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2024 .modulemode = MODULEMODE_SWCTRL,
2025 },
2026 },
2027 .dev_attr = &smartreflex_core_dev_attr,
2028};
2029
2030/* smartreflex_mpu */
2031/* smartreflex_mpu dev_attr */
2032static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2033 .sensor_voltdm_name = "mpu",
2034};
2035
2036static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2037 .name = "smartreflex_mpu",
2038 .class = &dra7xx_smartreflex_hwmod_class,
2039 .clkdm_name = "coreaon_clkdm",
2040 .main_clk = "wkupaon_iclk_mux",
2041 .prcm = {
2042 .omap4 = {
2043 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2044 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2045 .modulemode = MODULEMODE_SWCTRL,
2046 },
2047 },
2048 .dev_attr = &smartreflex_mpu_dev_attr,
2049};
2050
2051/*
2052 * 'spinlock' class
2053 *
2054 */
2055
2056static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2057 .rev_offs = 0x0000,
2058 .sysc_offs = 0x0010,
2059 .syss_offs = 0x0014,
Suman Annac317d0f2014-01-10 17:43:08 -0600[diff] [blame]2060 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2061 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2062 SYSS_HAS_RESET_STATUS),
2063 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2064 .sysc_fields = &omap_hwmod_sysc_type1,
2065};
2066
2067static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2068 .name = "spinlock",
2069 .sysc = &dra7xx_spinlock_sysc,
2070};
2071
2072/* spinlock */
2073static struct omap_hwmod dra7xx_spinlock_hwmod = {
2074 .name = "spinlock",
2075 .class = &dra7xx_spinlock_hwmod_class,
2076 .clkdm_name = "l4cfg_clkdm",
2077 .main_clk = "l3_iclk_div",
2078 .prcm = {
2079 .omap4 = {
2080 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2081 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2082 },
2083 },
2084};
2085
2086/*
2087 * 'timer' class
2088 *
2089 * This class contains several variants: ['timer_1ms', 'timer_secure',
2090 * 'timer']
2091 */
2092
2093static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2094 .rev_offs = 0x0000,
2095 .sysc_offs = 0x0010,
2096 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2097 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2098 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2099 SIDLE_SMART_WKUP),
2100 .sysc_fields = &omap_hwmod_sysc_type2,
2101};
2102
2103static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2104 .name = "timer",
2105 .sysc = &dra7xx_timer_1ms_sysc,
2106};
2107
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2108static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2109 .rev_offs = 0x0000,
2110 .sysc_offs = 0x0010,
2111 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2112 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2113 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2114 SIDLE_SMART_WKUP),
2115 .sysc_fields = &omap_hwmod_sysc_type2,
2116};
2117
2118static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2119 .name = "timer",
2120 .sysc = &dra7xx_timer_sysc,
2121};
2122
2123/* timer1 */
2124static struct omap_hwmod dra7xx_timer1_hwmod = {
2125 .name = "timer1",
2126 .class = &dra7xx_timer_1ms_hwmod_class,
2127 .clkdm_name = "wkupaon_clkdm",
2128 .main_clk = "timer1_gfclk_mux",
2129 .prcm = {
2130 .omap4 = {
2131 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2132 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2133 .modulemode = MODULEMODE_SWCTRL,
2134 },
2135 },
2136};
2137
2138/* timer2 */
2139static struct omap_hwmod dra7xx_timer2_hwmod = {
2140 .name = "timer2",
2141 .class = &dra7xx_timer_1ms_hwmod_class,
2142 .clkdm_name = "l4per_clkdm",
2143 .main_clk = "timer2_gfclk_mux",
2144 .prcm = {
2145 .omap4 = {
2146 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2147 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2148 .modulemode = MODULEMODE_SWCTRL,
2149 },
2150 },
2151};
2152
2153/* timer3 */
2154static struct omap_hwmod dra7xx_timer3_hwmod = {
2155 .name = "timer3",
2156 .class = &dra7xx_timer_hwmod_class,
2157 .clkdm_name = "l4per_clkdm",
2158 .main_clk = "timer3_gfclk_mux",
2159 .prcm = {
2160 .omap4 = {
2161 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2162 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2163 .modulemode = MODULEMODE_SWCTRL,
2164 },
2165 },
2166};
2167
2168/* timer4 */
2169static struct omap_hwmod dra7xx_timer4_hwmod = {
2170 .name = "timer4",
Suman Annaedec1782015-03-16 15:54:54 -0500[diff] [blame]2171 .class = &dra7xx_timer_hwmod_class,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2172 .clkdm_name = "l4per_clkdm",
2173 .main_clk = "timer4_gfclk_mux",
2174 .prcm = {
2175 .omap4 = {
2176 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2177 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2178 .modulemode = MODULEMODE_SWCTRL,
2179 },
2180 },
2181};
2182
2183/* timer5 */
2184static struct omap_hwmod dra7xx_timer5_hwmod = {
2185 .name = "timer5",
2186 .class = &dra7xx_timer_hwmod_class,
2187 .clkdm_name = "ipu_clkdm",
2188 .main_clk = "timer5_gfclk_mux",
2189 .prcm = {
2190 .omap4 = {
2191 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2192 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2193 .modulemode = MODULEMODE_SWCTRL,
2194 },
2195 },
2196};
2197
2198/* timer6 */
2199static struct omap_hwmod dra7xx_timer6_hwmod = {
2200 .name = "timer6",
2201 .class = &dra7xx_timer_hwmod_class,
2202 .clkdm_name = "ipu_clkdm",
2203 .main_clk = "timer6_gfclk_mux",
2204 .prcm = {
2205 .omap4 = {
2206 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2207 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2208 .modulemode = MODULEMODE_SWCTRL,
2209 },
2210 },
2211};
2212
2213/* timer7 */
2214static struct omap_hwmod dra7xx_timer7_hwmod = {
2215 .name = "timer7",
2216 .class = &dra7xx_timer_hwmod_class,
2217 .clkdm_name = "ipu_clkdm",
2218 .main_clk = "timer7_gfclk_mux",
2219 .prcm = {
2220 .omap4 = {
2221 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2222 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2223 .modulemode = MODULEMODE_SWCTRL,
2224 },
2225 },
2226};
2227
2228/* timer8 */
2229static struct omap_hwmod dra7xx_timer8_hwmod = {
2230 .name = "timer8",
2231 .class = &dra7xx_timer_hwmod_class,
2232 .clkdm_name = "ipu_clkdm",
2233 .main_clk = "timer8_gfclk_mux",
2234 .prcm = {
2235 .omap4 = {
2236 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2237 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2238 .modulemode = MODULEMODE_SWCTRL,
2239 },
2240 },
2241};
2242
2243/* timer9 */
2244static struct omap_hwmod dra7xx_timer9_hwmod = {
2245 .name = "timer9",
2246 .class = &dra7xx_timer_hwmod_class,
2247 .clkdm_name = "l4per_clkdm",
2248 .main_clk = "timer9_gfclk_mux",
2249 .prcm = {
2250 .omap4 = {
2251 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2252 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2253 .modulemode = MODULEMODE_SWCTRL,
2254 },
2255 },
2256};
2257
2258/* timer10 */
2259static struct omap_hwmod dra7xx_timer10_hwmod = {
2260 .name = "timer10",
2261 .class = &dra7xx_timer_1ms_hwmod_class,
2262 .clkdm_name = "l4per_clkdm",
2263 .main_clk = "timer10_gfclk_mux",
2264 .prcm = {
2265 .omap4 = {
2266 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2267 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2268 .modulemode = MODULEMODE_SWCTRL,
2269 },
2270 },
2271};
2272
2273/* timer11 */
2274static struct omap_hwmod dra7xx_timer11_hwmod = {
2275 .name = "timer11",
2276 .class = &dra7xx_timer_hwmod_class,
2277 .clkdm_name = "l4per_clkdm",
2278 .main_clk = "timer11_gfclk_mux",
2279 .prcm = {
2280 .omap4 = {
2281 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2282 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2283 .modulemode = MODULEMODE_SWCTRL,
2284 },
2285 },
2286};
2287
Suman Anna22d20cb2016-04-10 13:20:11 -0600[diff] [blame]2288/* timer12 */
2289static struct omap_hwmod dra7xx_timer12_hwmod = {
2290 .name = "timer12",
2291 .class = &dra7xx_timer_hwmod_class,
2292 .clkdm_name = "wkupaon_clkdm",
2293 .main_clk = "secure_32k_clk_src_ck",
2294 .prcm = {
2295 .omap4 = {
2296 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2297 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2298 },
2299 },
2300};
2301
Suman Anna1ac964f2015-03-16 15:54:53 -0500[diff] [blame]2302/* timer13 */
2303static struct omap_hwmod dra7xx_timer13_hwmod = {
2304 .name = "timer13",
2305 .class = &dra7xx_timer_hwmod_class,
2306 .clkdm_name = "l4per3_clkdm",
2307 .main_clk = "timer13_gfclk_mux",
2308 .prcm = {
2309 .omap4 = {
2310 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2311 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2312 .modulemode = MODULEMODE_SWCTRL,
2313 },
2314 },
2315};
2316
2317/* timer14 */
2318static struct omap_hwmod dra7xx_timer14_hwmod = {
2319 .name = "timer14",
2320 .class = &dra7xx_timer_hwmod_class,
2321 .clkdm_name = "l4per3_clkdm",
2322 .main_clk = "timer14_gfclk_mux",
2323 .prcm = {
2324 .omap4 = {
2325 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2326 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2327 .modulemode = MODULEMODE_SWCTRL,
2328 },
2329 },
2330};
2331
2332/* timer15 */
2333static struct omap_hwmod dra7xx_timer15_hwmod = {
2334 .name = "timer15",
2335 .class = &dra7xx_timer_hwmod_class,
2336 .clkdm_name = "l4per3_clkdm",
2337 .main_clk = "timer15_gfclk_mux",
2338 .prcm = {
2339 .omap4 = {
2340 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2341 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2342 .modulemode = MODULEMODE_SWCTRL,
2343 },
2344 },
2345};
2346
2347/* timer16 */
2348static struct omap_hwmod dra7xx_timer16_hwmod = {
2349 .name = "timer16",
2350 .class = &dra7xx_timer_hwmod_class,
2351 .clkdm_name = "l4per3_clkdm",
2352 .main_clk = "timer16_gfclk_mux",
2353 .prcm = {
2354 .omap4 = {
2355 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2356 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2357 .modulemode = MODULEMODE_SWCTRL,
2358 },
2359 },
2360};
2361
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2362/*
2363 * 'uart' class
2364 *
2365 */
2366
2367static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2368 .rev_offs = 0x0050,
2369 .sysc_offs = 0x0054,
2370 .syss_offs = 0x0058,
2371 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2372 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2373 SYSS_HAS_RESET_STATUS),
2374 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2375 SIDLE_SMART_WKUP),
2376 .sysc_fields = &omap_hwmod_sysc_type1,
2377};
2378
2379static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2380 .name = "uart",
2381 .sysc = &dra7xx_uart_sysc,
2382};
2383
2384/* uart1 */
2385static struct omap_hwmod dra7xx_uart1_hwmod = {
2386 .name = "uart1",
2387 .class = &dra7xx_uart_hwmod_class,
2388 .clkdm_name = "l4per_clkdm",
2389 .main_clk = "uart1_gfclk_mux",
Rajendra Nayak38958c12013-12-12 15:22:49 +0530[diff] [blame]2390 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2391 .prcm = {
2392 .omap4 = {
2393 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2394 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2395 .modulemode = MODULEMODE_SWCTRL,
2396 },
2397 },
2398};
2399
2400/* uart2 */
2401static struct omap_hwmod dra7xx_uart2_hwmod = {
2402 .name = "uart2",
2403 .class = &dra7xx_uart_hwmod_class,
2404 .clkdm_name = "l4per_clkdm",
2405 .main_clk = "uart2_gfclk_mux",
2406 .flags = HWMOD_SWSUP_SIDLE_ACT,
2407 .prcm = {
2408 .omap4 = {
2409 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2410 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2411 .modulemode = MODULEMODE_SWCTRL,
2412 },
2413 },
2414};
2415
2416/* uart3 */
2417static struct omap_hwmod dra7xx_uart3_hwmod = {
2418 .name = "uart3",
2419 .class = &dra7xx_uart_hwmod_class,
2420 .clkdm_name = "l4per_clkdm",
2421 .main_clk = "uart3_gfclk_mux",
Lokesh Vutla1c7e36b2015-01-08 17:22:04 +0530[diff] [blame]2422 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2423 .prcm = {
2424 .omap4 = {
2425 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2426 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2427 .modulemode = MODULEMODE_SWCTRL,
2428 },
2429 },
2430};
2431
2432/* uart4 */
2433static struct omap_hwmod dra7xx_uart4_hwmod = {
2434 .name = "uart4",
2435 .class = &dra7xx_uart_hwmod_class,
2436 .clkdm_name = "l4per_clkdm",
2437 .main_clk = "uart4_gfclk_mux",
J.D. Schroederb0340852015-10-22 19:24:16 -0500[diff] [blame]2438 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2439 .prcm = {
2440 .omap4 = {
2441 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2442 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2443 .modulemode = MODULEMODE_SWCTRL,
2444 },
2445 },
2446};
2447
2448/* uart5 */
2449static struct omap_hwmod dra7xx_uart5_hwmod = {
2450 .name = "uart5",
2451 .class = &dra7xx_uart_hwmod_class,
2452 .clkdm_name = "l4per_clkdm",
2453 .main_clk = "uart5_gfclk_mux",
2454 .flags = HWMOD_SWSUP_SIDLE_ACT,
2455 .prcm = {
2456 .omap4 = {
2457 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2458 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2459 .modulemode = MODULEMODE_SWCTRL,
2460 },
2461 },
2462};
2463
2464/* uart6 */
2465static struct omap_hwmod dra7xx_uart6_hwmod = {
2466 .name = "uart6",
2467 .class = &dra7xx_uart_hwmod_class,
2468 .clkdm_name = "ipu_clkdm",
2469 .main_clk = "uart6_gfclk_mux",
2470 .flags = HWMOD_SWSUP_SIDLE_ACT,
2471 .prcm = {
2472 .omap4 = {
2473 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2474 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2475 .modulemode = MODULEMODE_SWCTRL,
2476 },
2477 },
2478};
2479
Ambresh K33acc9f2014-10-21 11:17:51 -0500[diff] [blame]2480/* uart7 */
2481static struct omap_hwmod dra7xx_uart7_hwmod = {
2482 .name = "uart7",
2483 .class = &dra7xx_uart_hwmod_class,
2484 .clkdm_name = "l4per2_clkdm",
2485 .main_clk = "uart7_gfclk_mux",
2486 .flags = HWMOD_SWSUP_SIDLE_ACT,
2487 .prcm = {
2488 .omap4 = {
2489 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2490 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2491 .modulemode = MODULEMODE_SWCTRL,
2492 },
2493 },
2494};
2495
2496/* uart8 */
2497static struct omap_hwmod dra7xx_uart8_hwmod = {
2498 .name = "uart8",
2499 .class = &dra7xx_uart_hwmod_class,
2500 .clkdm_name = "l4per2_clkdm",
2501 .main_clk = "uart8_gfclk_mux",
2502 .flags = HWMOD_SWSUP_SIDLE_ACT,
2503 .prcm = {
2504 .omap4 = {
2505 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2506 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2507 .modulemode = MODULEMODE_SWCTRL,
2508 },
2509 },
2510};
2511
2512/* uart9 */
2513static struct omap_hwmod dra7xx_uart9_hwmod = {
2514 .name = "uart9",
2515 .class = &dra7xx_uart_hwmod_class,
2516 .clkdm_name = "l4per2_clkdm",
2517 .main_clk = "uart9_gfclk_mux",
2518 .flags = HWMOD_SWSUP_SIDLE_ACT,
2519 .prcm = {
2520 .omap4 = {
2521 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2522 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2523 .modulemode = MODULEMODE_SWCTRL,
2524 },
2525 },
2526};
2527
2528/* uart10 */
2529static struct omap_hwmod dra7xx_uart10_hwmod = {
2530 .name = "uart10",
2531 .class = &dra7xx_uart_hwmod_class,
2532 .clkdm_name = "wkupaon_clkdm",
2533 .main_clk = "uart10_gfclk_mux",
2534 .flags = HWMOD_SWSUP_SIDLE_ACT,
2535 .prcm = {
2536 .omap4 = {
2537 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2538 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2539 .modulemode = MODULEMODE_SWCTRL,
2540 },
2541 },
2542};
2543
Joel Fernandesc3118642016-10-18 10:55:21 +0300[diff] [blame^]2544/* DES (the 'P' (public) device) */
2545static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2546 .rev_offs = 0x0030,
2547 .sysc_offs = 0x0034,
2548 .syss_offs = 0x0038,
2549 .sysc_flags = SYSS_HAS_RESET_STATUS,
2550};
2551
2552static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2553 .name = "des",
2554 .sysc = &dra7xx_des_sysc,
2555};
2556
2557/* DES */
2558static struct omap_hwmod dra7xx_des_hwmod = {
2559 .name = "des",
2560 .class = &dra7xx_des_hwmod_class,
2561 .clkdm_name = "l4sec_clkdm",
2562 .main_clk = "l3_iclk_div",
2563 .prcm = {
2564 .omap4 = {
2565 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2566 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2567 .modulemode = MODULEMODE_HWCTRL,
2568 },
2569 },
2570};
2571
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2572/*
2573 * 'usb_otg_ss' class
2574 *
2575 */
2576
Roger Quadrosd904b382014-07-06 15:51:24 -0600[diff] [blame]2577static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2578 .rev_offs = 0x0000,
2579 .sysc_offs = 0x0010,
2580 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2581 SYSC_HAS_SIDLEMODE),
2582 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2583 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2584 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2585 .sysc_fields = &omap_hwmod_sysc_type2,
2586};
2587
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2588static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2589 .name = "usb_otg_ss",
Roger Quadrosd904b382014-07-06 15:51:24 -0600[diff] [blame]2590 .sysc = &dra7xx_usb_otg_ss_sysc,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2591};
2592
2593/* usb_otg_ss1 */
2594static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2595 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2596};
2597
2598static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2599 .name = "usb_otg_ss1",
2600 .class = &dra7xx_usb_otg_ss_hwmod_class,
2601 .clkdm_name = "l3init_clkdm",
2602 .main_clk = "dpll_core_h13x2_ck",
2603 .prcm = {
2604 .omap4 = {
2605 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2606 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2607 .modulemode = MODULEMODE_HWCTRL,
2608 },
2609 },
2610 .opt_clks = usb_otg_ss1_opt_clks,
2611 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2612};
2613
2614/* usb_otg_ss2 */
2615static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2616 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2617};
2618
2619static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2620 .name = "usb_otg_ss2",
2621 .class = &dra7xx_usb_otg_ss_hwmod_class,
2622 .clkdm_name = "l3init_clkdm",
2623 .main_clk = "dpll_core_h13x2_ck",
2624 .prcm = {
2625 .omap4 = {
2626 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2627 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2628 .modulemode = MODULEMODE_HWCTRL,
2629 },
2630 },
2631 .opt_clks = usb_otg_ss2_opt_clks,
2632 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2633};
2634
2635/* usb_otg_ss3 */
2636static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2637 .name = "usb_otg_ss3",
2638 .class = &dra7xx_usb_otg_ss_hwmod_class,
2639 .clkdm_name = "l3init_clkdm",
2640 .main_clk = "dpll_core_h13x2_ck",
2641 .prcm = {
2642 .omap4 = {
2643 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2644 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2645 .modulemode = MODULEMODE_HWCTRL,
2646 },
2647 },
2648};
2649
2650/* usb_otg_ss4 */
2651static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2652 .name = "usb_otg_ss4",
2653 .class = &dra7xx_usb_otg_ss_hwmod_class,
2654 .clkdm_name = "l3init_clkdm",
2655 .main_clk = "dpll_core_h13x2_ck",
2656 .prcm = {
2657 .omap4 = {
2658 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2659 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2660 .modulemode = MODULEMODE_HWCTRL,
2661 },
2662 },
2663};
2664
2665/*
2666 * 'vcp' class
2667 *
2668 */
2669
2670static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2671 .name = "vcp",
2672};
2673
2674/* vcp1 */
2675static struct omap_hwmod dra7xx_vcp1_hwmod = {
2676 .name = "vcp1",
2677 .class = &dra7xx_vcp_hwmod_class,
2678 .clkdm_name = "l3main1_clkdm",
2679 .main_clk = "l3_iclk_div",
2680 .prcm = {
2681 .omap4 = {
2682 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2683 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2684 },
2685 },
2686};
2687
2688/* vcp2 */
2689static struct omap_hwmod dra7xx_vcp2_hwmod = {
2690 .name = "vcp2",
2691 .class = &dra7xx_vcp_hwmod_class,
2692 .clkdm_name = "l3main1_clkdm",
2693 .main_clk = "l3_iclk_div",
2694 .prcm = {
2695 .omap4 = {
2696 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2697 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2698 },
2699 },
2700};
2701
2702/*
2703 * 'wd_timer' class
2704 *
2705 */
2706
2707static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2708 .rev_offs = 0x0000,
2709 .sysc_offs = 0x0010,
2710 .syss_offs = 0x0014,
2711 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2712 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2713 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2714 SIDLE_SMART_WKUP),
2715 .sysc_fields = &omap_hwmod_sysc_type1,
2716};
2717
2718static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2719 .name = "wd_timer",
2720 .sysc = &dra7xx_wd_timer_sysc,
2721 .pre_shutdown = &omap2_wd_timer_disable,
2722 .reset = &omap2_wd_timer_reset,
2723};
2724
2725/* wd_timer2 */
2726static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2727 .name = "wd_timer2",
2728 .class = &dra7xx_wd_timer_hwmod_class,
2729 .clkdm_name = "wkupaon_clkdm",
2730 .main_clk = "sys_32k_ck",
2731 .prcm = {
2732 .omap4 = {
2733 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2734 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2735 .modulemode = MODULEMODE_SWCTRL,
2736 },
2737 },
2738};
2739
2740
2741/*
2742 * Interfaces
2743 */
2744
Tomi Valkeinen42121682014-09-15 13:12:18 -0500[diff] [blame]2745/* l3_main_1 -> dmm */
2746static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2747 .master = &dra7xx_l3_main_1_hwmod,
2748 .slave = &dra7xx_dmm_hwmod,
2749 .clk = "l3_iclk_div",
2750 .user = OCP_USER_SDMA,
2751};
2752
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2753/* l3_main_2 -> l3_instr */
2754static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2755 .master = &dra7xx_l3_main_2_hwmod,
2756 .slave = &dra7xx_l3_instr_hwmod,
2757 .clk = "l3_iclk_div",
2758 .user = OCP_USER_MPU | OCP_USER_SDMA,
2759};
2760
2761/* l4_cfg -> l3_main_1 */
2762static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2763 .master = &dra7xx_l4_cfg_hwmod,
2764 .slave = &dra7xx_l3_main_1_hwmod,
2765 .clk = "l3_iclk_div",
2766 .user = OCP_USER_MPU | OCP_USER_SDMA,
2767};
2768
2769/* mpu -> l3_main_1 */
2770static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2771 .master = &dra7xx_mpu_hwmod,
2772 .slave = &dra7xx_l3_main_1_hwmod,
2773 .clk = "l3_iclk_div",
2774 .user = OCP_USER_MPU,
2775};
2776
2777/* l3_main_1 -> l3_main_2 */
2778static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2779 .master = &dra7xx_l3_main_1_hwmod,
2780 .slave = &dra7xx_l3_main_2_hwmod,
2781 .clk = "l3_iclk_div",
2782 .user = OCP_USER_MPU,
2783};
2784
2785/* l4_cfg -> l3_main_2 */
2786static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2787 .master = &dra7xx_l4_cfg_hwmod,
2788 .slave = &dra7xx_l3_main_2_hwmod,
2789 .clk = "l3_iclk_div",
2790 .user = OCP_USER_MPU | OCP_USER_SDMA,
2791};
2792
2793/* l3_main_1 -> l4_cfg */
2794static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2795 .master = &dra7xx_l3_main_1_hwmod,
2796 .slave = &dra7xx_l4_cfg_hwmod,
2797 .clk = "l3_iclk_div",
2798 .user = OCP_USER_MPU | OCP_USER_SDMA,
2799};
2800
2801/* l3_main_1 -> l4_per1 */
2802static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2803 .master = &dra7xx_l3_main_1_hwmod,
2804 .slave = &dra7xx_l4_per1_hwmod,
2805 .clk = "l3_iclk_div",
2806 .user = OCP_USER_MPU | OCP_USER_SDMA,
2807};
2808
2809/* l3_main_1 -> l4_per2 */
2810static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2811 .master = &dra7xx_l3_main_1_hwmod,
2812 .slave = &dra7xx_l4_per2_hwmod,
2813 .clk = "l3_iclk_div",
2814 .user = OCP_USER_MPU | OCP_USER_SDMA,
2815};
2816
2817/* l3_main_1 -> l4_per3 */
2818static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2819 .master = &dra7xx_l3_main_1_hwmod,
2820 .slave = &dra7xx_l4_per3_hwmod,
2821 .clk = "l3_iclk_div",
2822 .user = OCP_USER_MPU | OCP_USER_SDMA,
2823};
2824
2825/* l3_main_1 -> l4_wkup */
2826static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2827 .master = &dra7xx_l3_main_1_hwmod,
2828 .slave = &dra7xx_l4_wkup_hwmod,
2829 .clk = "wkupaon_iclk_mux",
2830 .user = OCP_USER_MPU | OCP_USER_SDMA,
2831};
2832
2833/* l4_per2 -> atl */
2834static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2835 .master = &dra7xx_l4_per2_hwmod,
2836 .slave = &dra7xx_atl_hwmod,
2837 .clk = "l3_iclk_div",
2838 .user = OCP_USER_MPU | OCP_USER_SDMA,
2839};
2840
2841/* l3_main_1 -> bb2d */
2842static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2843 .master = &dra7xx_l3_main_1_hwmod,
2844 .slave = &dra7xx_bb2d_hwmod,
2845 .clk = "l3_iclk_div",
2846 .user = OCP_USER_MPU | OCP_USER_SDMA,
2847};
2848
2849/* l4_wkup -> counter_32k */
2850static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2851 .master = &dra7xx_l4_wkup_hwmod,
2852 .slave = &dra7xx_counter_32k_hwmod,
2853 .clk = "wkupaon_iclk_mux",
2854 .user = OCP_USER_MPU | OCP_USER_SDMA,
2855};
2856
2857/* l4_wkup -> ctrl_module_wkup */
2858static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2859 .master = &dra7xx_l4_wkup_hwmod,
2860 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2861 .clk = "wkupaon_iclk_mux",
2862 .user = OCP_USER_MPU | OCP_USER_SDMA,
2863};
2864
Mugunthan V N077c42f2014-07-08 18:46:39 +0530[diff] [blame]2865static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2866 .master = &dra7xx_l4_per2_hwmod,
2867 .slave = &dra7xx_gmac_hwmod,
2868 .clk = "dpll_gmac_ck",
2869 .user = OCP_USER_MPU,
2870};
2871
2872static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2873 .master = &dra7xx_gmac_hwmod,
2874 .slave = &dra7xx_mdio_hwmod,
2875 .user = OCP_USER_MPU,
2876};
2877
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2878/* l4_wkup -> dcan1 */
2879static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2880 .master = &dra7xx_l4_wkup_hwmod,
2881 .slave = &dra7xx_dcan1_hwmod,
2882 .clk = "wkupaon_iclk_mux",
2883 .user = OCP_USER_MPU | OCP_USER_SDMA,
2884};
2885
2886/* l4_per2 -> dcan2 */
2887static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2888 .master = &dra7xx_l4_per2_hwmod,
2889 .slave = &dra7xx_dcan2_hwmod,
2890 .clk = "l3_iclk_div",
2891 .user = OCP_USER_MPU | OCP_USER_SDMA,
2892};
2893
2894static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2895 {
2896 .pa_start = 0x4a056000,
2897 .pa_end = 0x4a056fff,
2898 .flags = ADDR_TYPE_RT
2899 },
2900 { }
2901};
2902
2903/* l4_cfg -> dma_system */
2904static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2905 .master = &dra7xx_l4_cfg_hwmod,
2906 .slave = &dra7xx_dma_system_hwmod,
2907 .clk = "l3_iclk_div",
2908 .addr = dra7xx_dma_system_addrs,
2909 .user = OCP_USER_MPU | OCP_USER_SDMA,
2910};
2911
Peter Ujfalusi34b41822016-02-25 16:50:18 +0200[diff] [blame]2912/* l3_main_1 -> tpcc */
2913static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2914 .master = &dra7xx_l3_main_1_hwmod,
2915 .slave = &dra7xx_tpcc_hwmod,
2916 .clk = "l3_iclk_div",
2917 .user = OCP_USER_MPU,
2918};
2919
2920/* l3_main_1 -> tptc0 */
2921static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2922 .master = &dra7xx_l3_main_1_hwmod,
2923 .slave = &dra7xx_tptc0_hwmod,
2924 .clk = "l3_iclk_div",
2925 .user = OCP_USER_MPU,
2926};
2927
2928/* l3_main_1 -> tptc1 */
2929static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
2930 .master = &dra7xx_l3_main_1_hwmod,
2931 .slave = &dra7xx_tptc1_hwmod,
2932 .clk = "l3_iclk_div",
2933 .user = OCP_USER_MPU,
2934};
2935
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2936/* l3_main_1 -> dss */
2937static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2938 .master = &dra7xx_l3_main_1_hwmod,
2939 .slave = &dra7xx_dss_hwmod,
2940 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2941 .user = OCP_USER_MPU | OCP_USER_SDMA,
2942};
2943
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2944/* l3_main_1 -> dispc */
2945static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2946 .master = &dra7xx_l3_main_1_hwmod,
2947 .slave = &dra7xx_dss_dispc_hwmod,
2948 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2949 .user = OCP_USER_MPU | OCP_USER_SDMA,
2950};
2951
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2952/* l3_main_1 -> dispc */
2953static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2954 .master = &dra7xx_l3_main_1_hwmod,
2955 .slave = &dra7xx_dss_hdmi_hwmod,
2956 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]2957 .user = OCP_USER_MPU | OCP_USER_SDMA,
2958};
2959
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]2960/* l4_per2 -> mcasp1 */
2961static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
2962 .master = &dra7xx_l4_per2_hwmod,
2963 .slave = &dra7xx_mcasp1_hwmod,
2964 .clk = "l4_root_clk_div",
2965 .user = OCP_USER_MPU | OCP_USER_SDMA,
2966};
2967
2968/* l3_main_1 -> mcasp1 */
2969static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
2970 .master = &dra7xx_l3_main_1_hwmod,
2971 .slave = &dra7xx_mcasp1_hwmod,
2972 .clk = "l3_iclk_div",
2973 .user = OCP_USER_MPU | OCP_USER_SDMA,
2974};
2975
2976/* l4_per2 -> mcasp2 */
2977static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
2978 .master = &dra7xx_l4_per2_hwmod,
2979 .slave = &dra7xx_mcasp2_hwmod,
2980 .clk = "l4_root_clk_div",
2981 .user = OCP_USER_MPU | OCP_USER_SDMA,
2982};
2983
2984/* l3_main_1 -> mcasp2 */
2985static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
2986 .master = &dra7xx_l3_main_1_hwmod,
2987 .slave = &dra7xx_mcasp2_hwmod,
2988 .clk = "l3_iclk_div",
2989 .user = OCP_USER_MPU | OCP_USER_SDMA,
2990};
2991
Peter Ujfalusi469689a452015-11-12 09:32:59 +0200[diff] [blame]2992/* l4_per2 -> mcasp3 */
2993static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
2994 .master = &dra7xx_l4_per2_hwmod,
2995 .slave = &dra7xx_mcasp3_hwmod,
2996 .clk = "l4_root_clk_div",
2997 .user = OCP_USER_MPU | OCP_USER_SDMA,
2998};
2999
3000/* l3_main_1 -> mcasp3 */
3001static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3002 .master = &dra7xx_l3_main_1_hwmod,
3003 .slave = &dra7xx_mcasp3_hwmod,
3004 .clk = "l3_iclk_div",
3005 .user = OCP_USER_MPU | OCP_USER_SDMA,
3006};
3007
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]3008/* l4_per2 -> mcasp4 */
3009static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3010 .master = &dra7xx_l4_per2_hwmod,
3011 .slave = &dra7xx_mcasp4_hwmod,
3012 .clk = "l4_root_clk_div",
3013 .user = OCP_USER_MPU | OCP_USER_SDMA,
3014};
3015
3016/* l4_per2 -> mcasp5 */
3017static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3018 .master = &dra7xx_l4_per2_hwmod,
3019 .slave = &dra7xx_mcasp5_hwmod,
3020 .clk = "l4_root_clk_div",
3021 .user = OCP_USER_MPU | OCP_USER_SDMA,
3022};
3023
3024/* l4_per2 -> mcasp6 */
3025static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3026 .master = &dra7xx_l4_per2_hwmod,
3027 .slave = &dra7xx_mcasp6_hwmod,
3028 .clk = "l4_root_clk_div",
3029 .user = OCP_USER_MPU | OCP_USER_SDMA,
3030};
3031
3032/* l4_per2 -> mcasp7 */
3033static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3034 .master = &dra7xx_l4_per2_hwmod,
3035 .slave = &dra7xx_mcasp7_hwmod,
3036 .clk = "l4_root_clk_div",
3037 .user = OCP_USER_MPU | OCP_USER_SDMA,
3038};
3039
3040/* l4_per2 -> mcasp8 */
3041static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3042 .master = &dra7xx_l4_per2_hwmod,
3043 .slave = &dra7xx_mcasp8_hwmod,
3044 .clk = "l4_root_clk_div",
3045 .user = OCP_USER_MPU | OCP_USER_SDMA,
3046};
3047
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3048/* l4_per1 -> elm */
3049static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3050 .master = &dra7xx_l4_per1_hwmod,
3051 .slave = &dra7xx_elm_hwmod,
3052 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3053 .user = OCP_USER_MPU | OCP_USER_SDMA,
3054};
3055
3056/* l4_wkup -> gpio1 */
3057static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3058 .master = &dra7xx_l4_wkup_hwmod,
3059 .slave = &dra7xx_gpio1_hwmod,
3060 .clk = "wkupaon_iclk_mux",
3061 .user = OCP_USER_MPU | OCP_USER_SDMA,
3062};
3063
3064/* l4_per1 -> gpio2 */
3065static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3066 .master = &dra7xx_l4_per1_hwmod,
3067 .slave = &dra7xx_gpio2_hwmod,
3068 .clk = "l3_iclk_div",
3069 .user = OCP_USER_MPU | OCP_USER_SDMA,
3070};
3071
3072/* l4_per1 -> gpio3 */
3073static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3074 .master = &dra7xx_l4_per1_hwmod,
3075 .slave = &dra7xx_gpio3_hwmod,
3076 .clk = "l3_iclk_div",
3077 .user = OCP_USER_MPU | OCP_USER_SDMA,
3078};
3079
3080/* l4_per1 -> gpio4 */
3081static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3082 .master = &dra7xx_l4_per1_hwmod,
3083 .slave = &dra7xx_gpio4_hwmod,
3084 .clk = "l3_iclk_div",
3085 .user = OCP_USER_MPU | OCP_USER_SDMA,
3086};
3087
3088/* l4_per1 -> gpio5 */
3089static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3090 .master = &dra7xx_l4_per1_hwmod,
3091 .slave = &dra7xx_gpio5_hwmod,
3092 .clk = "l3_iclk_div",
3093 .user = OCP_USER_MPU | OCP_USER_SDMA,
3094};
3095
3096/* l4_per1 -> gpio6 */
3097static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3098 .master = &dra7xx_l4_per1_hwmod,
3099 .slave = &dra7xx_gpio6_hwmod,
3100 .clk = "l3_iclk_div",
3101 .user = OCP_USER_MPU | OCP_USER_SDMA,
3102};
3103
3104/* l4_per1 -> gpio7 */
3105static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3106 .master = &dra7xx_l4_per1_hwmod,
3107 .slave = &dra7xx_gpio7_hwmod,
3108 .clk = "l3_iclk_div",
3109 .user = OCP_USER_MPU | OCP_USER_SDMA,
3110};
3111
3112/* l4_per1 -> gpio8 */
3113static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3114 .master = &dra7xx_l4_per1_hwmod,
3115 .slave = &dra7xx_gpio8_hwmod,
3116 .clk = "l3_iclk_div",
3117 .user = OCP_USER_MPU | OCP_USER_SDMA,
3118};
3119
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3120/* l3_main_1 -> gpmc */
3121static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3122 .master = &dra7xx_l3_main_1_hwmod,
3123 .slave = &dra7xx_gpmc_hwmod,
3124 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3125 .user = OCP_USER_MPU | OCP_USER_SDMA,
3126};
3127
3128static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3129 {
3130 .pa_start = 0x480b2000,
3131 .pa_end = 0x480b201f,
3132 .flags = ADDR_TYPE_RT
3133 },
3134 { }
3135};
3136
3137/* l4_per1 -> hdq1w */
3138static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3139 .master = &dra7xx_l4_per1_hwmod,
3140 .slave = &dra7xx_hdq1w_hwmod,
3141 .clk = "l3_iclk_div",
3142 .addr = dra7xx_hdq1w_addrs,
3143 .user = OCP_USER_MPU | OCP_USER_SDMA,
3144};
3145
3146/* l4_per1 -> i2c1 */
3147static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3148 .master = &dra7xx_l4_per1_hwmod,
3149 .slave = &dra7xx_i2c1_hwmod,
3150 .clk = "l3_iclk_div",
3151 .user = OCP_USER_MPU | OCP_USER_SDMA,
3152};
3153
3154/* l4_per1 -> i2c2 */
3155static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3156 .master = &dra7xx_l4_per1_hwmod,
3157 .slave = &dra7xx_i2c2_hwmod,
3158 .clk = "l3_iclk_div",
3159 .user = OCP_USER_MPU | OCP_USER_SDMA,
3160};
3161
3162/* l4_per1 -> i2c3 */
3163static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3164 .master = &dra7xx_l4_per1_hwmod,
3165 .slave = &dra7xx_i2c3_hwmod,
3166 .clk = "l3_iclk_div",
3167 .user = OCP_USER_MPU | OCP_USER_SDMA,
3168};
3169
3170/* l4_per1 -> i2c4 */
3171static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3172 .master = &dra7xx_l4_per1_hwmod,
3173 .slave = &dra7xx_i2c4_hwmod,
3174 .clk = "l3_iclk_div",
3175 .user = OCP_USER_MPU | OCP_USER_SDMA,
3176};
3177
3178/* l4_per1 -> i2c5 */
3179static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3180 .master = &dra7xx_l4_per1_hwmod,
3181 .slave = &dra7xx_i2c5_hwmod,
3182 .clk = "l3_iclk_div",
3183 .user = OCP_USER_MPU | OCP_USER_SDMA,
3184};
3185
Suman Anna067395d2014-07-11 16:44:39 -0500[diff] [blame]3186/* l4_cfg -> mailbox1 */
3187static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3188 .master = &dra7xx_l4_cfg_hwmod,
3189 .slave = &dra7xx_mailbox1_hwmod,
3190 .clk = "l3_iclk_div",
3191 .user = OCP_USER_MPU | OCP_USER_SDMA,
3192};
3193
3194/* l4_per3 -> mailbox2 */
3195static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3196 .master = &dra7xx_l4_per3_hwmod,
3197 .slave = &dra7xx_mailbox2_hwmod,
3198 .clk = "l3_iclk_div",
3199 .user = OCP_USER_MPU | OCP_USER_SDMA,
3200};
3201
3202/* l4_per3 -> mailbox3 */
3203static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3204 .master = &dra7xx_l4_per3_hwmod,
3205 .slave = &dra7xx_mailbox3_hwmod,
3206 .clk = "l3_iclk_div",
3207 .user = OCP_USER_MPU | OCP_USER_SDMA,
3208};
3209
3210/* l4_per3 -> mailbox4 */
3211static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3212 .master = &dra7xx_l4_per3_hwmod,
3213 .slave = &dra7xx_mailbox4_hwmod,
3214 .clk = "l3_iclk_div",
3215 .user = OCP_USER_MPU | OCP_USER_SDMA,
3216};
3217
3218/* l4_per3 -> mailbox5 */
3219static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3220 .master = &dra7xx_l4_per3_hwmod,
3221 .slave = &dra7xx_mailbox5_hwmod,
3222 .clk = "l3_iclk_div",
3223 .user = OCP_USER_MPU | OCP_USER_SDMA,
3224};
3225
3226/* l4_per3 -> mailbox6 */
3227static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3228 .master = &dra7xx_l4_per3_hwmod,
3229 .slave = &dra7xx_mailbox6_hwmod,
3230 .clk = "l3_iclk_div",
3231 .user = OCP_USER_MPU | OCP_USER_SDMA,
3232};
3233
3234/* l4_per3 -> mailbox7 */
3235static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3236 .master = &dra7xx_l4_per3_hwmod,
3237 .slave = &dra7xx_mailbox7_hwmod,
3238 .clk = "l3_iclk_div",
3239 .user = OCP_USER_MPU | OCP_USER_SDMA,
3240};
3241
3242/* l4_per3 -> mailbox8 */
3243static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3244 .master = &dra7xx_l4_per3_hwmod,
3245 .slave = &dra7xx_mailbox8_hwmod,
3246 .clk = "l3_iclk_div",
3247 .user = OCP_USER_MPU | OCP_USER_SDMA,
3248};
3249
3250/* l4_per3 -> mailbox9 */
3251static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3252 .master = &dra7xx_l4_per3_hwmod,
3253 .slave = &dra7xx_mailbox9_hwmod,
3254 .clk = "l3_iclk_div",
3255 .user = OCP_USER_MPU | OCP_USER_SDMA,
3256};
3257
3258/* l4_per3 -> mailbox10 */
3259static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3260 .master = &dra7xx_l4_per3_hwmod,
3261 .slave = &dra7xx_mailbox10_hwmod,
3262 .clk = "l3_iclk_div",
3263 .user = OCP_USER_MPU | OCP_USER_SDMA,
3264};
3265
3266/* l4_per3 -> mailbox11 */
3267static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3268 .master = &dra7xx_l4_per3_hwmod,
3269 .slave = &dra7xx_mailbox11_hwmod,
3270 .clk = "l3_iclk_div",
3271 .user = OCP_USER_MPU | OCP_USER_SDMA,
3272};
3273
3274/* l4_per3 -> mailbox12 */
3275static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3276 .master = &dra7xx_l4_per3_hwmod,
3277 .slave = &dra7xx_mailbox12_hwmod,
3278 .clk = "l3_iclk_div",
3279 .user = OCP_USER_MPU | OCP_USER_SDMA,
3280};
3281
3282/* l4_per3 -> mailbox13 */
3283static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3284 .master = &dra7xx_l4_per3_hwmod,
3285 .slave = &dra7xx_mailbox13_hwmod,
3286 .clk = "l3_iclk_div",
3287 .user = OCP_USER_MPU | OCP_USER_SDMA,
3288};
3289
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3290/* l4_per1 -> mcspi1 */
3291static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3292 .master = &dra7xx_l4_per1_hwmod,
3293 .slave = &dra7xx_mcspi1_hwmod,
3294 .clk = "l3_iclk_div",
3295 .user = OCP_USER_MPU | OCP_USER_SDMA,
3296};
3297
3298/* l4_per1 -> mcspi2 */
3299static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3300 .master = &dra7xx_l4_per1_hwmod,
3301 .slave = &dra7xx_mcspi2_hwmod,
3302 .clk = "l3_iclk_div",
3303 .user = OCP_USER_MPU | OCP_USER_SDMA,
3304};
3305
3306/* l4_per1 -> mcspi3 */
3307static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3308 .master = &dra7xx_l4_per1_hwmod,
3309 .slave = &dra7xx_mcspi3_hwmod,
3310 .clk = "l3_iclk_div",
3311 .user = OCP_USER_MPU | OCP_USER_SDMA,
3312};
3313
3314/* l4_per1 -> mcspi4 */
3315static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3316 .master = &dra7xx_l4_per1_hwmod,
3317 .slave = &dra7xx_mcspi4_hwmod,
3318 .clk = "l3_iclk_div",
3319 .user = OCP_USER_MPU | OCP_USER_SDMA,
3320};
3321
3322/* l4_per1 -> mmc1 */
3323static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3324 .master = &dra7xx_l4_per1_hwmod,
3325 .slave = &dra7xx_mmc1_hwmod,
3326 .clk = "l3_iclk_div",
3327 .user = OCP_USER_MPU | OCP_USER_SDMA,
3328};
3329
3330/* l4_per1 -> mmc2 */
3331static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3332 .master = &dra7xx_l4_per1_hwmod,
3333 .slave = &dra7xx_mmc2_hwmod,
3334 .clk = "l3_iclk_div",
3335 .user = OCP_USER_MPU | OCP_USER_SDMA,
3336};
3337
3338/* l4_per1 -> mmc3 */
3339static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3340 .master = &dra7xx_l4_per1_hwmod,
3341 .slave = &dra7xx_mmc3_hwmod,
3342 .clk = "l3_iclk_div",
3343 .user = OCP_USER_MPU | OCP_USER_SDMA,
3344};
3345
3346/* l4_per1 -> mmc4 */
3347static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3348 .master = &dra7xx_l4_per1_hwmod,
3349 .slave = &dra7xx_mmc4_hwmod,
3350 .clk = "l3_iclk_div",
3351 .user = OCP_USER_MPU | OCP_USER_SDMA,
3352};
3353
3354/* l4_cfg -> mpu */
3355static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3356 .master = &dra7xx_l4_cfg_hwmod,
3357 .slave = &dra7xx_mpu_hwmod,
3358 .clk = "l3_iclk_div",
3359 .user = OCP_USER_MPU | OCP_USER_SDMA,
3360};
3361
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3362/* l4_cfg -> ocp2scp1 */
3363static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3364 .master = &dra7xx_l4_cfg_hwmod,
3365 .slave = &dra7xx_ocp2scp1_hwmod,
3366 .clk = "l4_root_clk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3367 .user = OCP_USER_MPU | OCP_USER_SDMA,
3368};
3369
Roger Quadrosdf0d0f12014-07-05 17:44:58 -0600[diff] [blame]3370/* l4_cfg -> ocp2scp3 */
3371static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3372 .master = &dra7xx_l4_cfg_hwmod,
3373 .slave = &dra7xx_ocp2scp3_hwmod,
3374 .clk = "l4_root_clk_div",
3375 .user = OCP_USER_MPU | OCP_USER_SDMA,
3376};
3377
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3378/* l3_main_1 -> pciess1 */
3379static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3380 .master = &dra7xx_l3_main_1_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3381 .slave = &dra7xx_pciess1_hwmod,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3382 .clk = "l3_iclk_div",
3383 .user = OCP_USER_MPU | OCP_USER_SDMA,
3384};
3385
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3386/* l4_cfg -> pciess1 */
3387static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3388 .master = &dra7xx_l4_cfg_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3389 .slave = &dra7xx_pciess1_hwmod,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3390 .clk = "l4_root_clk_div",
3391 .user = OCP_USER_MPU | OCP_USER_SDMA,
3392};
3393
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3394/* l3_main_1 -> pciess2 */
3395static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3396 .master = &dra7xx_l3_main_1_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3397 .slave = &dra7xx_pciess2_hwmod,
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3398 .clk = "l3_iclk_div",
3399 .user = OCP_USER_MPU | OCP_USER_SDMA,
3400};
3401
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3402/* l4_cfg -> pciess2 */
3403static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
Kishon Vijay Abraham I8dd3eb72014-07-09 14:32:47 +0530[diff] [blame]3404 .master = &dra7xx_l4_cfg_hwmod,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3405 .slave = &dra7xx_pciess2_hwmod,
Kishon Vijay Abraham I70c18ef72014-06-25 23:32:45 +0530[diff] [blame]3406 .clk = "l4_root_clk_div",
3407 .user = OCP_USER_MPU | OCP_USER_SDMA,
3408};
3409
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3410/* l3_main_1 -> qspi */
3411static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3412 .master = &dra7xx_l3_main_1_hwmod,
3413 .slave = &dra7xx_qspi_hwmod,
3414 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3415 .user = OCP_USER_MPU | OCP_USER_SDMA,
3416};
3417
Lokesh Vutlac913c8a2014-07-22 13:15:57 -0600[diff] [blame]3418/* l4_per3 -> rtcss */
3419static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3420 .master = &dra7xx_l4_per3_hwmod,
3421 .slave = &dra7xx_rtcss_hwmod,
3422 .clk = "l4_root_clk_div",
3423 .user = OCP_USER_MPU | OCP_USER_SDMA,
3424};
3425
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3426static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3427 {
3428 .name = "sysc",
3429 .pa_start = 0x4a141100,
3430 .pa_end = 0x4a141107,
3431 .flags = ADDR_TYPE_RT
3432 },
3433 { }
3434};
3435
3436/* l4_cfg -> sata */
3437static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3438 .master = &dra7xx_l4_cfg_hwmod,
3439 .slave = &dra7xx_sata_hwmod,
3440 .clk = "l3_iclk_div",
3441 .addr = dra7xx_sata_addrs,
3442 .user = OCP_USER_MPU | OCP_USER_SDMA,
3443};
3444
3445static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3446 {
3447 .pa_start = 0x4a0dd000,
3448 .pa_end = 0x4a0dd07f,
3449 .flags = ADDR_TYPE_RT
3450 },
3451 { }
3452};
3453
3454/* l4_cfg -> smartreflex_core */
3455static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3456 .master = &dra7xx_l4_cfg_hwmod,
3457 .slave = &dra7xx_smartreflex_core_hwmod,
3458 .clk = "l4_root_clk_div",
3459 .addr = dra7xx_smartreflex_core_addrs,
3460 .user = OCP_USER_MPU | OCP_USER_SDMA,
3461};
3462
3463static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3464 {
3465 .pa_start = 0x4a0d9000,
3466 .pa_end = 0x4a0d907f,
3467 .flags = ADDR_TYPE_RT
3468 },
3469 { }
3470};
3471
3472/* l4_cfg -> smartreflex_mpu */
3473static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3474 .master = &dra7xx_l4_cfg_hwmod,
3475 .slave = &dra7xx_smartreflex_mpu_hwmod,
3476 .clk = "l4_root_clk_div",
3477 .addr = dra7xx_smartreflex_mpu_addrs,
3478 .user = OCP_USER_MPU | OCP_USER_SDMA,
3479};
3480
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3481/* l4_cfg -> spinlock */
3482static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3483 .master = &dra7xx_l4_cfg_hwmod,
3484 .slave = &dra7xx_spinlock_hwmod,
3485 .clk = "l3_iclk_div",
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3486 .user = OCP_USER_MPU | OCP_USER_SDMA,
3487};
3488
3489/* l4_wkup -> timer1 */
3490static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3491 .master = &dra7xx_l4_wkup_hwmod,
3492 .slave = &dra7xx_timer1_hwmod,
3493 .clk = "wkupaon_iclk_mux",
3494 .user = OCP_USER_MPU | OCP_USER_SDMA,
3495};
3496
3497/* l4_per1 -> timer2 */
3498static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3499 .master = &dra7xx_l4_per1_hwmod,
3500 .slave = &dra7xx_timer2_hwmod,
3501 .clk = "l3_iclk_div",
3502 .user = OCP_USER_MPU | OCP_USER_SDMA,
3503};
3504
3505/* l4_per1 -> timer3 */
3506static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3507 .master = &dra7xx_l4_per1_hwmod,
3508 .slave = &dra7xx_timer3_hwmod,
3509 .clk = "l3_iclk_div",
3510 .user = OCP_USER_MPU | OCP_USER_SDMA,
3511};
3512
3513/* l4_per1 -> timer4 */
3514static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3515 .master = &dra7xx_l4_per1_hwmod,
3516 .slave = &dra7xx_timer4_hwmod,
3517 .clk = "l3_iclk_div",
3518 .user = OCP_USER_MPU | OCP_USER_SDMA,
3519};
3520
3521/* l4_per3 -> timer5 */
3522static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3523 .master = &dra7xx_l4_per3_hwmod,
3524 .slave = &dra7xx_timer5_hwmod,
3525 .clk = "l3_iclk_div",
3526 .user = OCP_USER_MPU | OCP_USER_SDMA,
3527};
3528
3529/* l4_per3 -> timer6 */
3530static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3531 .master = &dra7xx_l4_per3_hwmod,
3532 .slave = &dra7xx_timer6_hwmod,
3533 .clk = "l3_iclk_div",
3534 .user = OCP_USER_MPU | OCP_USER_SDMA,
3535};
3536
3537/* l4_per3 -> timer7 */
3538static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3539 .master = &dra7xx_l4_per3_hwmod,
3540 .slave = &dra7xx_timer7_hwmod,
3541 .clk = "l3_iclk_div",
3542 .user = OCP_USER_MPU | OCP_USER_SDMA,
3543};
3544
3545/* l4_per3 -> timer8 */
3546static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3547 .master = &dra7xx_l4_per3_hwmod,
3548 .slave = &dra7xx_timer8_hwmod,
3549 .clk = "l3_iclk_div",
3550 .user = OCP_USER_MPU | OCP_USER_SDMA,
3551};
3552
3553/* l4_per1 -> timer9 */
3554static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3555 .master = &dra7xx_l4_per1_hwmod,
3556 .slave = &dra7xx_timer9_hwmod,
3557 .clk = "l3_iclk_div",
3558 .user = OCP_USER_MPU | OCP_USER_SDMA,
3559};
3560
3561/* l4_per1 -> timer10 */
3562static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3563 .master = &dra7xx_l4_per1_hwmod,
3564 .slave = &dra7xx_timer10_hwmod,
3565 .clk = "l3_iclk_div",
3566 .user = OCP_USER_MPU | OCP_USER_SDMA,
3567};
3568
3569/* l4_per1 -> timer11 */
3570static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3571 .master = &dra7xx_l4_per1_hwmod,
3572 .slave = &dra7xx_timer11_hwmod,
3573 .clk = "l3_iclk_div",
3574 .user = OCP_USER_MPU | OCP_USER_SDMA,
3575};
3576
Suman Anna22d20cb2016-04-10 13:20:11 -0600[diff] [blame]3577/* l4_wkup -> timer12 */
3578static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3579 .master = &dra7xx_l4_wkup_hwmod,
3580 .slave = &dra7xx_timer12_hwmod,
3581 .clk = "wkupaon_iclk_mux",
3582 .user = OCP_USER_MPU | OCP_USER_SDMA,
3583};
3584
Suman Anna1ac964f2015-03-16 15:54:53 -0500[diff] [blame]3585/* l4_per3 -> timer13 */
3586static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3587 .master = &dra7xx_l4_per3_hwmod,
3588 .slave = &dra7xx_timer13_hwmod,
3589 .clk = "l3_iclk_div",
3590 .user = OCP_USER_MPU | OCP_USER_SDMA,
3591};
3592
3593/* l4_per3 -> timer14 */
3594static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3595 .master = &dra7xx_l4_per3_hwmod,
3596 .slave = &dra7xx_timer14_hwmod,
3597 .clk = "l3_iclk_div",
3598 .user = OCP_USER_MPU | OCP_USER_SDMA,
3599};
3600
3601/* l4_per3 -> timer15 */
3602static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3603 .master = &dra7xx_l4_per3_hwmod,
3604 .slave = &dra7xx_timer15_hwmod,
3605 .clk = "l3_iclk_div",
3606 .user = OCP_USER_MPU | OCP_USER_SDMA,
3607};
3608
3609/* l4_per3 -> timer16 */
3610static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3611 .master = &dra7xx_l4_per3_hwmod,
3612 .slave = &dra7xx_timer16_hwmod,
3613 .clk = "l3_iclk_div",
3614 .user = OCP_USER_MPU | OCP_USER_SDMA,
3615};
3616
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3617/* l4_per1 -> uart1 */
3618static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3619 .master = &dra7xx_l4_per1_hwmod,
3620 .slave = &dra7xx_uart1_hwmod,
3621 .clk = "l3_iclk_div",
3622 .user = OCP_USER_MPU | OCP_USER_SDMA,
3623};
3624
3625/* l4_per1 -> uart2 */
3626static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3627 .master = &dra7xx_l4_per1_hwmod,
3628 .slave = &dra7xx_uart2_hwmod,
3629 .clk = "l3_iclk_div",
3630 .user = OCP_USER_MPU | OCP_USER_SDMA,
3631};
3632
3633/* l4_per1 -> uart3 */
3634static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3635 .master = &dra7xx_l4_per1_hwmod,
3636 .slave = &dra7xx_uart3_hwmod,
3637 .clk = "l3_iclk_div",
3638 .user = OCP_USER_MPU | OCP_USER_SDMA,
3639};
3640
3641/* l4_per1 -> uart4 */
3642static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3643 .master = &dra7xx_l4_per1_hwmod,
3644 .slave = &dra7xx_uart4_hwmod,
3645 .clk = "l3_iclk_div",
3646 .user = OCP_USER_MPU | OCP_USER_SDMA,
3647};
3648
3649/* l4_per1 -> uart5 */
3650static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3651 .master = &dra7xx_l4_per1_hwmod,
3652 .slave = &dra7xx_uart5_hwmod,
3653 .clk = "l3_iclk_div",
3654 .user = OCP_USER_MPU | OCP_USER_SDMA,
3655};
3656
3657/* l4_per1 -> uart6 */
3658static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3659 .master = &dra7xx_l4_per1_hwmod,
3660 .slave = &dra7xx_uart6_hwmod,
3661 .clk = "l3_iclk_div",
3662 .user = OCP_USER_MPU | OCP_USER_SDMA,
3663};
3664
Ambresh K33acc9f2014-10-21 11:17:51 -0500[diff] [blame]3665/* l4_per2 -> uart7 */
3666static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3667 .master = &dra7xx_l4_per2_hwmod,
3668 .slave = &dra7xx_uart7_hwmod,
3669 .clk = "l3_iclk_div",
3670 .user = OCP_USER_MPU | OCP_USER_SDMA,
3671};
3672
Joel Fernandesc3118642016-10-18 10:55:21 +0300[diff] [blame^]3673/* l4_per1 -> des */
3674static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3675 .master = &dra7xx_l4_per1_hwmod,
3676 .slave = &dra7xx_des_hwmod,
3677 .clk = "l3_iclk_div",
3678 .user = OCP_USER_MPU | OCP_USER_SDMA,
3679};
3680
Ambresh K33acc9f2014-10-21 11:17:51 -0500[diff] [blame]3681/* l4_per2 -> uart8 */
3682static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3683 .master = &dra7xx_l4_per2_hwmod,
3684 .slave = &dra7xx_uart8_hwmod,
3685 .clk = "l3_iclk_div",
3686 .user = OCP_USER_MPU | OCP_USER_SDMA,
3687};
3688
3689/* l4_per2 -> uart9 */
3690static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3691 .master = &dra7xx_l4_per2_hwmod,
3692 .slave = &dra7xx_uart9_hwmod,
3693 .clk = "l3_iclk_div",
3694 .user = OCP_USER_MPU | OCP_USER_SDMA,
3695};
3696
3697/* l4_wkup -> uart10 */
3698static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3699 .master = &dra7xx_l4_wkup_hwmod,
3700 .slave = &dra7xx_uart10_hwmod,
3701 .clk = "wkupaon_iclk_mux",
3702 .user = OCP_USER_MPU | OCP_USER_SDMA,
3703};
3704
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3705/* l4_per3 -> usb_otg_ss1 */
3706static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3707 .master = &dra7xx_l4_per3_hwmod,
3708 .slave = &dra7xx_usb_otg_ss1_hwmod,
3709 .clk = "dpll_core_h13x2_ck",
3710 .user = OCP_USER_MPU | OCP_USER_SDMA,
3711};
3712
3713/* l4_per3 -> usb_otg_ss2 */
3714static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3715 .master = &dra7xx_l4_per3_hwmod,
3716 .slave = &dra7xx_usb_otg_ss2_hwmod,
3717 .clk = "dpll_core_h13x2_ck",
3718 .user = OCP_USER_MPU | OCP_USER_SDMA,
3719};
3720
3721/* l4_per3 -> usb_otg_ss3 */
3722static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3723 .master = &dra7xx_l4_per3_hwmod,
3724 .slave = &dra7xx_usb_otg_ss3_hwmod,
3725 .clk = "dpll_core_h13x2_ck",
3726 .user = OCP_USER_MPU | OCP_USER_SDMA,
3727};
3728
3729/* l4_per3 -> usb_otg_ss4 */
3730static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3731 .master = &dra7xx_l4_per3_hwmod,
3732 .slave = &dra7xx_usb_otg_ss4_hwmod,
3733 .clk = "dpll_core_h13x2_ck",
3734 .user = OCP_USER_MPU | OCP_USER_SDMA,
3735};
3736
3737/* l3_main_1 -> vcp1 */
3738static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3739 .master = &dra7xx_l3_main_1_hwmod,
3740 .slave = &dra7xx_vcp1_hwmod,
3741 .clk = "l3_iclk_div",
3742 .user = OCP_USER_MPU | OCP_USER_SDMA,
3743};
3744
3745/* l4_per2 -> vcp1 */
3746static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3747 .master = &dra7xx_l4_per2_hwmod,
3748 .slave = &dra7xx_vcp1_hwmod,
3749 .clk = "l3_iclk_div",
3750 .user = OCP_USER_MPU | OCP_USER_SDMA,
3751};
3752
3753/* l3_main_1 -> vcp2 */
3754static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3755 .master = &dra7xx_l3_main_1_hwmod,
3756 .slave = &dra7xx_vcp2_hwmod,
3757 .clk = "l3_iclk_div",
3758 .user = OCP_USER_MPU | OCP_USER_SDMA,
3759};
3760
3761/* l4_per2 -> vcp2 */
3762static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3763 .master = &dra7xx_l4_per2_hwmod,
3764 .slave = &dra7xx_vcp2_hwmod,
3765 .clk = "l3_iclk_div",
3766 .user = OCP_USER_MPU | OCP_USER_SDMA,
3767};
3768
3769/* l4_wkup -> wd_timer2 */
3770static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3771 .master = &dra7xx_l4_wkup_hwmod,
3772 .slave = &dra7xx_wd_timer2_hwmod,
3773 .clk = "wkupaon_iclk_mux",
3774 .user = OCP_USER_MPU | OCP_USER_SDMA,
3775};
3776
Vignesh Rb05ff3c2016-04-10 13:20:09 -0600[diff] [blame]3777/* l4_per2 -> epwmss0 */
3778static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3779 .master = &dra7xx_l4_per2_hwmod,
3780 .slave = &dra7xx_epwmss0_hwmod,
3781 .clk = "l4_root_clk_div",
3782 .user = OCP_USER_MPU,
3783};
3784
3785/* l4_per2 -> epwmss1 */
3786static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3787 .master = &dra7xx_l4_per2_hwmod,
3788 .slave = &dra7xx_epwmss1_hwmod,
3789 .clk = "l4_root_clk_div",
3790 .user = OCP_USER_MPU,
3791};
3792
3793/* l4_per2 -> epwmss2 */
3794static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3795 .master = &dra7xx_l4_per2_hwmod,
3796 .slave = &dra7xx_epwmss2_hwmod,
3797 .clk = "l4_root_clk_div",
3798 .user = OCP_USER_MPU,
3799};
3800
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3801static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
Tomi Valkeinen42121682014-09-15 13:12:18 -0500[diff] [blame]3802 &dra7xx_l3_main_1__dmm,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3803 &dra7xx_l3_main_2__l3_instr,
3804 &dra7xx_l4_cfg__l3_main_1,
3805 &dra7xx_mpu__l3_main_1,
3806 &dra7xx_l3_main_1__l3_main_2,
3807 &dra7xx_l4_cfg__l3_main_2,
3808 &dra7xx_l3_main_1__l4_cfg,
3809 &dra7xx_l3_main_1__l4_per1,
3810 &dra7xx_l3_main_1__l4_per2,
3811 &dra7xx_l3_main_1__l4_per3,
3812 &dra7xx_l3_main_1__l4_wkup,
3813 &dra7xx_l4_per2__atl,
3814 &dra7xx_l3_main_1__bb2d,
3815 &dra7xx_l4_wkup__counter_32k,
3816 &dra7xx_l4_wkup__ctrl_module_wkup,
3817 &dra7xx_l4_wkup__dcan1,
3818 &dra7xx_l4_per2__dcan2,
Mugunthan V N077c42f2014-07-08 18:46:39 +0530[diff] [blame]3819 &dra7xx_l4_per2__cpgmac0,
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]3820 &dra7xx_l4_per2__mcasp1,
3821 &dra7xx_l3_main_1__mcasp1,
3822 &dra7xx_l4_per2__mcasp2,
3823 &dra7xx_l3_main_1__mcasp2,
Peter Ujfalusi469689a452015-11-12 09:32:59 +0200[diff] [blame]3824 &dra7xx_l4_per2__mcasp3,
3825 &dra7xx_l3_main_1__mcasp3,
Peter Ujfalusi9ad4d9a2016-04-10 13:20:09 -0600[diff] [blame]3826 &dra7xx_l4_per2__mcasp4,
3827 &dra7xx_l4_per2__mcasp5,
3828 &dra7xx_l4_per2__mcasp6,
3829 &dra7xx_l4_per2__mcasp7,
3830 &dra7xx_l4_per2__mcasp8,
Mugunthan V N077c42f2014-07-08 18:46:39 +0530[diff] [blame]3831 &dra7xx_gmac__mdio,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3832 &dra7xx_l4_cfg__dma_system,
Peter Ujfalusi34b41822016-02-25 16:50:18 +0200[diff] [blame]3833 &dra7xx_l3_main_1__tpcc,
3834 &dra7xx_l3_main_1__tptc0,
3835 &dra7xx_l3_main_1__tptc1,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3836 &dra7xx_l3_main_1__dss,
3837 &dra7xx_l3_main_1__dispc,
3838 &dra7xx_l3_main_1__hdmi,
3839 &dra7xx_l4_per1__elm,
3840 &dra7xx_l4_wkup__gpio1,
3841 &dra7xx_l4_per1__gpio2,
3842 &dra7xx_l4_per1__gpio3,
3843 &dra7xx_l4_per1__gpio4,
3844 &dra7xx_l4_per1__gpio5,
3845 &dra7xx_l4_per1__gpio6,
3846 &dra7xx_l4_per1__gpio7,
3847 &dra7xx_l4_per1__gpio8,
3848 &dra7xx_l3_main_1__gpmc,
3849 &dra7xx_l4_per1__hdq1w,
3850 &dra7xx_l4_per1__i2c1,
3851 &dra7xx_l4_per1__i2c2,
3852 &dra7xx_l4_per1__i2c3,
3853 &dra7xx_l4_per1__i2c4,
3854 &dra7xx_l4_per1__i2c5,
Suman Anna067395d2014-07-11 16:44:39 -0500[diff] [blame]3855 &dra7xx_l4_cfg__mailbox1,
3856 &dra7xx_l4_per3__mailbox2,
3857 &dra7xx_l4_per3__mailbox3,
3858 &dra7xx_l4_per3__mailbox4,
3859 &dra7xx_l4_per3__mailbox5,
3860 &dra7xx_l4_per3__mailbox6,
3861 &dra7xx_l4_per3__mailbox7,
3862 &dra7xx_l4_per3__mailbox8,
3863 &dra7xx_l4_per3__mailbox9,
3864 &dra7xx_l4_per3__mailbox10,
3865 &dra7xx_l4_per3__mailbox11,
3866 &dra7xx_l4_per3__mailbox12,
3867 &dra7xx_l4_per3__mailbox13,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3868 &dra7xx_l4_per1__mcspi1,
3869 &dra7xx_l4_per1__mcspi2,
3870 &dra7xx_l4_per1__mcspi3,
3871 &dra7xx_l4_per1__mcspi4,
3872 &dra7xx_l4_per1__mmc1,
3873 &dra7xx_l4_per1__mmc2,
3874 &dra7xx_l4_per1__mmc3,
3875 &dra7xx_l4_per1__mmc4,
3876 &dra7xx_l4_cfg__mpu,
3877 &dra7xx_l4_cfg__ocp2scp1,
Roger Quadrosdf0d0f12014-07-05 17:44:58 -0600[diff] [blame]3878 &dra7xx_l4_cfg__ocp2scp3,
Kishon Vijay Abraham I07171032015-02-20 14:21:13 +0530[diff] [blame]3879 &dra7xx_l3_main_1__pciess1,
3880 &dra7xx_l4_cfg__pciess1,
3881 &dra7xx_l3_main_1__pciess2,
3882 &dra7xx_l4_cfg__pciess2,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3883 &dra7xx_l3_main_1__qspi,
Lokesh Vutlac913c8a2014-07-22 13:15:57 -0600[diff] [blame]3884 &dra7xx_l4_per3__rtcss,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3885 &dra7xx_l4_cfg__sata,
3886 &dra7xx_l4_cfg__smartreflex_core,
3887 &dra7xx_l4_cfg__smartreflex_mpu,
3888 &dra7xx_l4_cfg__spinlock,
3889 &dra7xx_l4_wkup__timer1,
3890 &dra7xx_l4_per1__timer2,
3891 &dra7xx_l4_per1__timer3,
3892 &dra7xx_l4_per1__timer4,
3893 &dra7xx_l4_per3__timer5,
3894 &dra7xx_l4_per3__timer6,
3895 &dra7xx_l4_per3__timer7,
3896 &dra7xx_l4_per3__timer8,
3897 &dra7xx_l4_per1__timer9,
3898 &dra7xx_l4_per1__timer10,
3899 &dra7xx_l4_per1__timer11,
Suman Anna1ac964f2015-03-16 15:54:53 -0500[diff] [blame]3900 &dra7xx_l4_per3__timer13,
3901 &dra7xx_l4_per3__timer14,
3902 &dra7xx_l4_per3__timer15,
3903 &dra7xx_l4_per3__timer16,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3904 &dra7xx_l4_per1__uart1,
3905 &dra7xx_l4_per1__uart2,
3906 &dra7xx_l4_per1__uart3,
3907 &dra7xx_l4_per1__uart4,
3908 &dra7xx_l4_per1__uart5,
3909 &dra7xx_l4_per1__uart6,
Ambresh K33acc9f2014-10-21 11:17:51 -0500[diff] [blame]3910 &dra7xx_l4_per2__uart7,
3911 &dra7xx_l4_per2__uart8,
3912 &dra7xx_l4_per2__uart9,
3913 &dra7xx_l4_wkup__uart10,
Joel Fernandesc3118642016-10-18 10:55:21 +0300[diff] [blame^]3914 &dra7xx_l4_per1__des,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3915 &dra7xx_l4_per3__usb_otg_ss1,
3916 &dra7xx_l4_per3__usb_otg_ss2,
3917 &dra7xx_l4_per3__usb_otg_ss3,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3918 &dra7xx_l3_main_1__vcp1,
3919 &dra7xx_l4_per2__vcp1,
3920 &dra7xx_l3_main_1__vcp2,
3921 &dra7xx_l4_per2__vcp2,
3922 &dra7xx_l4_wkup__wd_timer2,
Vignesh Rb05ff3c2016-04-10 13:20:09 -0600[diff] [blame]3923 &dra7xx_l4_per2__epwmss0,
3924 &dra7xx_l4_per2__epwmss1,
3925 &dra7xx_l4_per2__epwmss2,
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3926 NULL,
3927};
3928
Suman Anna22d20cb2016-04-10 13:20:11 -0600[diff] [blame]3929/* GP-only hwmod links */
3930static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
3931 &dra7xx_l4_wkup__timer12,
3932 NULL,
3933};
3934
3935/* SoC variant specific hwmod links */
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]3936static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3937 &dra7xx_l4_per3__usb_otg_ss4,
3938 NULL,
3939};
3940
3941static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3942 NULL,
3943};
3944
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3945int __init dra7xx_hwmod_init(void)
3946{
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]3947 int ret;
3948
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3949 omap_hwmod_init();
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]3950 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3951
3952 if (!ret && soc_is_dra74x())
Suman Anna22d20cb2016-04-10 13:20:11 -0600[diff] [blame]3953 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]3954 else if (!ret && soc_is_dra72x())
Suman Anna22d20cb2016-04-10 13:20:11 -0600[diff] [blame]3955 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3956
3957 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
3958 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
Rajendra Nayakf7f7a292014-08-27 19:38:23 -0600[diff] [blame]3959
3960 return ret;
Ambresh K90020c72013-07-09 13:02:16 +0530[diff] [blame]3961}