blob: 986d608002a36b60ef543d81e84bfe625032964f [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#define CURSOR_WIDTH 64
31#define CURSOR_HEIGHT 64
32
33static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
34{
35 struct radeon_device *rdev = crtc->dev->dev_private;
36 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
37 uint32_t cur_lock;
38
Alex Deucherbcc1c2a2010-01-12 17:54:34 -050039 if (ASIC_IS_DCE4(rdev)) {
40 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
41 if (lock)
42 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
43 else
44 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
45 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
46 } else if (ASIC_IS_AVIVO(rdev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +020047 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
48 if (lock)
49 cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
50 else
51 cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
52 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
53 } else {
54 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
55 if (lock)
56 cur_lock |= RADEON_CUR_LOCK;
57 else
58 cur_lock &= ~RADEON_CUR_LOCK;
59 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
60 }
61}
62
63static void radeon_hide_cursor(struct drm_crtc *crtc)
64{
65 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
66 struct radeon_device *rdev = crtc->dev->dev_private;
67
Alex Deucherbcc1c2a2010-01-12 17:54:34 -050068 if (ASIC_IS_DCE4(rdev)) {
69 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
70 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
71 } else if (ASIC_IS_AVIVO(rdev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +020072 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
73 WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
74 } else {
75 switch (radeon_crtc->crtc_id) {
76 case 0:
77 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
78 break;
79 case 1:
80 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
81 break;
82 default:
83 return;
84 }
85 WREG32_P(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
86 }
87}
88
89static void radeon_show_cursor(struct drm_crtc *crtc)
90{
91 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
92 struct radeon_device *rdev = crtc->dev->dev_private;
93
Alex Deucherbcc1c2a2010-01-12 17:54:34 -050094 if (ASIC_IS_DCE4(rdev)) {
95 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
96 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
97 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
98 } else if (ASIC_IS_AVIVO(rdev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +020099 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
100 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500101 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200102 } else {
103 switch (radeon_crtc->crtc_id) {
104 case 0:
105 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
106 break;
107 case 1:
108 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
109 break;
110 default:
111 return;
112 }
113
114 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
115 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
116 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
117 }
118}
119
120static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
Alex Deucherf981d462010-09-30 19:16:03 -0400121 uint64_t gpu_addr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200122{
123 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
124 struct radeon_device *rdev = crtc->dev->dev_private;
125
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500126 if (ASIC_IS_DCE4(rdev)) {
Alex Deucherf981d462010-09-30 19:16:03 -0400127 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
128 upper_32_bits(gpu_addr));
129 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
130 gpu_addr & 0xffffffff);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500131 } else if (ASIC_IS_AVIVO(rdev)) {
Alex Deucherc290dad2009-10-22 16:12:34 -0400132 if (rdev->family >= CHIP_RV770) {
133 if (radeon_crtc->crtc_id)
Alex Deucherf981d462010-09-30 19:16:03 -0400134 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
Alex Deucherc290dad2009-10-22 16:12:34 -0400135 else
Alex Deucherf981d462010-09-30 19:16:03 -0400136 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
Alex Deucherc290dad2009-10-22 16:12:34 -0400137 }
Alex Deucherf981d462010-09-30 19:16:03 -0400138 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
139 gpu_addr & 0xffffffff);
Alex Deucherc290dad2009-10-22 16:12:34 -0400140 } else {
Alex Deucherc836e862009-07-13 13:51:03 -0400141 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200142 /* offset is from DISP(2)_BASE_ADDRESS */
Alex Deucherc836e862009-07-13 13:51:03 -0400143 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
144 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200145}
146
147int radeon_crtc_cursor_set(struct drm_crtc *crtc,
148 struct drm_file *file_priv,
149 uint32_t handle,
150 uint32_t width,
151 uint32_t height)
152{
153 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
Michel Dänzerc4353012012-03-14 17:12:41 +0100154 struct radeon_device *rdev = crtc->dev->dev_private;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200155 struct drm_gem_object *obj;
Michel Dänzerc4353012012-03-14 17:12:41 +0100156 struct radeon_bo *robj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200157 uint64_t gpu_addr;
158 int ret;
159
160 if (!handle) {
161 /* turn off cursor */
162 radeon_hide_cursor(crtc);
163 obj = NULL;
164 goto unpin;
165 }
166
167 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
168 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
169 return -EINVAL;
170 }
171
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200172 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
173 if (!obj) {
174 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
Chris Wilsonbf79cb92010-08-04 14:19:46 +0100175 return -ENOENT;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200176 }
177
Michel Dänzerc4353012012-03-14 17:12:41 +0100178 robj = gem_to_radeon_bo(obj);
179 ret = radeon_bo_reserve(robj, false);
180 if (unlikely(ret != 0))
181 goto fail;
182 /* Only 27 bit offset for legacy cursor */
183 ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
184 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
185 &gpu_addr);
186 radeon_bo_unreserve(robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200187 if (ret)
188 goto fail;
189
Ilija Hadzic45e5f6a2011-05-04 20:15:03 -0400190 radeon_crtc->cursor_width = width;
191 radeon_crtc->cursor_height = height;
192
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200193 radeon_lock_cursor(crtc, true);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200194 radeon_set_cursor(crtc, obj, gpu_addr);
195 radeon_show_cursor(crtc);
196 radeon_lock_cursor(crtc, false);
197
198unpin:
199 if (radeon_crtc->cursor_bo) {
200 radeon_gem_object_unpin(radeon_crtc->cursor_bo);
Luca Barbieribc9025b2010-02-09 05:49:12 +0000201 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200202 }
203
204 radeon_crtc->cursor_bo = obj;
205 return 0;
206fail:
Luca Barbieribc9025b2010-02-09 05:49:12 +0000207 drm_gem_object_unreference_unlocked(obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200208
Matt Turner4cdb82b2010-06-19 14:13:45 -0400209 return ret;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200210}
211
212int radeon_crtc_cursor_move(struct drm_crtc *crtc,
213 int x, int y)
214{
215 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
216 struct radeon_device *rdev = crtc->dev->dev_private;
217 int xorigin = 0, yorigin = 0;
Alex Deucher6a2a11d2010-10-14 17:14:57 -0400218 int w = radeon_crtc->cursor_width;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200219
Michel Dänzerb8aee292011-09-30 17:16:52 +0200220 if (ASIC_IS_AVIVO(rdev)) {
221 /* avivo cursor are offset into the total surface */
222 x += crtc->x;
223 y += crtc->y;
224 }
225 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
226
Michel Dänzer02e68592011-09-30 17:16:53 +0200227 if (x < 0) {
Michel Dänzer7d309522011-09-30 17:16:51 +0200228 xorigin = min(-x, CURSOR_WIDTH - 1);
Michel Dänzer02e68592011-09-30 17:16:53 +0200229 x = 0;
230 }
231 if (y < 0) {
Michel Dänzer7d309522011-09-30 17:16:51 +0200232 yorigin = min(-y, CURSOR_HEIGHT - 1);
Michel Dänzer02e68592011-09-30 17:16:53 +0200233 y = 0;
234 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200235
Alex Deucher6a2a11d2010-10-14 17:14:57 -0400236 if (ASIC_IS_AVIVO(rdev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200237 int i = 0;
238 struct drm_crtc *crtc_p;
239
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300240 /* avivo cursor image can't end on 128 pixel boundary or
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200241 * go past the end of the frame if both crtcs are enabled
242 */
243 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
244 if (crtc_p->enabled)
245 i++;
246 }
247 if (i > 1) {
248 int cursor_end, frame_end;
249
250 cursor_end = x - xorigin + w;
251 frame_end = crtc->x + crtc->mode.crtc_hdisplay;
252 if (cursor_end >= frame_end) {
253 w = w - (cursor_end - frame_end);
254 if (!(frame_end & 0x7f))
255 w--;
256 } else {
257 if (!(cursor_end & 0x7f))
258 w--;
259 }
260 if (w <= 0)
261 w = 1;
262 }
Alex Deucher6a2a11d2010-10-14 17:14:57 -0400263 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200264
Alex Deucher6a2a11d2010-10-14 17:14:57 -0400265 radeon_lock_cursor(crtc, true);
266 if (ASIC_IS_DCE4(rdev)) {
Michel Dänzer02e68592011-09-30 17:16:53 +0200267 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
Alex Deucher6a2a11d2010-10-14 17:14:57 -0400268 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
269 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
270 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
271 } else if (ASIC_IS_AVIVO(rdev)) {
Michel Dänzer02e68592011-09-30 17:16:53 +0200272 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200273 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
274 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
275 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
276 } else {
277 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
278 y *= 2;
279
280 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
281 (RADEON_CUR_LOCK
282 | (xorigin << 16)
283 | yorigin));
284 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
285 (RADEON_CUR_LOCK
Michel Dänzer02e68592011-09-30 17:16:53 +0200286 | (x << 16)
287 | y));
Alex Deucherc836e862009-07-13 13:51:03 -0400288 /* offset is from DISP(2)_BASE_ADDRESS */
289 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
290 (yorigin * 256)));
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200291 }
292 radeon_lock_cursor(crtc, false);
293
294 return 0;
295}