Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 1 | /* |
Juergen Beisert | 259bcaa | 2008-07-05 10:02:54 +0200 | [diff] [blame] | 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 17 | * MA 02110-1301, USA. |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 18 | */ |
| 19 | |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 20 | #include <linux/module.h> |
Juergen Beisert | 259bcaa | 2008-07-05 10:02:54 +0200 | [diff] [blame] | 21 | #include <linux/irq.h> |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 22 | #include <linux/irqdomain.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 23 | #include <linux/io.h> |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 24 | #include <linux/of.h> |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 25 | #include <asm/mach/irq.h> |
Jason Liu | 98de0cb | 2011-11-03 17:31:26 +0800 | [diff] [blame] | 26 | #include <asm/exception.h> |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 27 | |
Shawn Guo | e337247 | 2012-09-13 21:01:00 +0800 | [diff] [blame] | 28 | #include "common.h" |
Shawn Guo | 50f2de6 | 2012-09-14 14:14:45 +0800 | [diff] [blame] | 29 | #include "hardware.h" |
Peter Horton | cdc3f10 | 2010-12-06 11:37:38 +0000 | [diff] [blame] | 30 | #include "irq-common.h" |
| 31 | |
Sascha Hauer | 84c9fa4 | 2009-02-18 20:59:04 +0100 | [diff] [blame] | 32 | #define AVIC_INTCNTL 0x00 /* int control reg */ |
| 33 | #define AVIC_NIMASK 0x04 /* int mask reg */ |
| 34 | #define AVIC_INTENNUM 0x08 /* int enable number reg */ |
| 35 | #define AVIC_INTDISNUM 0x0C /* int disable number reg */ |
| 36 | #define AVIC_INTENABLEH 0x10 /* int enable reg high */ |
| 37 | #define AVIC_INTENABLEL 0x14 /* int enable reg low */ |
| 38 | #define AVIC_INTTYPEH 0x18 /* int type reg high */ |
| 39 | #define AVIC_INTTYPEL 0x1C /* int type reg low */ |
| 40 | #define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ |
| 41 | #define AVIC_NIVECSR 0x40 /* norm int vector/status */ |
| 42 | #define AVIC_FIVECSR 0x44 /* fast int vector/status */ |
| 43 | #define AVIC_INTSRCH 0x48 /* int source reg high */ |
| 44 | #define AVIC_INTSRCL 0x4C /* int source reg low */ |
| 45 | #define AVIC_INTFRCH 0x50 /* int force reg high */ |
| 46 | #define AVIC_INTFRCL 0x54 /* int force reg low */ |
| 47 | #define AVIC_NIPNDH 0x58 /* norm int pending high */ |
| 48 | #define AVIC_NIPNDL 0x5C /* norm int pending low */ |
| 49 | #define AVIC_FIPNDH 0x60 /* fast int pending high */ |
| 50 | #define AVIC_FIPNDL 0x64 /* fast int pending low */ |
| 51 | |
Sascha Hauer | 5a24d69 | 2011-05-10 18:16:10 +0200 | [diff] [blame] | 52 | #define AVIC_NUM_IRQS 64 |
| 53 | |
Fabio Estevam | ae00ac7 | 2013-03-25 09:20:40 -0300 | [diff] [blame] | 54 | static void __iomem *avic_base; |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 55 | static struct irq_domain *domain; |
Juergen Beisert | 259bcaa | 2008-07-05 10:02:54 +0200 | [diff] [blame] | 56 | |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 57 | #ifdef CONFIG_FIQ |
Peter Horton | cdc3f10 | 2010-12-06 11:37:38 +0000 | [diff] [blame] | 58 | static int avic_set_irq_fiq(unsigned int irq, unsigned int type) |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 59 | { |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 60 | struct irq_data *d = irq_get_irq_data(irq); |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 61 | unsigned int irqt; |
| 62 | |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 63 | irq = d->hwirq; |
| 64 | |
Sascha Hauer | 5a24d69 | 2011-05-10 18:16:10 +0200 | [diff] [blame] | 65 | if (irq >= AVIC_NUM_IRQS) |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 66 | return -EINVAL; |
| 67 | |
Sascha Hauer | 5a24d69 | 2011-05-10 18:16:10 +0200 | [diff] [blame] | 68 | if (irq < AVIC_NUM_IRQS / 2) { |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame^] | 69 | irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); |
| 70 | imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 71 | } else { |
Sascha Hauer | 5a24d69 | 2011-05-10 18:16:10 +0200 | [diff] [blame] | 72 | irq -= AVIC_NUM_IRQS / 2; |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame^] | 73 | irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); |
| 74 | imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | return 0; |
| 78 | } |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 79 | #endif /* CONFIG_FIQ */ |
| 80 | |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 81 | |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 82 | static struct mxc_extra_irq avic_extra_irq = { |
Peter Horton | cdc3f10 | 2010-12-06 11:37:38 +0000 | [diff] [blame] | 83 | #ifdef CONFIG_FIQ |
| 84 | .set_irq_fiq = avic_set_irq_fiq, |
| 85 | #endif |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 86 | }; |
| 87 | |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 88 | #ifdef CONFIG_PM |
Fabio Estevam | 5fe839d | 2013-02-05 15:36:16 -0200 | [diff] [blame] | 89 | static u32 avic_saved_mask_reg[2]; |
| 90 | |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 91 | static void avic_irq_suspend(struct irq_data *d) |
| 92 | { |
| 93 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 94 | struct irq_chip_type *ct = gc->chip_types; |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 95 | int idx = d->hwirq >> 5; |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 96 | |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame^] | 97 | avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); |
| 98 | imx_writel(gc->wake_active, avic_base + ct->regs.mask); |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | static void avic_irq_resume(struct irq_data *d) |
| 102 | { |
| 103 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 104 | struct irq_chip_type *ct = gc->chip_types; |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 105 | int idx = d->hwirq >> 5; |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 106 | |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame^] | 107 | imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | #else |
| 111 | #define avic_irq_suspend NULL |
| 112 | #define avic_irq_resume NULL |
| 113 | #endif |
| 114 | |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 115 | static __init void avic_init_gc(int idx, unsigned int irq_start) |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 116 | { |
| 117 | struct irq_chip_generic *gc; |
| 118 | struct irq_chip_type *ct; |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 119 | |
| 120 | gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, |
| 121 | handle_level_irq); |
| 122 | gc->private = &avic_extra_irq; |
| 123 | gc->wake_enabled = IRQ_MSK(32); |
| 124 | |
| 125 | ct = gc->chip_types; |
| 126 | ct->chip.irq_mask = irq_gc_mask_clr_bit; |
| 127 | ct->chip.irq_unmask = irq_gc_mask_set_bit; |
| 128 | ct->chip.irq_ack = irq_gc_mask_clr_bit; |
| 129 | ct->chip.irq_set_wake = irq_gc_set_wake; |
| 130 | ct->chip.irq_suspend = avic_irq_suspend; |
| 131 | ct->chip.irq_resume = avic_irq_resume; |
| 132 | ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH; |
| 133 | ct->regs.ack = ct->regs.mask; |
| 134 | |
| 135 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); |
| 136 | } |
| 137 | |
Alexander Shiyan | 000bf9e | 2014-05-11 11:35:57 +0400 | [diff] [blame] | 138 | static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) |
Sascha Hauer | b6de943 | 2011-09-20 14:28:17 +0200 | [diff] [blame] | 139 | { |
| 140 | u32 nivector; |
| 141 | |
| 142 | do { |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame^] | 143 | nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16; |
Sascha Hauer | b6de943 | 2011-09-20 14:28:17 +0200 | [diff] [blame] | 144 | if (nivector == 0xffff) |
| 145 | break; |
| 146 | |
Marc Zyngier | 9705ca3 | 2014-08-26 11:03:37 +0100 | [diff] [blame] | 147 | handle_domain_irq(domain, nivector, regs); |
Sascha Hauer | b6de943 | 2011-09-20 14:28:17 +0200 | [diff] [blame] | 148 | } while (1); |
| 149 | } |
| 150 | |
Robert Schwebel | 2c130fd | 2008-03-28 11:02:13 +0100 | [diff] [blame] | 151 | /* |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 152 | * This function initializes the AVIC hardware and disables all the |
| 153 | * interrupts. It registers the interrupt enable and disable functions |
| 154 | * to the kernel for each interrupt source. |
| 155 | */ |
Sascha Hauer | c5aa0ad | 2009-05-25 17:36:19 +0200 | [diff] [blame] | 156 | void __init mxc_init_irq(void __iomem *irqbase) |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 157 | { |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 158 | struct device_node *np; |
| 159 | int irq_base; |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 160 | int i; |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 161 | |
Sascha Hauer | c5aa0ad | 2009-05-25 17:36:19 +0200 | [diff] [blame] | 162 | avic_base = irqbase; |
Sascha Hauer | 84c9fa4 | 2009-02-18 20:59:04 +0100 | [diff] [blame] | 163 | |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 164 | /* put the AVIC into the reset value with |
| 165 | * all interrupts disabled |
| 166 | */ |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame^] | 167 | imx_writel(0, avic_base + AVIC_INTCNTL); |
| 168 | imx_writel(0x1f, avic_base + AVIC_NIMASK); |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 169 | |
| 170 | /* disable all interrupts */ |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame^] | 171 | imx_writel(0, avic_base + AVIC_INTENABLEH); |
| 172 | imx_writel(0, avic_base + AVIC_INTENABLEL); |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 173 | |
| 174 | /* all IRQ no FIQ */ |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame^] | 175 | imx_writel(0, avic_base + AVIC_INTTYPEH); |
| 176 | imx_writel(0, avic_base + AVIC_INTTYPEL); |
Hui Wang | 3439a39 | 2011-09-22 17:40:08 +0800 | [diff] [blame] | 177 | |
Shawn Guo | 544496a | 2012-06-13 10:55:46 +0800 | [diff] [blame] | 178 | irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); |
| 179 | WARN_ON(irq_base < 0); |
| 180 | |
| 181 | np = of_find_compatible_node(NULL, NULL, "fsl,avic"); |
| 182 | domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, |
| 183 | &irq_domain_simple_ops, NULL); |
| 184 | WARN_ON(!domain); |
| 185 | |
| 186 | for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) |
| 187 | avic_init_gc(i, irq_base); |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 188 | |
Darius Augulis | 479c901 | 2008-09-09 11:29:41 +0200 | [diff] [blame] | 189 | /* Set default priority value (0) for all IRQ's */ |
| 190 | for (i = 0; i < 8; i++) |
Johannes Berg | c553138 | 2016-01-27 17:59:35 +0100 | [diff] [blame^] | 191 | imx_writel(0, avic_base + AVIC_NIPRIORITY(i)); |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 192 | |
Alexander Shiyan | 000bf9e | 2014-05-11 11:35:57 +0400 | [diff] [blame] | 193 | set_handle_irq(avic_handle_irq); |
| 194 | |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 195 | #ifdef CONFIG_FIQ |
| 196 | /* Initialize FIQ */ |
Shawn Guo | bc89663 | 2012-06-28 14:42:08 +0800 | [diff] [blame] | 197 | init_FIQ(FIQ_START); |
Paulius Zaleckas | d7927e1 | 2008-11-14 11:01:39 +0100 | [diff] [blame] | 198 | #endif |
| 199 | |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 200 | printk(KERN_INFO "MXC IRQ initialized\n"); |
| 201 | } |