blob: 91ac8da2502017a0463f73e2394c2778bd78376d [file] [log] [blame]
Chris Leechc13c8262006-05-23 17:18:44 -07001/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000021#ifndef LINUX_DMAENGINE_H
22#define LINUX_DMAENGINE_H
David Woodhouse1c0f16e2006-06-27 02:53:56 -070023
Chris Leechc13c8262006-05-23 17:18:44 -070024#include <linux/device.h>
25#include <linux/uio.h>
Paul Gortmaker187f1882011-11-23 20:12:59 -050026#include <linux/bug.h>
Vinod Koul90b44f82011-07-25 19:57:52 +053027#include <linux/scatterlist.h>
Paul Gortmakera8efa9d2011-07-29 16:55:11 +100028#include <linux/bitmap.h>
Viresh Kumardcc043d2012-02-01 16:12:18 +053029#include <linux/types.h>
Paul Gortmakera8efa9d2011-07-29 16:55:11 +100030#include <asm/page.h>
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +000031
Chris Leechc13c8262006-05-23 17:18:44 -070032/**
Randy Dunlapfe4ada22006-07-03 19:44:51 -070033 * typedef dma_cookie_t - an opaque DMA cookie
Chris Leechc13c8262006-05-23 17:18:44 -070034 *
35 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
36 */
37typedef s32 dma_cookie_t;
Steven J. Magnani76bd0612010-02-28 22:18:16 -070038#define DMA_MIN_COOKIE 1
39#define DMA_MAX_COOKIE INT_MAX
Chris Leechc13c8262006-05-23 17:18:44 -070040
41#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
42
43/**
44 * enum dma_status - DMA transaction status
45 * @DMA_SUCCESS: transaction completed successfully
46 * @DMA_IN_PROGRESS: transaction not yet processed
Linus Walleij07934482010-03-26 16:50:49 -070047 * @DMA_PAUSED: transaction is paused
Chris Leechc13c8262006-05-23 17:18:44 -070048 * @DMA_ERROR: transaction failed
49 */
50enum dma_status {
51 DMA_SUCCESS,
52 DMA_IN_PROGRESS,
Linus Walleij07934482010-03-26 16:50:49 -070053 DMA_PAUSED,
Chris Leechc13c8262006-05-23 17:18:44 -070054 DMA_ERROR,
55};
56
57/**
Dan Williams7405f742007-01-02 11:10:43 -070058 * enum dma_transaction_type - DMA transaction types/indexes
Dan Williams138f4c32009-09-08 17:42:51 -070059 *
60 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
61 * automatically set as dma devices are registered.
Dan Williams7405f742007-01-02 11:10:43 -070062 */
63enum dma_transaction_type {
64 DMA_MEMCPY,
65 DMA_XOR,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070066 DMA_PQ,
Dan Williams099f53c2009-04-08 14:28:37 -070067 DMA_XOR_VAL,
68 DMA_PQ_VAL,
Dan Williams7405f742007-01-02 11:10:43 -070069 DMA_MEMSET,
Dan Williams7405f742007-01-02 11:10:43 -070070 DMA_INTERRUPT,
Ira Snydera86ee032010-09-30 11:46:44 +000071 DMA_SG,
Dan Williams59b5ec22009-01-06 11:38:15 -070072 DMA_PRIVATE,
Dan Williams138f4c32009-09-08 17:42:51 -070073 DMA_ASYNC_TX,
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070074 DMA_SLAVE,
Sascha Hauer782bc952010-09-30 13:56:32 +000075 DMA_CYCLIC,
Jassi Brarb14dab72011-10-13 12:33:30 +053076 DMA_INTERLEAVE,
Dan Williams7405f742007-01-02 11:10:43 -070077/* last transaction type for creation of the capabilities mask */
Jassi Brarb14dab72011-10-13 12:33:30 +053078 DMA_TX_TYPE_END,
79};
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070080
Vinod Koul49920bc2011-10-13 15:15:27 +053081/**
82 * enum dma_transfer_direction - dma transfer mode and direction indicator
83 * @DMA_MEM_TO_MEM: Async/Memcpy mode
84 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
85 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
86 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
87 */
88enum dma_transfer_direction {
89 DMA_MEM_TO_MEM,
90 DMA_MEM_TO_DEV,
91 DMA_DEV_TO_MEM,
92 DMA_DEV_TO_DEV,
Shawn Guo62268ce2011-12-13 23:48:03 +080093 DMA_TRANS_NONE,
Vinod Koul49920bc2011-10-13 15:15:27 +053094};
Dan Williams7405f742007-01-02 11:10:43 -070095
96/**
Jassi Brarb14dab72011-10-13 12:33:30 +053097 * Interleaved Transfer Request
98 * ----------------------------
99 * A chunk is collection of contiguous bytes to be transfered.
100 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
101 * ICGs may or maynot change between chunks.
102 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
103 * that when repeated an integral number of times, specifies the transfer.
104 * A transfer template is specification of a Frame, the number of times
105 * it is to be repeated and other per-transfer attributes.
106 *
107 * Practically, a client driver would have ready a template for each
108 * type of transfer it is going to need during its lifetime and
109 * set only 'src_start' and 'dst_start' before submitting the requests.
110 *
111 *
112 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
113 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
114 *
115 * == Chunk size
116 * ... ICG
117 */
118
119/**
120 * struct data_chunk - Element of scatter-gather list that makes a frame.
121 * @size: Number of bytes to read from source.
122 * size_dst := fn(op, size_src), so doesn't mean much for destination.
123 * @icg: Number of bytes to jump after last src/dst address of this
124 * chunk and before first src/dst address for next chunk.
125 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
126 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
127 */
128struct data_chunk {
129 size_t size;
130 size_t icg;
131};
132
133/**
134 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
135 * and attributes.
136 * @src_start: Bus address of source for the first chunk.
137 * @dst_start: Bus address of destination for the first chunk.
138 * @dir: Specifies the type of Source and Destination.
139 * @src_inc: If the source address increments after reading from it.
140 * @dst_inc: If the destination address increments after writing to it.
141 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
142 * Otherwise, source is read contiguously (icg ignored).
143 * Ignored if src_inc is false.
144 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
145 * Otherwise, destination is filled contiguously (icg ignored).
146 * Ignored if dst_inc is false.
147 * @numf: Number of frames in this template.
148 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
149 * @sgl: Array of {chunk,icg} pairs that make up a frame.
150 */
151struct dma_interleaved_template {
152 dma_addr_t src_start;
153 dma_addr_t dst_start;
154 enum dma_transfer_direction dir;
155 bool src_inc;
156 bool dst_inc;
157 bool src_sgl;
158 bool dst_sgl;
159 size_t numf;
160 size_t frame_size;
161 struct data_chunk sgl[0];
162};
163
164/**
Dan Williams636bdea2008-04-17 20:17:26 -0700165 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700166 * control completion, and communicate status.
Dan Williamsd4c56f92008-02-02 19:49:58 -0700167 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700168 * this transaction
Guennadi Liakhovetskia88f6662009-12-10 18:35:15 +0100169 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700170 * acknowledges receipt, i.e. has has a chance to establish any dependency
171 * chains
Dan Williamse1d181e2008-07-04 00:13:40 -0700172 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
173 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200174 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
175 * (if not set, do the source dma-unmapping as page)
176 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
177 * (if not set, do the destination dma-unmapping as page)
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700178 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
179 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
180 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
181 * sources that were the result of a previous operation, in the case of a PQ
182 * operation it continues the calculation with new sources
Dan Williams0403e382009-09-08 17:42:50 -0700183 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
184 * on the result of this operation
Dan Williamsd4c56f92008-02-02 19:49:58 -0700185 */
Dan Williams636bdea2008-04-17 20:17:26 -0700186enum dma_ctrl_flags {
Dan Williamsd4c56f92008-02-02 19:49:58 -0700187 DMA_PREP_INTERRUPT = (1 << 0),
Dan Williams636bdea2008-04-17 20:17:26 -0700188 DMA_CTRL_ACK = (1 << 1),
Dan Williamse1d181e2008-07-04 00:13:40 -0700189 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
190 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200191 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
192 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
Dan Williamsf9dd2132009-09-08 17:42:29 -0700193 DMA_PREP_PQ_DISABLE_P = (1 << 6),
194 DMA_PREP_PQ_DISABLE_Q = (1 << 7),
195 DMA_PREP_CONTINUE = (1 << 8),
Dan Williams0403e382009-09-08 17:42:50 -0700196 DMA_PREP_FENCE = (1 << 9),
Dan Williamsd4c56f92008-02-02 19:49:58 -0700197};
198
199/**
Linus Walleijc3635c72010-03-26 16:44:01 -0700200 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
201 * on a running channel.
202 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
203 * @DMA_PAUSE: pause ongoing transfers
204 * @DMA_RESUME: resume paused transfer
Linus Walleijc156d0a2010-08-04 13:37:33 +0200205 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
206 * that need to runtime reconfigure the slave channels (as opposed to passing
207 * configuration data in statically from the platform). An additional
208 * argument of struct dma_slave_config must be passed in with this
209 * command.
Ira Snyder968f19a2010-09-30 11:46:46 +0000210 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
211 * into external start mode.
Linus Walleijc3635c72010-03-26 16:44:01 -0700212 */
213enum dma_ctrl_cmd {
214 DMA_TERMINATE_ALL,
215 DMA_PAUSE,
216 DMA_RESUME,
Linus Walleijc156d0a2010-08-04 13:37:33 +0200217 DMA_SLAVE_CONFIG,
Ira Snyder968f19a2010-09-30 11:46:46 +0000218 FSLDMA_EXTERNAL_START,
Linus Walleijc3635c72010-03-26 16:44:01 -0700219};
220
221/**
Dan Williamsad283ea2009-08-29 19:09:26 -0700222 * enum sum_check_bits - bit position of pq_check_flags
223 */
224enum sum_check_bits {
225 SUM_CHECK_P = 0,
226 SUM_CHECK_Q = 1,
227};
228
229/**
230 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
231 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
232 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
233 */
234enum sum_check_flags {
235 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
236 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
237};
238
239
240/**
Dan Williams7405f742007-01-02 11:10:43 -0700241 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
242 * See linux/cpumask.h
243 */
244typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
245
246/**
Chris Leechc13c8262006-05-23 17:18:44 -0700247 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
Chris Leechc13c8262006-05-23 17:18:44 -0700248 * @memcpy_count: transaction counter
249 * @bytes_transferred: byte counter
250 */
251
252struct dma_chan_percpu {
Chris Leechc13c8262006-05-23 17:18:44 -0700253 /* stats */
254 unsigned long memcpy_count;
255 unsigned long bytes_transferred;
256};
257
258/**
259 * struct dma_chan - devices supply DMA channels, clients use them
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700260 * @device: ptr to the dma device who supplies this channel, always !%NULL
Chris Leechc13c8262006-05-23 17:18:44 -0700261 * @cookie: last cookie value returned to client
Russell King - ARM Linux4d4e58d2012-03-06 22:34:06 +0000262 * @completed_cookie: last completed cookie for this channel
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700263 * @chan_id: channel ID for sysfs
Dan Williams41d5e592009-01-06 11:38:21 -0700264 * @dev: class device for sysfs
Chris Leechc13c8262006-05-23 17:18:44 -0700265 * @device_node: used to add this to the device chan list
266 * @local: per-cpu pointer to a struct dma_chan_percpu
Dan Williams7cc5bf92008-07-08 11:58:21 -0700267 * @client-count: how many clients are using this channel
Dan Williamsbec08512009-01-06 11:38:14 -0700268 * @table_count: number of appearances in the mem-to-mem allocation table
Dan Williams287d8592009-02-18 14:48:26 -0800269 * @private: private data for certain client-channel associations
Chris Leechc13c8262006-05-23 17:18:44 -0700270 */
271struct dma_chan {
Chris Leechc13c8262006-05-23 17:18:44 -0700272 struct dma_device *device;
273 dma_cookie_t cookie;
Russell King - ARM Linux4d4e58d2012-03-06 22:34:06 +0000274 dma_cookie_t completed_cookie;
Chris Leechc13c8262006-05-23 17:18:44 -0700275
276 /* sysfs */
277 int chan_id;
Dan Williams41d5e592009-01-06 11:38:21 -0700278 struct dma_chan_dev *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700279
Chris Leechc13c8262006-05-23 17:18:44 -0700280 struct list_head device_node;
Tejun Heoa29d8b82010-02-02 14:39:15 +0900281 struct dma_chan_percpu __percpu *local;
Dan Williams7cc5bf92008-07-08 11:58:21 -0700282 int client_count;
Dan Williamsbec08512009-01-06 11:38:14 -0700283 int table_count;
Dan Williams287d8592009-02-18 14:48:26 -0800284 void *private;
Chris Leechc13c8262006-05-23 17:18:44 -0700285};
286
Dan Williams41d5e592009-01-06 11:38:21 -0700287/**
288 * struct dma_chan_dev - relate sysfs device node to backing channel device
289 * @chan - driver channel device
290 * @device - sysfs device
Dan Williams864498a2009-01-06 11:38:21 -0700291 * @dev_id - parent dma_device dev_id
292 * @idr_ref - reference count to gate release of dma_device dev_id
Dan Williams41d5e592009-01-06 11:38:21 -0700293 */
294struct dma_chan_dev {
295 struct dma_chan *chan;
296 struct device device;
Dan Williams864498a2009-01-06 11:38:21 -0700297 int dev_id;
298 atomic_t *idr_ref;
Dan Williams41d5e592009-01-06 11:38:21 -0700299};
300
Linus Walleijc156d0a2010-08-04 13:37:33 +0200301/**
302 * enum dma_slave_buswidth - defines bus with of the DMA slave
303 * device, source or target buses
304 */
305enum dma_slave_buswidth {
306 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
307 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
308 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
309 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
310 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
311};
312
313/**
314 * struct dma_slave_config - dma slave channel runtime config
315 * @direction: whether the data shall go in or out on this slave
316 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
317 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
318 * need to differentiate source and target addresses.
319 * @src_addr: this is the physical address where DMA slave data
320 * should be read (RX), if the source is memory this argument is
321 * ignored.
322 * @dst_addr: this is the physical address where DMA slave data
323 * should be written (TX), if the source is memory this argument
324 * is ignored.
325 * @src_addr_width: this is the width in bytes of the source (RX)
326 * register where DMA data shall be read. If the source
327 * is memory this may be ignored depending on architecture.
328 * Legal values: 1, 2, 4, 8.
329 * @dst_addr_width: same as src_addr_width but for destination
330 * target (TX) mutatis mutandis.
331 * @src_maxburst: the maximum number of words (note: words, as in
332 * units of the src_addr_width member, not bytes) that can be sent
333 * in one burst to the device. Typically something like half the
334 * FIFO depth on I/O peripherals so you don't overflow it. This
335 * may or may not be applicable on memory sources.
336 * @dst_maxburst: same as src_maxburst but for destination target
337 * mutatis mutandis.
Viresh Kumardcc043d2012-02-01 16:12:18 +0530338 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
339 * with 'true' if peripheral should be flow controller. Direction will be
340 * selected at Runtime.
Laxman Dewangan4fd1e322012-06-06 10:55:26 +0530341 * @slave_id: Slave requester id. Only valid for slave channels. The dma
342 * slave peripheral will have unique id as dma requester which need to be
343 * pass as slave config.
Linus Walleijc156d0a2010-08-04 13:37:33 +0200344 *
345 * This struct is passed in as configuration data to a DMA engine
346 * in order to set up a certain channel for DMA transport at runtime.
347 * The DMA device/engine has to provide support for an additional
348 * command in the channel config interface, DMA_SLAVE_CONFIG
349 * and this struct will then be passed in as an argument to the
350 * DMA engine device_control() function.
351 *
352 * The rationale for adding configuration information to this struct
353 * is as follows: if it is likely that most DMA slave controllers in
354 * the world will support the configuration option, then make it
355 * generic. If not: if it is fixed so that it be sent in static from
356 * the platform data, then prefer to do that. Else, if it is neither
357 * fixed at runtime, nor generic enough (such as bus mastership on
358 * some CPU family and whatnot) then create a custom slave config
359 * struct and pass that, then make this config a member of that
360 * struct, if applicable.
361 */
362struct dma_slave_config {
Vinod Koul49920bc2011-10-13 15:15:27 +0530363 enum dma_transfer_direction direction;
Linus Walleijc156d0a2010-08-04 13:37:33 +0200364 dma_addr_t src_addr;
365 dma_addr_t dst_addr;
366 enum dma_slave_buswidth src_addr_width;
367 enum dma_slave_buswidth dst_addr_width;
368 u32 src_maxburst;
369 u32 dst_maxburst;
Viresh Kumardcc043d2012-02-01 16:12:18 +0530370 bool device_fc;
Laxman Dewangan4fd1e322012-06-06 10:55:26 +0530371 unsigned int slave_id;
Linus Walleijc156d0a2010-08-04 13:37:33 +0200372};
373
Dan Williams41d5e592009-01-06 11:38:21 -0700374static inline const char *dma_chan_name(struct dma_chan *chan)
375{
376 return dev_name(&chan->dev->device);
377}
Dan Williamsd379b012007-07-09 11:56:42 -0700378
Chris Leechc13c8262006-05-23 17:18:44 -0700379void dma_chan_cleanup(struct kref *kref);
380
Chris Leechc13c8262006-05-23 17:18:44 -0700381/**
Dan Williams59b5ec22009-01-06 11:38:15 -0700382 * typedef dma_filter_fn - callback filter for dma_request_channel
383 * @chan: channel to be reviewed
384 * @filter_param: opaque parameter passed through dma_request_channel
385 *
386 * When this optional parameter is specified in a call to dma_request_channel a
387 * suitable channel is passed to this routine for further dispositioning before
388 * being returned. Where 'suitable' indicates a non-busy channel that
Dan Williams7dd60252009-01-06 11:38:19 -0700389 * satisfies the given capability mask. It returns 'true' to indicate that the
390 * channel is suitable.
Dan Williams59b5ec22009-01-06 11:38:15 -0700391 */
Dan Williams7dd60252009-01-06 11:38:19 -0700392typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
Dan Williams59b5ec22009-01-06 11:38:15 -0700393
Dan Williams7405f742007-01-02 11:10:43 -0700394typedef void (*dma_async_tx_callback)(void *dma_async_param);
395/**
396 * struct dma_async_tx_descriptor - async transaction descriptor
397 * ---dma generic offload fields---
398 * @cookie: tracking cookie for this transaction, set to -EBUSY if
399 * this tx is sitting on a dependency list
Dan Williams636bdea2008-04-17 20:17:26 -0700400 * @flags: flags to augment operation preparation, control completion, and
401 * communicate status
Dan Williams7405f742007-01-02 11:10:43 -0700402 * @phys: physical address of the descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700403 * @chan: target channel for this operation
404 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
Dan Williams7405f742007-01-02 11:10:43 -0700405 * @callback: routine to call after this operation is complete
406 * @callback_param: general parameter to pass to the callback routine
407 * ---async_tx api specific fields---
Dan Williams19242d72008-04-17 20:17:25 -0700408 * @next: at completion submit this descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700409 * @parent: pointer to the next level up in the dependency chain
Dan Williams19242d72008-04-17 20:17:25 -0700410 * @lock: protect the parent and next pointers
Dan Williams7405f742007-01-02 11:10:43 -0700411 */
412struct dma_async_tx_descriptor {
413 dma_cookie_t cookie;
Dan Williams636bdea2008-04-17 20:17:26 -0700414 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
Dan Williams7405f742007-01-02 11:10:43 -0700415 dma_addr_t phys;
Dan Williams7405f742007-01-02 11:10:43 -0700416 struct dma_chan *chan;
417 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
Dan Williams7405f742007-01-02 11:10:43 -0700418 dma_async_tx_callback callback;
419 void *callback_param;
Dan Williams5fc6d892010-10-07 16:44:50 -0700420#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williams19242d72008-04-17 20:17:25 -0700421 struct dma_async_tx_descriptor *next;
Dan Williams7405f742007-01-02 11:10:43 -0700422 struct dma_async_tx_descriptor *parent;
423 spinlock_t lock;
Dan Williamscaa20d972010-05-17 16:24:16 -0700424#endif
Dan Williams7405f742007-01-02 11:10:43 -0700425};
426
Dan Williams5fc6d892010-10-07 16:44:50 -0700427#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williamscaa20d972010-05-17 16:24:16 -0700428static inline void txd_lock(struct dma_async_tx_descriptor *txd)
429{
430}
431static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
432{
433}
434static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
435{
436 BUG();
437}
438static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
439{
440}
441static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
442{
443}
444static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
445{
446 return NULL;
447}
448static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
449{
450 return NULL;
451}
452
453#else
454static inline void txd_lock(struct dma_async_tx_descriptor *txd)
455{
456 spin_lock_bh(&txd->lock);
457}
458static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
459{
460 spin_unlock_bh(&txd->lock);
461}
462static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
463{
464 txd->next = next;
465 next->parent = txd;
466}
467static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
468{
469 txd->parent = NULL;
470}
471static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
472{
473 txd->next = NULL;
474}
475static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
476{
477 return txd->parent;
478}
479static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
480{
481 return txd->next;
482}
483#endif
484
Chris Leechc13c8262006-05-23 17:18:44 -0700485/**
Linus Walleij07934482010-03-26 16:50:49 -0700486 * struct dma_tx_state - filled in to report the status of
487 * a transfer.
488 * @last: last completed DMA cookie
489 * @used: last issued DMA cookie (i.e. the one in progress)
490 * @residue: the remaining number of bytes left to transmit
491 * on the selected transfer for states DMA_IN_PROGRESS and
492 * DMA_PAUSED if this is implemented in the driver, else 0
493 */
494struct dma_tx_state {
495 dma_cookie_t last;
496 dma_cookie_t used;
497 u32 residue;
498};
499
500/**
Chris Leechc13c8262006-05-23 17:18:44 -0700501 * struct dma_device - info on the entity supplying DMA services
502 * @chancnt: how many DMA channels are supported
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900503 * @privatecnt: how many DMA channels are requested by dma_request_channel
Chris Leechc13c8262006-05-23 17:18:44 -0700504 * @channels: the list of struct dma_chan
505 * @global_node: list_head for global dma_device_list
Dan Williams7405f742007-01-02 11:10:43 -0700506 * @cap_mask: one or more dma_capability flags
507 * @max_xor: maximum number of xor sources, 0 if no capability
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700508 * @max_pq: maximum number of PQ sources and PQ-continue capability
Dan Williams83544ae2009-09-08 17:42:53 -0700509 * @copy_align: alignment shift for memcpy operations
510 * @xor_align: alignment shift for xor operations
511 * @pq_align: alignment shift for pq operations
512 * @fill_align: alignment shift for memset operations
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700513 * @dev_id: unique device ID
Dan Williams7405f742007-01-02 11:10:43 -0700514 * @dev: struct device reference for dma mapping api
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700515 * @device_alloc_chan_resources: allocate resources and return the
516 * number of allocated descriptors
517 * @device_free_chan_resources: release DMA channel's resources
Dan Williams7405f742007-01-02 11:10:43 -0700518 * @device_prep_dma_memcpy: prepares a memcpy operation
519 * @device_prep_dma_xor: prepares a xor operation
Dan Williams099f53c2009-04-08 14:28:37 -0700520 * @device_prep_dma_xor_val: prepares a xor validation operation
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700521 * @device_prep_dma_pq: prepares a pq operation
522 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
Dan Williams7405f742007-01-02 11:10:43 -0700523 * @device_prep_dma_memset: prepares a memset operation
524 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700525 * @device_prep_slave_sg: prepares a slave dma operation
Sascha Hauer782bc952010-09-30 13:56:32 +0000526 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
527 * The function takes a buffer of size buf_len. The callback function will
528 * be called after period_len bytes have been transferred.
Jassi Brarb14dab72011-10-13 12:33:30 +0530529 * @device_prep_interleaved_dma: Transfer expression in a generic way.
Linus Walleijc3635c72010-03-26 16:44:01 -0700530 * @device_control: manipulate all pending operations on a channel, returns
531 * zero or error code
Linus Walleij07934482010-03-26 16:50:49 -0700532 * @device_tx_status: poll for transaction completion, the optional
533 * txstate parameter can be supplied with a pointer to get a
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300534 * struct with auxiliary transfer status information, otherwise the call
Linus Walleij07934482010-03-26 16:50:49 -0700535 * will just return a simple status code
Dan Williams7405f742007-01-02 11:10:43 -0700536 * @device_issue_pending: push pending transactions to hardware
Chris Leechc13c8262006-05-23 17:18:44 -0700537 */
538struct dma_device {
539
540 unsigned int chancnt;
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900541 unsigned int privatecnt;
Chris Leechc13c8262006-05-23 17:18:44 -0700542 struct list_head channels;
543 struct list_head global_node;
Dan Williams7405f742007-01-02 11:10:43 -0700544 dma_cap_mask_t cap_mask;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700545 unsigned short max_xor;
546 unsigned short max_pq;
Dan Williams83544ae2009-09-08 17:42:53 -0700547 u8 copy_align;
548 u8 xor_align;
549 u8 pq_align;
550 u8 fill_align;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700551 #define DMA_HAS_PQ_CONTINUE (1 << 15)
Chris Leechc13c8262006-05-23 17:18:44 -0700552
Chris Leechc13c8262006-05-23 17:18:44 -0700553 int dev_id;
Dan Williams7405f742007-01-02 11:10:43 -0700554 struct device *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700555
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700556 int (*device_alloc_chan_resources)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700557 void (*device_free_chan_resources)(struct dma_chan *chan);
Dan Williams7405f742007-01-02 11:10:43 -0700558
559 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
Dan Williams00367312008-02-02 19:49:57 -0700560 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700561 size_t len, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700562 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
Dan Williams00367312008-02-02 19:49:57 -0700563 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700564 unsigned int src_cnt, size_t len, unsigned long flags);
Dan Williams099f53c2009-04-08 14:28:37 -0700565 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
Dan Williams00367312008-02-02 19:49:57 -0700566 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
Dan Williamsad283ea2009-08-29 19:09:26 -0700567 size_t len, enum sum_check_flags *result, unsigned long flags);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700568 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
569 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
570 unsigned int src_cnt, const unsigned char *scf,
571 size_t len, unsigned long flags);
572 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
573 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
574 unsigned int src_cnt, const unsigned char *scf, size_t len,
575 enum sum_check_flags *pqres, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700576 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
Dan Williams00367312008-02-02 19:49:57 -0700577 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700578 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700579 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
Dan Williams636bdea2008-04-17 20:17:26 -0700580 struct dma_chan *chan, unsigned long flags);
Ira Snydera86ee032010-09-30 11:46:44 +0000581 struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
582 struct dma_chan *chan,
583 struct scatterlist *dst_sg, unsigned int dst_nents,
584 struct scatterlist *src_sg, unsigned int src_nents,
585 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700586
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700587 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
588 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Koul49920bc2011-10-13 15:15:27 +0530589 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500590 unsigned long flags, void *context);
Sascha Hauer782bc952010-09-30 13:56:32 +0000591 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
592 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500593 size_t period_len, enum dma_transfer_direction direction,
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +0300594 unsigned long flags, void *context);
Jassi Brarb14dab72011-10-13 12:33:30 +0530595 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
596 struct dma_chan *chan, struct dma_interleaved_template *xt,
597 unsigned long flags);
Linus Walleij05827632010-05-17 16:30:42 -0700598 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
599 unsigned long arg);
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700600
Linus Walleij07934482010-03-26 16:50:49 -0700601 enum dma_status (*device_tx_status)(struct dma_chan *chan,
602 dma_cookie_t cookie,
603 struct dma_tx_state *txstate);
Dan Williams7405f742007-01-02 11:10:43 -0700604 void (*device_issue_pending)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700605};
606
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000607static inline int dmaengine_device_control(struct dma_chan *chan,
608 enum dma_ctrl_cmd cmd,
609 unsigned long arg)
610{
Jon Mason944ea4d2012-11-11 23:03:20 +0000611 if (chan->device->device_control)
612 return chan->device->device_control(chan, cmd, arg);
Andy Shevchenko978c4172013-02-14 11:00:16 +0200613
614 return -ENOSYS;
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000615}
616
617static inline int dmaengine_slave_config(struct dma_chan *chan,
618 struct dma_slave_config *config)
619{
620 return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
621 (unsigned long)config);
622}
623
Andy Shevchenko61cc13a2013-01-10 10:52:56 +0200624static inline bool is_slave_direction(enum dma_transfer_direction direction)
625{
626 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
627}
628
Vinod Koul90b44f82011-07-25 19:57:52 +0530629static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
Kuninori Morimoto922ee082012-04-25 20:50:53 +0200630 struct dma_chan *chan, dma_addr_t buf, size_t len,
Vinod Koul49920bc2011-10-13 15:15:27 +0530631 enum dma_transfer_direction dir, unsigned long flags)
Vinod Koul90b44f82011-07-25 19:57:52 +0530632{
633 struct scatterlist sg;
Kuninori Morimoto922ee082012-04-25 20:50:53 +0200634 sg_init_table(&sg, 1);
635 sg_dma_address(&sg) = buf;
636 sg_dma_len(&sg) = len;
Vinod Koul90b44f82011-07-25 19:57:52 +0530637
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500638 return chan->device->device_prep_slave_sg(chan, &sg, 1,
639 dir, flags, NULL);
Vinod Koul90b44f82011-07-25 19:57:52 +0530640}
641
Alexandre Bounine16052822012-03-08 16:11:18 -0500642static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
643 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
644 enum dma_transfer_direction dir, unsigned long flags)
645{
646 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500647 dir, flags, NULL);
Alexandre Bounine16052822012-03-08 16:11:18 -0500648}
649
Alexandre Bouninee42d98e2012-05-31 16:26:38 -0700650#ifdef CONFIG_RAPIDIO_DMA_ENGINE
651struct rio_dma_ext;
652static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
653 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
654 enum dma_transfer_direction dir, unsigned long flags,
655 struct rio_dma_ext *rio_ext)
656{
657 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
658 dir, flags, rio_ext);
659}
660#endif
661
Alexandre Bounine16052822012-03-08 16:11:18 -0500662static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
663 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
Peter Ujfalusie7736cd2012-09-24 10:58:04 +0300664 size_t period_len, enum dma_transfer_direction dir,
665 unsigned long flags)
Alexandre Bounine16052822012-03-08 16:11:18 -0500666{
667 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +0300668 period_len, dir, flags, NULL);
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000669}
670
Barry Songa14acb42012-11-06 21:32:39 +0800671static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
672 struct dma_chan *chan, struct dma_interleaved_template *xt,
673 unsigned long flags)
674{
675 return chan->device->device_prep_interleaved_dma(chan, xt, flags);
676}
677
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000678static inline int dmaengine_terminate_all(struct dma_chan *chan)
679{
680 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
681}
682
683static inline int dmaengine_pause(struct dma_chan *chan)
684{
685 return dmaengine_device_control(chan, DMA_PAUSE, 0);
686}
687
688static inline int dmaengine_resume(struct dma_chan *chan)
689{
690 return dmaengine_device_control(chan, DMA_RESUME, 0);
691}
692
Lars-Peter Clausen3052cc22012-06-11 20:11:40 +0200693static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
694 dma_cookie_t cookie, struct dma_tx_state *state)
695{
696 return chan->device->device_tx_status(chan, cookie, state);
697}
698
Russell King - ARM Linux98d530f2011-01-01 23:00:23 +0000699static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
Sascha Hauer6e3ecaf2010-09-30 13:56:33 +0000700{
701 return desc->tx_submit(desc);
702}
703
Dan Williams83544ae2009-09-08 17:42:53 -0700704static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
705{
706 size_t mask;
707
708 if (!align)
709 return true;
710 mask = (1 << align) - 1;
711 if (mask & (off1 | off2 | len))
712 return false;
713 return true;
714}
715
716static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
717 size_t off2, size_t len)
718{
719 return dmaengine_check_align(dev->copy_align, off1, off2, len);
720}
721
722static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
723 size_t off2, size_t len)
724{
725 return dmaengine_check_align(dev->xor_align, off1, off2, len);
726}
727
728static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
729 size_t off2, size_t len)
730{
731 return dmaengine_check_align(dev->pq_align, off1, off2, len);
732}
733
734static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
735 size_t off2, size_t len)
736{
737 return dmaengine_check_align(dev->fill_align, off1, off2, len);
738}
739
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700740static inline void
741dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
742{
743 dma->max_pq = maxpq;
744 if (has_pq_continue)
745 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
746}
747
748static inline bool dmaf_continue(enum dma_ctrl_flags flags)
749{
750 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
751}
752
753static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
754{
755 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
756
757 return (flags & mask) == mask;
758}
759
760static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
761{
762 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
763}
764
Mathieu Lacaged3f3cf82010-08-14 15:02:44 +0200765static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700766{
767 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
768}
769
770/* dma_maxpq - reduce maxpq in the face of continued operations
771 * @dma - dma device with PQ capability
772 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
773 *
774 * When an engine does not support native continuation we need 3 extra
775 * source slots to reuse P and Q with the following coefficients:
776 * 1/ {00} * P : remove P from Q', but use it as a source for P'
777 * 2/ {01} * Q : use Q to continue Q' calculation
778 * 3/ {00} * Q : subtract Q from P' to cancel (2)
779 *
780 * In the case where P is disabled we only need 1 extra source:
781 * 1/ {01} * Q : use Q to continue Q' calculation
782 */
783static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
784{
785 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
786 return dma_dev_to_maxpq(dma);
787 else if (dmaf_p_disabled_continue(flags))
788 return dma_dev_to_maxpq(dma) - 1;
789 else if (dmaf_continue(flags))
790 return dma_dev_to_maxpq(dma) - 3;
791 BUG();
792}
793
Chris Leechc13c8262006-05-23 17:18:44 -0700794/* --- public DMA engine API --- */
795
Dan Williams649274d2009-01-11 00:20:39 -0800796#ifdef CONFIG_DMA_ENGINE
Dan Williams209b84a2009-01-06 11:38:17 -0700797void dmaengine_get(void);
798void dmaengine_put(void);
Dan Williams649274d2009-01-11 00:20:39 -0800799#else
800static inline void dmaengine_get(void)
801{
802}
803static inline void dmaengine_put(void)
804{
805}
806#endif
807
David S. Millerb4bd07c2009-02-06 22:06:43 -0800808#ifdef CONFIG_NET_DMA
809#define net_dmaengine_get() dmaengine_get()
810#define net_dmaengine_put() dmaengine_put()
811#else
812static inline void net_dmaengine_get(void)
813{
814}
815static inline void net_dmaengine_put(void)
816{
817}
818#endif
819
Dan Williams729b5d12009-03-25 09:13:25 -0700820#ifdef CONFIG_ASYNC_TX_DMA
821#define async_dmaengine_get() dmaengine_get()
822#define async_dmaengine_put() dmaengine_put()
Dan Williams5fc6d892010-10-07 16:44:50 -0700823#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
Dan Williams138f4c32009-09-08 17:42:51 -0700824#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
825#else
Dan Williams729b5d12009-03-25 09:13:25 -0700826#define async_dma_find_channel(type) dma_find_channel(type)
Dan Williams5fc6d892010-10-07 16:44:50 -0700827#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
Dan Williams729b5d12009-03-25 09:13:25 -0700828#else
829static inline void async_dmaengine_get(void)
830{
831}
832static inline void async_dmaengine_put(void)
833{
834}
835static inline struct dma_chan *
836async_dma_find_channel(enum dma_transaction_type type)
837{
838 return NULL;
839}
Dan Williams138f4c32009-09-08 17:42:51 -0700840#endif /* CONFIG_ASYNC_TX_DMA */
Dan Williams729b5d12009-03-25 09:13:25 -0700841
Dan Williams7405f742007-01-02 11:10:43 -0700842dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
843 void *dest, void *src, size_t len);
844dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
845 struct page *page, unsigned int offset, void *kdata, size_t len);
846dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700847 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
Dan Williams7405f742007-01-02 11:10:43 -0700848 unsigned int src_off, size_t len);
849void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
850 struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700851
Dan Williams08398752008-07-17 17:59:56 -0700852static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700853{
Dan Williams636bdea2008-04-17 20:17:26 -0700854 tx->flags |= DMA_CTRL_ACK;
855}
856
Guennadi Liakhovetskief560682009-01-19 15:36:21 -0700857static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
858{
859 tx->flags &= ~DMA_CTRL_ACK;
860}
861
Dan Williams08398752008-07-17 17:59:56 -0700862static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
Dan Williams636bdea2008-04-17 20:17:26 -0700863{
Dan Williams08398752008-07-17 17:59:56 -0700864 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
Chris Leechc13c8262006-05-23 17:18:44 -0700865}
866
Dan Williams7405f742007-01-02 11:10:43 -0700867#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
868static inline void
869__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
870{
871 set_bit(tx_type, dstp->bits);
872}
873
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900874#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
875static inline void
876__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
877{
878 clear_bit(tx_type, dstp->bits);
879}
880
Dan Williams33df8ca2009-01-06 11:38:15 -0700881#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
882static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
883{
884 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
885}
886
Dan Williams7405f742007-01-02 11:10:43 -0700887#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
888static inline int
889__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
890{
891 return test_bit(tx_type, srcp->bits);
892}
893
894#define for_each_dma_cap_mask(cap, mask) \
Akinobu Mitae5a087f2012-10-26 23:35:15 +0900895 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
Dan Williams7405f742007-01-02 11:10:43 -0700896
Chris Leechc13c8262006-05-23 17:18:44 -0700897/**
Dan Williams7405f742007-01-02 11:10:43 -0700898 * dma_async_issue_pending - flush pending transactions to HW
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700899 * @chan: target DMA channel
Chris Leechc13c8262006-05-23 17:18:44 -0700900 *
901 * This allows drivers to push copies to HW in batches,
902 * reducing MMIO writes where possible.
903 */
Dan Williams7405f742007-01-02 11:10:43 -0700904static inline void dma_async_issue_pending(struct dma_chan *chan)
Chris Leechc13c8262006-05-23 17:18:44 -0700905{
Dan Williamsec8670f2008-03-01 07:51:29 -0700906 chan->device->device_issue_pending(chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700907}
908
909/**
Dan Williams7405f742007-01-02 11:10:43 -0700910 * dma_async_is_tx_complete - poll for transaction completion
Chris Leechc13c8262006-05-23 17:18:44 -0700911 * @chan: DMA channel
912 * @cookie: transaction identifier to check status of
913 * @last: returns last completed cookie, can be NULL
914 * @used: returns last issued cookie, can be NULL
915 *
916 * If @last and @used are passed in, upon return they reflect the driver
917 * internal state and can be used with dma_async_is_complete() to check
918 * the status of multiple cookies without re-checking hardware state.
919 */
Dan Williams7405f742007-01-02 11:10:43 -0700920static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700921 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
922{
Linus Walleij07934482010-03-26 16:50:49 -0700923 struct dma_tx_state state;
924 enum dma_status status;
925
926 status = chan->device->device_tx_status(chan, cookie, &state);
927 if (last)
928 *last = state.last;
929 if (used)
930 *used = state.used;
931 return status;
Chris Leechc13c8262006-05-23 17:18:44 -0700932}
933
934/**
935 * dma_async_is_complete - test a cookie against chan state
936 * @cookie: transaction identifier to test status of
937 * @last_complete: last know completed transaction
938 * @last_used: last cookie value handed out
939 *
Bartlomiej Zolnierkiewicze239345f2012-11-08 10:01:01 +0000940 * dma_async_is_complete() is used in dma_async_is_tx_complete()
Sebastian Siewior8a5703f2008-04-21 22:38:45 +0000941 * the test logic is separated for lightweight testing of multiple cookies
Chris Leechc13c8262006-05-23 17:18:44 -0700942 */
943static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
944 dma_cookie_t last_complete, dma_cookie_t last_used)
945{
946 if (last_complete <= last_used) {
947 if ((cookie <= last_complete) || (cookie > last_used))
948 return DMA_SUCCESS;
949 } else {
950 if ((cookie <= last_complete) && (cookie > last_used))
951 return DMA_SUCCESS;
952 }
953 return DMA_IN_PROGRESS;
954}
955
Dan Williamsbca34692010-03-26 16:52:10 -0700956static inline void
957dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
958{
959 if (st) {
960 st->last = last;
961 st->used = used;
962 st->residue = residue;
963 }
964}
965
Dan Williams7405f742007-01-02 11:10:43 -0700966enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
Dan Williams07f22112009-01-05 17:14:31 -0700967#ifdef CONFIG_DMA_ENGINE
968enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
Dan Williamsc50331e2009-01-19 15:33:14 -0700969void dma_issue_pending_all(void);
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +0100970struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
Jon Hunter9a6cecc2012-09-14 17:41:57 -0500971struct dma_chan *dma_request_slave_channel(struct device *dev, char *name);
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +0100972void dma_release_channel(struct dma_chan *chan);
Dan Williams07f22112009-01-05 17:14:31 -0700973#else
974static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
975{
976 return DMA_SUCCESS;
977}
Dan Williamsc50331e2009-01-19 15:33:14 -0700978static inline void dma_issue_pending_all(void)
979{
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +0100980}
981static inline struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask,
982 dma_filter_fn fn, void *fn_param)
983{
984 return NULL;
985}
Jon Hunter9a6cecc2012-09-14 17:41:57 -0500986static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
987 char *name)
988{
Vinod Kould18d5f52012-09-25 16:18:55 +0530989 return NULL;
Jon Hunter9a6cecc2012-09-14 17:41:57 -0500990}
Guennadi Liakhovetski8f33d522010-12-22 14:46:46 +0100991static inline void dma_release_channel(struct dma_chan *chan)
992{
Dan Williamsc50331e2009-01-19 15:33:14 -0700993}
Dan Williams07f22112009-01-05 17:14:31 -0700994#endif
Chris Leechc13c8262006-05-23 17:18:44 -0700995
996/* --- DMA device --- */
997
998int dma_async_device_register(struct dma_device *device);
999void dma_async_device_unregister(struct dma_device *device);
Dan Williams07f22112009-01-05 17:14:31 -07001000void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
Dan Williamsbec08512009-01-06 11:38:14 -07001001struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
Dave Jianga2bd1142012-04-04 16:10:46 -07001002struct dma_chan *net_dma_find_channel(void);
Dan Williams59b5ec22009-01-06 11:38:15 -07001003#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
Matt Porter864ef692013-02-01 18:22:52 +00001004#define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1005 __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1006
1007static inline struct dma_chan
1008*__dma_request_slave_channel_compat(dma_cap_mask_t *mask, dma_filter_fn fn,
1009 void *fn_param, struct device *dev,
1010 char *name)
1011{
1012 struct dma_chan *chan;
1013
1014 chan = dma_request_slave_channel(dev, name);
1015 if (chan)
1016 return chan;
1017
1018 return __dma_request_channel(mask, fn, fn_param);
1019}
Chris Leechc13c8262006-05-23 17:18:44 -07001020
Chris Leechde5506e2006-05-23 17:50:37 -07001021/* --- Helper iov-locking functions --- */
1022
1023struct dma_page_list {
Al Virob2ddb902008-03-29 03:09:38 +00001024 char __user *base_address;
Chris Leechde5506e2006-05-23 17:50:37 -07001025 int nr_pages;
1026 struct page **pages;
1027};
1028
1029struct dma_pinned_list {
1030 int nr_iovecs;
1031 struct dma_page_list page_list[0];
1032};
1033
1034struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
1035void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
1036
1037dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
1038 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
1039dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
1040 struct dma_pinned_list *pinned_list, struct page *page,
1041 unsigned int offset, size_t len);
1042
Chris Leechc13c8262006-05-23 17:18:44 -07001043#endif /* DMAENGINE_H */