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gerrit-public.fairphone.software / kernel / msm-4.19 / c784b1e2ece8a591263050d1f59607547dfad8f3 / . / include / media / adv7604.h
blob: 6186771c0642fbfc33c7c8a47077f21c10b3a5af [file] [log] [blame]
Hans Verkuil54450f52012-07-18 05:45:16 -0300[diff] [blame]1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21#ifndef _ADV7604_
22#define _ADV7604_
23
Lars-Peter Clausene5e749d2013-11-21 11:23:45 -0300[diff] [blame]24#include <linux/types.h>
25
Hans Verkuil54450f52012-07-18 05:45:16 -0300[diff] [blame]26/* Analog input muxing modes (AFE register 0x02, [2:0]) */
27enum adv7604_ain_sel {
28 ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
29 ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
30 ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
31 ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
32 ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
33};
34
35/* Bus rotation and reordering (IO register 0x04, [7:5]) */
36enum adv7604_op_ch_sel {
37 ADV7604_OP_CH_SEL_GBR = 0,
38 ADV7604_OP_CH_SEL_GRB = 1,
39 ADV7604_OP_CH_SEL_BGR = 2,
40 ADV7604_OP_CH_SEL_RGB = 3,
41 ADV7604_OP_CH_SEL_BRG = 4,
42 ADV7604_OP_CH_SEL_RBG = 5,
43};
44
Hans Verkuil54450f52012-07-18 05:45:16 -0300[diff] [blame]45/* Input Color Space (IO register 0x02, [7:4]) */
46enum adv7604_inp_color_space {
47 ADV7604_INP_COLOR_SPACE_LIM_RGB = 0,
48 ADV7604_INP_COLOR_SPACE_FULL_RGB = 1,
49 ADV7604_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
50 ADV7604_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
51 ADV7604_INP_COLOR_SPACE_XVYCC_601 = 4,
52 ADV7604_INP_COLOR_SPACE_XVYCC_709 = 5,
53 ADV7604_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
54 ADV7604_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
55 ADV7604_INP_COLOR_SPACE_AUTO = 0xf,
56};
57
58/* Select output format (IO register 0x03, [7:0]) */
59enum adv7604_op_format_sel {
60 ADV7604_OP_FORMAT_SEL_SDR_ITU656_8 = 0x00,
61 ADV7604_OP_FORMAT_SEL_SDR_ITU656_10 = 0x01,
62 ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE0 = 0x02,
63 ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE1 = 0x06,
64 ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE2 = 0x0a,
65 ADV7604_OP_FORMAT_SEL_DDR_422_8 = 0x20,
66 ADV7604_OP_FORMAT_SEL_DDR_422_10 = 0x21,
67 ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE0 = 0x22,
68 ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE1 = 0x23,
69 ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE2 = 0x24,
70 ADV7604_OP_FORMAT_SEL_SDR_444_24 = 0x40,
71 ADV7604_OP_FORMAT_SEL_SDR_444_30 = 0x41,
72 ADV7604_OP_FORMAT_SEL_SDR_444_36_MODE0 = 0x42,
73 ADV7604_OP_FORMAT_SEL_DDR_444_24 = 0x60,
74 ADV7604_OP_FORMAT_SEL_DDR_444_30 = 0x61,
75 ADV7604_OP_FORMAT_SEL_DDR_444_36 = 0x62,
76 ADV7604_OP_FORMAT_SEL_SDR_ITU656_16 = 0x80,
77 ADV7604_OP_FORMAT_SEL_SDR_ITU656_20 = 0x81,
78 ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE0 = 0x82,
79 ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE1 = 0x86,
80 ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE2 = 0x8a,
81};
82
Mikhail Khelikf31b62e2013-12-20 05:12:00 -0300[diff] [blame]83enum adv7604_drive_strength {
84 ADV7604_DR_STR_MEDIUM_LOW = 1,
85 ADV7604_DR_STR_MEDIUM_HIGH = 2,
86 ADV7604_DR_STR_HIGH = 3,
87};
88
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300[diff] [blame]89enum adv7604_int1_config {
90 ADV7604_INT1_CONFIG_OPEN_DRAIN,
91 ADV7604_INT1_CONFIG_ACTIVE_LOW,
92 ADV7604_INT1_CONFIG_ACTIVE_HIGH,
93 ADV7604_INT1_CONFIG_DISABLED,
94};
95
Hans Verkuil54450f52012-07-18 05:45:16 -0300[diff] [blame]96/* Platform dependent definition */
97struct adv7604_platform_data {
Hans Verkuil54450f52012-07-18 05:45:16 -0300[diff] [blame]98 /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
99 unsigned disable_pwrdnb:1;
100
101 /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
102 unsigned disable_cable_det_rst:1;
103
104 /* Analog input muxing mode */
105 enum adv7604_ain_sel ain_sel;
106
107 /* Bus rotation and reordering */
108 enum adv7604_op_ch_sel op_ch_sel;
109
Hans Verkuil54450f52012-07-18 05:45:16 -0300[diff] [blame]110 /* Select output format */
111 enum adv7604_op_format_sel op_format_sel;
112
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300[diff] [blame]113 /* Configuration of the INT1 pin */
114 enum adv7604_int1_config int1_config;
115
Hans Verkuil54450f52012-07-18 05:45:16 -0300[diff] [blame]116 /* IO register 0x02 */
117 unsigned alt_gamma:1;
118 unsigned op_656_range:1;
119 unsigned rgb_out:1;
120 unsigned alt_data_sat:1;
121
122 /* IO register 0x05 */
123 unsigned blank_data:1;
124 unsigned insert_av_codes:1;
125 unsigned replicate_av_codes:1;
126 unsigned invert_cbcr:1;
127
Martin Bugge98908692013-12-20 05:14:57 -0300[diff] [blame]128 /* IO register 0x06 */
129 unsigned inv_vs_pol:1;
130 unsigned inv_hs_pol:1;
131
Mikhail Khelikf31b62e2013-12-20 05:12:00 -0300[diff] [blame]132 /* IO register 0x14 */
133 enum adv7604_drive_strength dr_str_data;
134 enum adv7604_drive_strength dr_str_clk;
135 enum adv7604_drive_strength dr_str_sync;
136
Hans Verkuil54450f52012-07-18 05:45:16 -0300[diff] [blame]137 /* IO register 0x30 */
138 unsigned output_bus_lsb_to_msb:1;
139
140 /* Free run */
141 unsigned hdmi_free_run_mode;
142
143 /* i2c addresses: 0 == use default */
144 u8 i2c_avlink;
145 u8 i2c_cec;
146 u8 i2c_infoframe;
147 u8 i2c_esdp;
148 u8 i2c_dpp;
149 u8 i2c_afe;
150 u8 i2c_repeater;
151 u8 i2c_edid;
152 u8 i2c_hdmi;
153 u8 i2c_test;
154 u8 i2c_cp;
155 u8 i2c_vdp;
156};
157
Laurent Pinchartc784b1e2014-01-29 10:08:58 -0300[diff] [blame^]158enum adv7604_pad {
159 ADV7604_PAD_HDMI_PORT_A = 0,
160 ADV7604_PAD_HDMI_PORT_B = 1,
161 ADV7604_PAD_HDMI_PORT_C = 2,
162 ADV7604_PAD_HDMI_PORT_D = 3,
163 ADV7604_PAD_VGA_RGB = 4,
164 ADV7604_PAD_VGA_COMP = 5,
165 /* The source pad is either 1 (ADV7611) or 6 (ADV7604) */
166 ADV7604_PAD_SOURCE = 6,
167 ADV7611_PAD_SOURCE = 1,
168 ADV7604_PAD_MAX = 7,
Hans Verkuil6b0d5d32012-10-16 06:40:45 -0300[diff] [blame]169};
170
Hans Verkuil54450f52012-07-18 05:45:16 -0300[diff] [blame]171#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
172#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
173#define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
174
175/* notify events */
176#define ADV7604_HOTPLUG 1
177#define ADV7604_FMT_CHANGE 2
178
179#endif