blob: f80773b7f9ef1efc3c25477b2b74c1543b514fff [file] [log] [blame]
Pan Wenc80dfd92016-11-14 10:49:54 +08001config COMMON_CLK_HI3516CV300
2 tristate "HI3516CV300 Clock Driver"
3 depends on ARCH_HISI || COMPILE_TEST
4 select RESET_HISI
5 default ARCH_HISI
6 help
7 Build the clock driver for hi3516cv300.
8
Jiancheng Xue6c9da382016-04-23 15:40:30 +08009config COMMON_CLK_HI3519
10 tristate "Hi3519 Clock Driver"
11 depends on ARCH_HISI || COMPILE_TEST
12 select RESET_HISI
13 default ARCH_HISI
14 help
15 Build the clock driver for hi3519.
16
Jiancheng Xue707d33c2016-10-29 14:13:37 +080017config COMMON_CLK_HI3798CV200
18 tristate "Hi3798CV200 Clock Driver"
19 depends on ARCH_HISI || COMPILE_TEST
20 select RESET_HISI
21 default ARCH_HISI
22 help
23 Build the clock driver for hi3798cv200.
24
Bintian Wang72ea4862015-05-29 10:08:38 +080025config COMMON_CLK_HI6220
26 bool "Hi6220 Clock Driver"
Leo Yan9f42a892015-09-02 10:57:47 +080027 depends on ARCH_HISI || COMPILE_TEST
Bintian Wang72ea4862015-05-29 10:08:38 +080028 default ARCH_HISI
29 help
30 Build the Hisilicon Hi6220 clock driver based on the common clock framework.
Leo Yan9f42a892015-09-02 10:57:47 +080031
Jiancheng Xue25824d52016-04-23 15:40:28 +080032config RESET_HISI
33 bool "HiSilicon Reset Controller Driver"
34 depends on ARCH_HISI || COMPILE_TEST
35 select RESET_CONTROLLER
36 help
37 Build reset controller driver for HiSilicon device chipsets.
38
Leo Yan9f42a892015-09-02 10:57:47 +080039config STUB_CLK_HI6220
40 bool "Hi6220 Stub Clock Driver"
41 depends on COMMON_CLK_HI6220 && MAILBOX
42 help
43 Build the Hisilicon Hi6220 stub clock driver.