| Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 2 | #ifndef __ASM_ASM_UACCESS_H |
| 3 | #define __ASM_ASM_UACCESS_H |
| 4 | |
| 5 | #include <asm/alternative.h> |
| 6 | #include <asm/kernel-pgtable.h> |
| Will Deacon | b519538 | 2017-12-01 17:33:48 +0000 | [diff] [blame] | 7 | #include <asm/mmu.h> |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 8 | #include <asm/sysreg.h> |
| 9 | #include <asm/assembler.h> |
| 10 | |
| 11 | /* |
| 12 | * User access enabling/disabling macros. |
| 13 | */ |
| 14 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 15 | .macro __uaccess_ttbr0_disable, tmp1 |
| Steve Capper | 9dfe482 | 2018-01-11 10:11:57 +0000 | [diff] [blame] | 16 | mrs \tmp1, ttbr1_el1 // swapper_pg_dir |
| Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 17 | bic \tmp1, \tmp1, #TTBR_ASID_MASK |
| Steve Capper | 9dfe482 | 2018-01-11 10:11:57 +0000 | [diff] [blame] | 18 | sub \tmp1, \tmp1, #RESERVED_TTBR0_SIZE // reserved_ttbr0 just before swapper_pg_dir |
| 19 | msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 20 | isb |
| Steve Capper | 9dfe482 | 2018-01-11 10:11:57 +0000 | [diff] [blame] | 21 | add \tmp1, \tmp1, #RESERVED_TTBR0_SIZE |
| Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 22 | msr ttbr1_el1, \tmp1 // set reserved ASID |
| 23 | isb |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 24 | .endm |
| 25 | |
| Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 26 | .macro __uaccess_ttbr0_enable, tmp1, tmp2 |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 27 | get_thread_info \tmp1 |
| 28 | ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 |
| Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 29 | mrs \tmp2, ttbr1_el1 |
| 30 | extr \tmp2, \tmp2, \tmp1, #48 |
| 31 | ror \tmp2, \tmp2, #16 |
| 32 | msr ttbr1_el1, \tmp2 // set the active ASID |
| 33 | isb |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 34 | msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 |
| 35 | isb |
| 36 | .endm |
| 37 | |
| Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 38 | .macro uaccess_ttbr0_disable, tmp1, tmp2 |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 39 | alternative_if_not ARM64_HAS_PAN |
| Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 40 | save_and_disable_irq \tmp2 // avoid preemption |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 41 | __uaccess_ttbr0_disable \tmp1 |
| Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 42 | restore_irq \tmp2 |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 43 | alternative_else_nop_endif |
| 44 | .endm |
| 45 | |
| Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 46 | .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 47 | alternative_if_not ARM64_HAS_PAN |
| Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 48 | save_and_disable_irq \tmp3 // avoid preemption |
| 49 | __uaccess_ttbr0_enable \tmp1, \tmp2 |
| 50 | restore_irq \tmp3 |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 51 | alternative_else_nop_endif |
| 52 | .endm |
| 53 | #else |
| Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 54 | .macro uaccess_ttbr0_disable, tmp1, tmp2 |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 55 | .endm |
| 56 | |
| Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 57 | .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 58 | .endm |
| 59 | #endif |
| 60 | |
| 61 | /* |
| 62 | * These macros are no-ops when UAO is present. |
| 63 | */ |
| Catalin Marinas | 6b88a32 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 64 | .macro uaccess_disable_not_uao, tmp1, tmp2 |
| 65 | uaccess_ttbr0_disable \tmp1, \tmp2 |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 66 | alternative_if ARM64_ALT_PAN_NOT_UAO |
| 67 | SET_PSTATE_PAN(1) |
| 68 | alternative_else_nop_endif |
| 69 | .endm |
| 70 | |
| Will Deacon | 27a921e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 71 | .macro uaccess_enable_not_uao, tmp1, tmp2, tmp3 |
| 72 | uaccess_ttbr0_enable \tmp1, \tmp2, \tmp3 |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 73 | alternative_if ARM64_ALT_PAN_NOT_UAO |
| 74 | SET_PSTATE_PAN(0) |
| 75 | alternative_else_nop_endif |
| 76 | .endm |
| 77 | |
| Kristina Martsenko | 276e932 | 2017-05-03 16:37:47 +0100 | [diff] [blame] | 78 | /* |
| 79 | * Remove the address tag from a virtual address, if present. |
| 80 | */ |
| Will Deacon | 2cf899d | 2019-10-15 21:04:18 -0700 | [diff] [blame] | 81 | .macro untagged_addr, dst, addr |
| 82 | sbfx \dst, \addr, #0, #56 |
| 83 | and \dst, \dst, \addr |
| Kristina Martsenko | 276e932 | 2017-05-03 16:37:47 +0100 | [diff] [blame] | 84 | .endm |
| 85 | |
| Al Viro | b4b8664 | 2016-12-26 04:10:19 -0500 | [diff] [blame] | 86 | #endif |