blob: 73288c6077e56ad526daa0cfc47296a14d5ed519 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
Jerome Glissed39c3b82009-09-28 18:34:43 +020045/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
Arun Sharma600634972011-07-26 16:09:06 -070063#include <linux/atomic.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020064#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
Alex Deucher0aea5e42014-07-30 11:49:56 -040067#include <linux/interval_tree.h>
Christian König341cb9e2014-08-07 09:36:03 +020068#include <linux/hashtable.h>
Maarten Lankhorst954605c2014-01-09 11:03:12 +010069#include <linux/fence.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020070
Jerome Glisse4c788672009-11-20 14:29:23 +010071#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
Thomas Hellstrom147666f2010-11-17 12:38:32 +000075#include <ttm/ttm_execbuf_util.h>
Jerome Glisse4c788672009-11-20 14:29:23 +010076
Daniel Vetterd9fc9412014-09-23 15:46:53 +020077#include <drm/drm_gem.h>
78
Dave Airliec2142712009-09-22 08:50:10 +100079#include "radeon_family.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020080#include "radeon_mode.h"
81#include "radeon_reg.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020082
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
Michel Dänzerecc0b322009-07-21 11:23:57 +020094extern int radeon_testing;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020095extern int radeon_connector_table;
Dave Airlie4ce001a2009-08-13 16:32:14 +100096extern int radeon_tv;
Christian Koenigdafc3bd2009-10-11 23:49:13 +020097extern int radeon_audio;
Alex Deucherf46c0122010-03-31 00:33:27 -040098extern int radeon_disp_priority;
Alex Deuchere2b0a8e2010-03-17 02:07:37 -040099extern int radeon_hw_i2c;
Alex Deucherd42dd572011-01-12 20:05:11 -0500100extern int radeon_pcie_gen2;
Alex Deuchera18cee12011-11-01 14:20:30 -0400101extern int radeon_msi;
Christian König3368ff02012-05-02 15:11:21 +0200102extern int radeon_lockup_timeout;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400103extern int radeon_fastfb;
Alex Deucherda321c82013-04-12 13:55:22 -0400104extern int radeon_dpm;
Alex Deucher1294d4a2013-07-16 15:58:50 -0400105extern int radeon_aspm;
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000106extern int radeon_runtime_pm;
Alex Deucher363eb0b2014-01-08 17:55:08 -0500107extern int radeon_hard_reset;
Christian Königc1c44132014-06-05 23:47:32 -0400108extern int radeon_vm_size;
Christian König4510fb92014-06-05 23:56:50 -0400109extern int radeon_vm_block_size;
Alex Deuchera624f422014-07-01 11:23:03 -0400110extern int radeon_deep_color;
Mario Kleiner39dc5452014-07-29 06:21:44 +0200111extern int radeon_use_pflipirq;
Alex Deucher6e909f72014-08-07 09:28:31 -0400112extern int radeon_bapm;
Alex Deucherbc130182014-09-16 20:57:26 -0400113extern int radeon_backlight;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200114
115/*
116 * Copy from radeon_drv.h so we don't have to include both and have conflicting
117 * symbol;
118 */
Jerome Glissebb635562012-05-09 15:34:46 +0200119#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
120#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
Jerome Glissee8217672010-02-15 21:36:13 +0100121/* RADEON_IB_POOL_SIZE must be a power of 2 */
Jerome Glissebb635562012-05-09 15:34:46 +0200122#define RADEON_IB_POOL_SIZE 16
123#define RADEON_DEBUGFS_MAX_COMPONENTS 32
124#define RADEONFB_CONN_LIMIT 4
125#define RADEON_BIOS_NUM_SCRATCH 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200126
Alex Deucher1b370782011-11-17 20:13:28 -0500127/* internal ring indices */
128/* r1xx+ has gfx CP ring */
Christian Königd93f7932013-05-23 12:10:04 +0200129#define RADEON_RING_TYPE_GFX_INDEX 0
Alex Deucher1b370782011-11-17 20:13:28 -0500130
131/* cayman has 2 compute CP rings */
Christian Königd93f7932013-05-23 12:10:04 +0200132#define CAYMAN_RING_TYPE_CP1_INDEX 1
133#define CAYMAN_RING_TYPE_CP2_INDEX 2
Alex Deucher1b370782011-11-17 20:13:28 -0500134
Alex Deucher4d756582012-09-27 15:08:35 -0400135/* R600+ has an async dma ring */
136#define R600_RING_TYPE_DMA_INDEX 3
Alex Deucherf60cbd12012-12-04 15:27:33 -0500137/* cayman add a second async dma ring */
138#define CAYMAN_RING_TYPE_DMA1_INDEX 4
Alex Deucher4d756582012-09-27 15:08:35 -0400139
Christian Königf2ba57b2013-04-08 12:41:29 +0200140/* R600+ */
Christian Königd93f7932013-05-23 12:10:04 +0200141#define R600_RING_TYPE_UVD_INDEX 5
142
143/* TN+ */
144#define TN_RING_TYPE_VCE1_INDEX 6
145#define TN_RING_TYPE_VCE2_INDEX 7
146
147/* max number of rings */
148#define RADEON_NUM_RINGS 8
Christian Königf2ba57b2013-04-08 12:41:29 +0200149
Christian König1c61eae2014-02-18 01:50:22 -0700150/* number of hw syncs before falling back on blocking */
151#define RADEON_NUM_SYNCS 4
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200152
Christian König8f534922014-02-18 11:37:20 +0100153/* number of hw syncs before falling back on blocking */
154#define RADEON_NUM_SYNCS 4
155
Jerome Glisse721604a2012-01-05 22:11:05 -0500156/* hardcode those limit for now */
Christian Königca19f212012-09-11 16:09:59 +0200157#define RADEON_VA_IB_OFFSET (1 << 20)
Jerome Glissebb635562012-05-09 15:34:46 +0200158#define RADEON_VA_RESERVED_SIZE (8 << 20)
159#define RADEON_IB_VM_MAX_SIZE (64 << 10)
Jerome Glisse721604a2012-01-05 22:11:05 -0500160
Alex Deucher1a0041b2013-10-02 13:01:36 -0400161/* hard reset data */
162#define RADEON_ASIC_RESET_DATA 0x39d5e86b
163
Alex Deucherec46c762013-01-03 12:07:30 -0500164/* reset flags */
165#define RADEON_RESET_GFX (1 << 0)
166#define RADEON_RESET_COMPUTE (1 << 1)
167#define RADEON_RESET_DMA (1 << 2)
Alex Deucher9ff07442013-01-18 12:18:17 -0500168#define RADEON_RESET_CP (1 << 3)
169#define RADEON_RESET_GRBM (1 << 4)
170#define RADEON_RESET_DMA1 (1 << 5)
171#define RADEON_RESET_RLC (1 << 6)
172#define RADEON_RESET_SEM (1 << 7)
173#define RADEON_RESET_IH (1 << 8)
174#define RADEON_RESET_VMC (1 << 9)
175#define RADEON_RESET_MC (1 << 10)
176#define RADEON_RESET_DISPLAY (1 << 11)
Alex Deucherec46c762013-01-03 12:07:30 -0500177
Alex Deucher22c775c2013-07-23 09:41:05 -0400178/* CG block flags */
179#define RADEON_CG_BLOCK_GFX (1 << 0)
180#define RADEON_CG_BLOCK_MC (1 << 1)
181#define RADEON_CG_BLOCK_SDMA (1 << 2)
182#define RADEON_CG_BLOCK_UVD (1 << 3)
183#define RADEON_CG_BLOCK_VCE (1 << 4)
184#define RADEON_CG_BLOCK_HDP (1 << 5)
Alex Deuchere16866e2013-08-08 19:34:07 -0400185#define RADEON_CG_BLOCK_BIF (1 << 6)
Alex Deucher22c775c2013-07-23 09:41:05 -0400186
Alex Deucher64d8a722013-08-08 16:31:25 -0400187/* CG flags */
188#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
189#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
190#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
191#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
192#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
193#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
194#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
195#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
196#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
197#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
198#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
199#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
200#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
201#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
202#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
203#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
204#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
205
206/* PG flags */
Alex Deucher2b19d172013-09-04 16:58:29 -0400207#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
Alex Deucher64d8a722013-08-08 16:31:25 -0400208#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
209#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
210#define RADEON_PG_SUPPORT_UVD (1 << 3)
211#define RADEON_PG_SUPPORT_VCE (1 << 4)
212#define RADEON_PG_SUPPORT_CP (1 << 5)
213#define RADEON_PG_SUPPORT_GDS (1 << 6)
214#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
215#define RADEON_PG_SUPPORT_SDMA (1 << 8)
216#define RADEON_PG_SUPPORT_ACP (1 << 9)
217#define RADEON_PG_SUPPORT_SAMU (1 << 10)
218
Alex Deucher9e05fa12013-01-24 10:06:33 -0500219/* max cursor sizes (in pixels) */
220#define CURSOR_WIDTH 64
221#define CURSOR_HEIGHT 64
222
223#define CIK_CURSOR_WIDTH 128
224#define CIK_CURSOR_HEIGHT 128
225
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200226/*
227 * Errata workarounds.
228 */
229enum radeon_pll_errata {
230 CHIP_ERRATA_R300_CG = 0x00000001,
231 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
232 CHIP_ERRATA_PLL_DELAY = 0x00000004
233};
234
235
236struct radeon_device;
237
238
239/*
240 * BIOS.
241 */
242bool radeon_get_bios(struct radeon_device *rdev);
243
Jerome Glisse9fc04b52012-01-23 11:52:15 -0500244/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000245 * Dummy page
246 */
247struct radeon_dummy_page {
248 struct page *page;
249 dma_addr_t addr;
250};
251int radeon_dummy_page_init(struct radeon_device *rdev);
252void radeon_dummy_page_fini(struct radeon_device *rdev);
253
254
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200255/*
256 * Clocks
257 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200258struct radeon_clock {
259 struct radeon_pll p1pll;
260 struct radeon_pll p2pll;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500261 struct radeon_pll dcpll;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200262 struct radeon_pll spll;
263 struct radeon_pll mpll;
264 /* 10 Khz units */
265 uint32_t default_mclk;
266 uint32_t default_sclk;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500267 uint32_t default_dispclk;
Alex Deucher4489cd622013-03-22 15:59:10 -0400268 uint32_t current_dispclk;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500269 uint32_t dp_extclk;
Alex Deucherb20f9be2011-06-08 13:01:11 -0400270 uint32_t max_pixel_clock;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200271};
272
Rafał Miłecki74338742009-11-03 00:53:02 +0100273/*
274 * Power management
275 */
276int radeon_pm_init(struct radeon_device *rdev);
Alex Deucher914a8982013-12-19 11:37:22 -0500277int radeon_pm_late_init(struct radeon_device *rdev);
Alex Deucher29fb52c2010-03-11 10:01:17 -0500278void radeon_pm_fini(struct radeon_device *rdev);
Rafał Miłeckic913e232009-12-22 23:02:16 +0100279void radeon_pm_compute_clocks(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400280void radeon_pm_suspend(struct radeon_device *rdev);
281void radeon_pm_resume(struct radeon_device *rdev);
Alex Deucher56278a82009-12-28 13:58:44 -0500282void radeon_combios_get_power_modes(struct radeon_device *rdev);
283void radeon_atombios_get_power_modes(struct radeon_device *rdev);
Christian König7062ab62013-04-08 12:41:31 +0200284int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
285 u8 clock_type,
286 u32 clock,
287 bool strobe_mode,
288 struct atom_clock_dividers *dividers);
Alex Deuchereaa778a2013-02-13 16:38:25 -0500289int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
290 u32 clock,
291 bool strobe_mode,
292 struct atom_mpll_param *mpll_param);
Alex Deucher8a83ec52011-04-12 14:49:23 -0400293void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400294int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
295 u16 voltage_level, u8 voltage_type,
296 u32 *gpio_value, u32 *gpio_mask);
297void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
298 u32 eng_clock, u32 mem_clock);
299int radeon_atom_get_voltage_step(struct radeon_device *rdev,
300 u8 voltage_type, u16 *voltage_step);
Alex Deucher4a6369e2013-04-12 14:04:10 -0400301int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
302 u16 voltage_id, u16 *voltage);
Alex Deucherbeb79f42013-02-19 17:14:43 -0500303int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
304 u16 *voltage,
305 u16 leakage_idx);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400306int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
307 u16 *leakage_id);
308int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
309 u16 *vddc, u16 *vddci,
310 u16 virtual_voltage_id,
311 u16 vbios_voltage_id);
Alex Deuchere9f274b2014-07-31 17:57:42 -0400312int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
313 u16 virtual_voltage_id,
314 u16 *voltage);
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400315int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
316 u8 voltage_type,
317 u16 nominal_voltage,
318 u16 *true_voltage);
319int radeon_atom_get_min_voltage(struct radeon_device *rdev,
320 u8 voltage_type, u16 *min_voltage);
321int radeon_atom_get_max_voltage(struct radeon_device *rdev,
322 u8 voltage_type, u16 *max_voltage);
323int radeon_atom_get_voltage_table(struct radeon_device *rdev,
Alex Deucher65171942013-02-13 17:29:54 -0500324 u8 voltage_type, u8 voltage_mode,
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400325 struct atom_voltage_table *voltage_table);
Alex Deucher58653ab2013-02-13 17:04:59 -0500326bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
327 u8 voltage_type, u8 voltage_mode);
Alex Deucher636e2582014-06-06 18:43:45 -0400328int radeon_atom_get_svi2_info(struct radeon_device *rdev,
329 u8 voltage_type,
330 u8 *svd_gpio_id, u8 *svc_gpio_id);
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400331void radeon_atom_update_memory_dll(struct radeon_device *rdev,
332 u32 mem_clock);
333void radeon_atom_set_ac_timing(struct radeon_device *rdev,
334 u32 mem_clock);
335int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
336 u8 module_index,
337 struct atom_mc_reg_table *reg_table);
338int radeon_atom_get_memory_info(struct radeon_device *rdev,
339 u8 module_index, struct atom_memory_info *mem_info);
340int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
341 bool gddr5, u8 module_index,
342 struct atom_memory_clock_range_table *mclk_range_table);
343int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
344 u16 voltage_id, u16 *voltage);
Alex Deucherf8920342010-06-30 12:02:03 -0400345void rs690_pm_info(struct radeon_device *rdev);
Jerome Glisse285484e2011-12-16 17:03:42 -0500346extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
347 unsigned *bankh, unsigned *mtaspect,
348 unsigned *tile_split);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000349
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200350/*
351 * Fences.
352 */
353struct radeon_fence_driver {
Christian König0bfa4b42014-08-27 15:21:58 +0200354 struct radeon_device *rdev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200355 uint32_t scratch_reg;
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000356 uint64_t gpu_addr;
357 volatile uint32_t *cpu_addr;
Christian König68e250b2012-05-10 15:57:31 +0200358 /* sync_seq is protected by ring emission lock */
359 uint64_t sync_seq[RADEON_NUM_RINGS];
Jerome Glissebb635562012-05-09 15:34:46 +0200360 atomic64_t last_seq;
Maarten Lankhorst954605c2014-01-09 11:03:12 +0100361 bool initialized, delayed_irq;
Christian König0bfa4b42014-08-27 15:21:58 +0200362 struct delayed_work lockup_work;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200363};
364
365struct radeon_fence {
Maarten Lankhorst954605c2014-01-09 11:03:12 +0100366 struct fence base;
367
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200368 struct radeon_device *rdev;
Jerome Glissebb635562012-05-09 15:34:46 +0200369 uint64_t seq;
Alex Deucher74652802011-08-25 13:39:48 -0400370 /* RB, DMA, etc. */
Jerome Glissebb635562012-05-09 15:34:46 +0200371 unsigned ring;
Maarten Lankhorst954605c2014-01-09 11:03:12 +0100372
373 wait_queue_t fence_wake;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200374};
375
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000376int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
377int radeon_fence_driver_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200378void radeon_fence_driver_fini(struct radeon_device *rdev);
Christian Königeb98c702014-08-27 15:21:56 +0200379void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
Christian König876dc9f2012-05-08 14:24:01 +0200380int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
Alex Deucher74652802011-08-25 13:39:48 -0400381void radeon_fence_process(struct radeon_device *rdev, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200382bool radeon_fence_signaled(struct radeon_fence *fence);
383int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
Christian König37615522014-02-18 15:58:31 +0100384int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
385int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
Jerome Glisse0085c9502012-05-09 15:34:55 +0200386int radeon_fence_wait_any(struct radeon_device *rdev,
387 struct radeon_fence **fences,
388 bool intr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200389struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
390void radeon_fence_unref(struct radeon_fence **fence);
Jerome Glisse3b7a2b22012-05-09 15:34:47 +0200391unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
Christian König68e250b2012-05-10 15:57:31 +0200392bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
393void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
394static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
395 struct radeon_fence *b)
396{
397 if (!a) {
398 return b;
399 }
400
401 if (!b) {
402 return a;
403 }
404
405 BUG_ON(a->ring != b->ring);
406
407 if (a->seq > b->seq) {
408 return a;
409 } else {
410 return b;
411 }
412}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200413
Christian Königee60e292012-08-09 16:21:08 +0200414static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
415 struct radeon_fence *b)
416{
417 if (!a) {
418 return false;
419 }
420
421 if (!b) {
422 return true;
423 }
424
425 BUG_ON(a->ring != b->ring);
426
427 return a->seq < b->seq;
428}
429
Dave Airliee024e112009-06-24 09:48:08 +1000430/*
431 * Tiling registers
432 */
433struct radeon_surface_reg {
Jerome Glisse4c788672009-11-20 14:29:23 +0100434 struct radeon_bo *bo;
Dave Airliee024e112009-06-24 09:48:08 +1000435};
436
437#define RADEON_GEM_MAX_SURFACES 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200438
439/*
Jerome Glisse4c788672009-11-20 14:29:23 +0100440 * TTM.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200441 */
Jerome Glisse4c788672009-11-20 14:29:23 +0100442struct radeon_mman {
443 struct ttm_bo_global_ref bo_global_ref;
Dave Airlieba4420c2010-03-09 10:56:52 +1000444 struct drm_global_reference mem_global_ref;
Jerome Glisse4c788672009-11-20 14:29:23 +0100445 struct ttm_bo_device bdev;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100446 bool mem_global_referenced;
447 bool initialized;
Christian König2014b562013-12-18 21:07:39 +0100448
449#if defined(CONFIG_DEBUG_FS)
450 struct dentry *vram;
Christian Königdd66d202013-12-18 21:07:40 +0100451 struct dentry *gtt;
Christian König2014b562013-12-18 21:07:39 +0100452#endif
Jerome Glisse4c788672009-11-20 14:29:23 +0100453};
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200454
Jerome Glisse721604a2012-01-05 22:11:05 -0500455/* bo virtual address in a specific vm */
456struct radeon_bo_va {
Christian Könige971bd52012-09-11 16:10:04 +0200457 /* protected by bo being reserved */
Jerome Glisse721604a2012-01-05 22:11:05 -0500458 struct list_head bo_list;
Jerome Glisse721604a2012-01-05 22:11:05 -0500459 uint32_t flags;
Christian Könige31ad962014-07-18 09:24:53 +0200460 uint64_t addr;
Christian Könige971bd52012-09-11 16:10:04 +0200461 unsigned ref_count;
462
463 /* protected by vm mutex */
Alex Deucher0aea5e42014-07-30 11:49:56 -0400464 struct interval_tree_node it;
Christian König036bf462014-07-18 08:56:40 +0200465 struct list_head vm_status;
Christian Könige971bd52012-09-11 16:10:04 +0200466
467 /* constant after initialization */
468 struct radeon_vm *vm;
469 struct radeon_bo *bo;
Jerome Glisse721604a2012-01-05 22:11:05 -0500470};
471
Jerome Glisse4c788672009-11-20 14:29:23 +0100472struct radeon_bo {
473 /* Protected by gem.mutex */
474 struct list_head list;
475 /* Protected by tbo.reserved */
Marek Olšákbda72d52014-03-02 00:56:17 +0100476 u32 initial_domain;
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900477 struct ttm_place placements[4];
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100478 struct ttm_placement placement;
Jerome Glisse4c788672009-11-20 14:29:23 +0100479 struct ttm_buffer_object tbo;
480 struct ttm_bo_kmap_obj kmap;
Michel Dänzer02376d82014-07-17 19:01:08 +0900481 u32 flags;
Jerome Glisse4c788672009-11-20 14:29:23 +0100482 unsigned pin_count;
483 void *kptr;
484 u32 tiling_flags;
485 u32 pitch;
486 int surface_reg;
Jerome Glisse721604a2012-01-05 22:11:05 -0500487 /* list of all virtual address to which this bo
488 * is associated to
489 */
490 struct list_head va;
Jerome Glisse4c788672009-11-20 14:29:23 +0100491 /* Constant after initialization */
492 struct radeon_device *rdev;
Daniel Vetter441921d2011-02-18 17:59:16 +0100493 struct drm_gem_object gem_base;
Dave Airlie63bc6202012-05-31 13:52:53 +0100494
Jerome Glisse409851f2013-04-25 22:29:27 -0400495 struct ttm_bo_kmap_obj dma_buf_vmap;
496 pid_t pid;
Christian König341cb9e2014-08-07 09:36:03 +0200497
498 struct radeon_mn *mn;
499 struct interval_tree_node mn_it;
Jerome Glisse4c788672009-11-20 14:29:23 +0100500};
Daniel Vetter7e4d15d2011-02-18 17:59:17 +0100501#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
Jerome Glisse4c788672009-11-20 14:29:23 +0100502
Jerome Glisse409851f2013-04-25 22:29:27 -0400503int radeon_gem_debugfs_init(struct radeon_device *rdev);
504
Jerome Glisseb15ba512011-11-15 11:48:34 -0500505/* sub-allocation manager, it has to be protected by another lock.
506 * By conception this is an helper for other part of the driver
507 * like the indirect buffer or semaphore, which both have their
508 * locking.
509 *
510 * Principe is simple, we keep a list of sub allocation in offset
511 * order (first entry has offset == 0, last entry has the highest
512 * offset).
513 *
514 * When allocating new object we first check if there is room at
515 * the end total_size - (last_object_offset + last_object_size) >=
516 * alloc_size. If so we allocate new object there.
517 *
518 * When there is not enough room at the end, we start waiting for
519 * each sub object until we reach object_offset+object_size >=
520 * alloc_size, this object then become the sub object we return.
521 *
522 * Alignment can't be bigger than page size.
523 *
524 * Hole are not considered for allocation to keep things simple.
525 * Assumption is that there won't be hole (all object on same
526 * alignment).
527 */
528struct radeon_sa_manager {
Christian Königbfb38d32012-07-11 21:07:57 +0200529 wait_queue_head_t wq;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500530 struct radeon_bo *bo;
Christian Königc3b7fe82012-05-09 15:34:56 +0200531 struct list_head *hole;
532 struct list_head flist[RADEON_NUM_RINGS];
533 struct list_head olist;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500534 unsigned size;
535 uint64_t gpu_addr;
536 void *cpu_ptr;
537 uint32_t domain;
Alex Deucher6c4f9782013-07-12 15:46:09 -0400538 uint32_t align;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500539};
540
541struct radeon_sa_bo;
542
543/* sub-allocation buffer */
544struct radeon_sa_bo {
Christian Königc3b7fe82012-05-09 15:34:56 +0200545 struct list_head olist;
546 struct list_head flist;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500547 struct radeon_sa_manager *manager;
Christian Könige6661a92012-05-09 15:34:52 +0200548 unsigned soffset;
549 unsigned eoffset;
Christian König557017a2012-05-09 15:34:54 +0200550 struct radeon_fence *fence;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500551};
552
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200553/*
554 * GEM objects.
555 */
556struct radeon_gem {
Jerome Glisse4c788672009-11-20 14:29:23 +0100557 struct mutex mutex;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200558 struct list_head objects;
559};
560
561int radeon_gem_init(struct radeon_device *rdev);
562void radeon_gem_fini(struct radeon_device *rdev);
Alex Deucher391bfec2014-07-17 12:26:29 -0400563int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
Jerome Glisse4c788672009-11-20 14:29:23 +0100564 int alignment, int initial_domain,
Christian Königed5cb432014-07-21 13:27:27 +0200565 u32 flags, bool kernel,
Jerome Glisse4c788672009-11-20 14:29:23 +0100566 struct drm_gem_object **obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200567
Dave Airlieff72145b2011-02-07 12:16:14 +1000568int radeon_mode_dumb_create(struct drm_file *file_priv,
569 struct drm_device *dev,
570 struct drm_mode_create_dumb *args);
571int radeon_mode_dumb_mmap(struct drm_file *filp,
572 struct drm_device *dev,
573 uint32_t handle, uint64_t *offset_p);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200574
575/*
Jerome Glissec1341e52011-12-21 12:13:47 -0500576 * Semaphores.
577 */
Jerome Glissec1341e52011-12-21 12:13:47 -0500578struct radeon_semaphore {
Jerome Glissea8c05942012-05-09 15:34:57 +0200579 struct radeon_sa_bo *sa_bo;
580 signed waiters;
Jerome Glissec1341e52011-12-21 12:13:47 -0500581 uint64_t gpu_addr;
Christian König1654b812013-11-12 12:58:05 +0100582 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
Jerome Glissec1341e52011-12-21 12:13:47 -0500583};
584
Jerome Glissec1341e52011-12-21 12:13:47 -0500585int radeon_semaphore_create(struct radeon_device *rdev,
586 struct radeon_semaphore **semaphore);
Christian König1654b812013-11-12 12:58:05 +0100587bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
Jerome Glissec1341e52011-12-21 12:13:47 -0500588 struct radeon_semaphore *semaphore);
Christian König1654b812013-11-12 12:58:05 +0100589bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
Jerome Glissec1341e52011-12-21 12:13:47 -0500590 struct radeon_semaphore *semaphore);
Christian König57d20a42014-09-04 20:01:53 +0200591void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore,
592 struct radeon_fence *fence);
Maarten Lankhorst392a2502014-09-25 12:39:38 +0200593int radeon_semaphore_sync_resv(struct radeon_device *rdev,
594 struct radeon_semaphore *semaphore,
595 struct reservation_object *resv,
596 bool shared);
Christian König8f676c42012-05-02 15:11:18 +0200597int radeon_semaphore_sync_rings(struct radeon_device *rdev,
598 struct radeon_semaphore *semaphore,
Christian König1654b812013-11-12 12:58:05 +0100599 int waiting_ring);
Jerome Glissec1341e52011-12-21 12:13:47 -0500600void radeon_semaphore_free(struct radeon_device *rdev,
Christian König220907d2012-05-10 16:46:43 +0200601 struct radeon_semaphore **semaphore,
Jerome Glissea8c05942012-05-09 15:34:57 +0200602 struct radeon_fence *fence);
Jerome Glissec1341e52011-12-21 12:13:47 -0500603
604/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200605 * GART structures, functions & helpers
606 */
607struct radeon_mc;
608
Matt Turnera77f1712009-10-14 00:34:41 -0400609#define RADEON_GPU_PAGE_SIZE 4096
Jerome Glissed594e462010-02-17 21:54:29 +0000610#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
Alex Deucher003cefe2011-09-16 12:04:08 -0400611#define RADEON_GPU_PAGE_SHIFT 12
Jerome Glisse721604a2012-01-05 22:11:05 -0500612#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
Matt Turnera77f1712009-10-14 00:34:41 -0400613
Michel Dänzer77497f22014-07-17 19:01:07 +0900614#define RADEON_GART_PAGE_DUMMY 0
615#define RADEON_GART_PAGE_VALID (1 << 0)
616#define RADEON_GART_PAGE_READ (1 << 1)
617#define RADEON_GART_PAGE_WRITE (1 << 2)
618#define RADEON_GART_PAGE_SNOOP (1 << 3)
619
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200620struct radeon_gart {
621 dma_addr_t table_addr;
Jerome Glissec9a1be92011-11-03 11:16:49 -0400622 struct radeon_bo *robj;
623 void *ptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200624 unsigned num_gpu_pages;
625 unsigned num_cpu_pages;
626 unsigned table_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200627 struct page **pages;
628 dma_addr_t *pages_addr;
629 bool ready;
630};
631
632int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
633void radeon_gart_table_ram_free(struct radeon_device *rdev);
634int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
635void radeon_gart_table_vram_free(struct radeon_device *rdev);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400636int radeon_gart_table_vram_pin(struct radeon_device *rdev);
637void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200638int radeon_gart_init(struct radeon_device *rdev);
639void radeon_gart_fini(struct radeon_device *rdev);
640void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
641 int pages);
642int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
Konrad Rzeszutek Wilkc39d3512010-12-02 11:04:29 -0500643 int pages, struct page **pagelist,
Michel Dänzer77497f22014-07-17 19:01:07 +0900644 dma_addr_t *dma_addr, uint32_t flags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200645
646
647/*
648 * GPU MC structures, functions & helpers
649 */
650struct radeon_mc {
651 resource_size_t aper_size;
652 resource_size_t aper_base;
653 resource_size_t agp_base;
Dave Airlie7a50f012009-07-21 20:39:30 +1000654 /* for some chips with <= 32MB we need to lie
655 * about vram size near mc fb location */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000656 u64 mc_vram_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000657 u64 visible_vram_size;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000658 u64 gtt_size;
659 u64 gtt_start;
660 u64 gtt_end;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000661 u64 vram_start;
662 u64 vram_end;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200663 unsigned vram_width;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000664 u64 real_vram_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200665 int vram_mtrr;
666 bool vram_is_ddr;
Jerome Glissed594e462010-02-17 21:54:29 +0000667 bool igp_sideport_enabled;
Alex Deucher8d369bb2010-07-15 10:51:10 -0400668 u64 gtt_base_align;
Alex Deucher9ed8b1f2013-04-08 11:13:01 -0400669 u64 mc_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200670};
671
Alex Deucher06b64762010-01-05 11:27:29 -0500672bool radeon_combios_sideport_present(struct radeon_device *rdev);
673bool radeon_atombios_sideport_present(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200674
675/*
676 * GPU scratch registers structures, functions & helpers
677 */
678struct radeon_scratch {
679 unsigned num_reg;
Alex Deucher724c80e2010-08-27 18:25:25 -0400680 uint32_t reg_base;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200681 bool free[32];
682 uint32_t reg[32];
683};
684
685int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
686void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
687
Alex Deucher75efdee2013-03-04 12:47:46 -0500688/*
689 * GPU doorbell structures, functions & helpers
690 */
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500691#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
692
Alex Deucher75efdee2013-03-04 12:47:46 -0500693struct radeon_doorbell {
Alex Deucher75efdee2013-03-04 12:47:46 -0500694 /* doorbell mmio */
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500695 resource_size_t base;
696 resource_size_t size;
697 u32 __iomem *ptr;
698 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
699 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
Alex Deucher75efdee2013-03-04 12:47:46 -0500700};
701
702int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
703void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200704
705/*
706 * IRQS.
707 */
Alex Deucher6f34be52010-11-21 10:59:01 -0500708
Christian Königfa7f5172014-06-03 18:13:21 -0400709struct radeon_flip_work {
710 struct work_struct flip_work;
711 struct work_struct unpin_work;
712 struct radeon_device *rdev;
713 int crtc_id;
Michel Dänzerc60381b2014-07-14 15:48:42 +0900714 uint64_t base;
Alex Deucher6f34be52010-11-21 10:59:01 -0500715 struct drm_pending_vblank_event *event;
Christian Königfa7f5172014-06-03 18:13:21 -0400716 struct radeon_bo *old_rbo;
Maarten Lankhorsta0e84762014-09-17 14:35:02 +0200717 struct fence *fence;
Alex Deucher6f34be52010-11-21 10:59:01 -0500718};
719
720struct r500_irq_stat_regs {
721 u32 disp_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400722 u32 hdmi0_status;
Alex Deucher6f34be52010-11-21 10:59:01 -0500723};
724
725struct r600_irq_stat_regs {
726 u32 disp_int;
727 u32 disp_int_cont;
728 u32 disp_int_cont2;
729 u32 d1grph_int;
730 u32 d2grph_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400731 u32 hdmi0_status;
732 u32 hdmi1_status;
Alex Deucher6f34be52010-11-21 10:59:01 -0500733};
734
735struct evergreen_irq_stat_regs {
736 u32 disp_int;
737 u32 disp_int_cont;
738 u32 disp_int_cont2;
739 u32 disp_int_cont3;
740 u32 disp_int_cont4;
741 u32 disp_int_cont5;
742 u32 d1grph_int;
743 u32 d2grph_int;
744 u32 d3grph_int;
745 u32 d4grph_int;
746 u32 d5grph_int;
747 u32 d6grph_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400748 u32 afmt_status1;
749 u32 afmt_status2;
750 u32 afmt_status3;
751 u32 afmt_status4;
752 u32 afmt_status5;
753 u32 afmt_status6;
Alex Deucher6f34be52010-11-21 10:59:01 -0500754};
755
Alex Deuchera59781b2012-11-09 10:45:57 -0500756struct cik_irq_stat_regs {
757 u32 disp_int;
758 u32 disp_int_cont;
759 u32 disp_int_cont2;
760 u32 disp_int_cont3;
761 u32 disp_int_cont4;
762 u32 disp_int_cont5;
763 u32 disp_int_cont6;
Christian Königf5d636d2014-04-23 20:46:06 +0200764 u32 d1grph_int;
765 u32 d2grph_int;
766 u32 d3grph_int;
767 u32 d4grph_int;
768 u32 d5grph_int;
769 u32 d6grph_int;
Alex Deuchera59781b2012-11-09 10:45:57 -0500770};
771
Alex Deucher6f34be52010-11-21 10:59:01 -0500772union radeon_irq_stat_regs {
773 struct r500_irq_stat_regs r500;
774 struct r600_irq_stat_regs r600;
775 struct evergreen_irq_stat_regs evergreen;
Alex Deuchera59781b2012-11-09 10:45:57 -0500776 struct cik_irq_stat_regs cik;
Alex Deucher6f34be52010-11-21 10:59:01 -0500777};
778
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200779struct radeon_irq {
Christian Koenigfb982572012-05-17 01:33:30 +0200780 bool installed;
781 spinlock_t lock;
Christian Koenig736fc372012-05-17 19:52:00 +0200782 atomic_t ring_int[RADEON_NUM_RINGS];
Christian Koenigfb982572012-05-17 01:33:30 +0200783 bool crtc_vblank_int[RADEON_MAX_CRTCS];
Christian Koenig736fc372012-05-17 19:52:00 +0200784 atomic_t pflip[RADEON_MAX_CRTCS];
Christian Koenigfb982572012-05-17 01:33:30 +0200785 wait_queue_head_t vblank_queue;
786 bool hpd[RADEON_MAX_HPD_PINS];
Christian Koenigfb982572012-05-17 01:33:30 +0200787 bool afmt[RADEON_MAX_AFMT_BLOCKS];
788 union radeon_irq_stat_regs stat_regs;
Alex Deucher4a6369e2013-04-12 14:04:10 -0400789 bool dpm_thermal;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200790};
791
792int radeon_irq_kms_init(struct radeon_device *rdev);
793void radeon_irq_kms_fini(struct radeon_device *rdev);
Alex Deucher1b370782011-11-17 20:13:28 -0500794void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
Maarten Lankhorst954605c2014-01-09 11:03:12 +0100795bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
Alex Deucher1b370782011-11-17 20:13:28 -0500796void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
Alex Deucher6f34be52010-11-21 10:59:01 -0500797void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
798void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
Christian Koenigfb982572012-05-17 01:33:30 +0200799void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
800void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
801void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
802void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200803
804/*
Christian Könige32eb502011-10-23 12:56:27 +0200805 * CP & rings.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200806 */
Alex Deucher74652802011-08-25 13:39:48 -0400807
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200808struct radeon_ib {
Jerome Glisse68470ae2012-05-09 15:35:00 +0200809 struct radeon_sa_bo *sa_bo;
810 uint32_t length_dw;
811 uint64_t gpu_addr;
812 uint32_t *ptr;
Christian König876dc9f2012-05-08 14:24:01 +0200813 int ring;
Jerome Glisse68470ae2012-05-09 15:35:00 +0200814 struct radeon_fence *fence;
Christian König4bf3dd92012-08-06 18:57:44 +0200815 struct radeon_vm *vm;
Jerome Glisse68470ae2012-05-09 15:35:00 +0200816 bool is_const_ib;
817 struct radeon_semaphore *semaphore;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200818};
819
Christian Könige32eb502011-10-23 12:56:27 +0200820struct radeon_ring {
Jerome Glisse4c788672009-11-20 14:29:23 +0100821 struct radeon_bo *ring_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200822 volatile uint32_t *ring;
Christian König5596a9d2011-10-13 12:48:45 +0200823 unsigned rptr_offs;
Christian König45df6802012-07-06 16:22:55 +0200824 unsigned rptr_save_reg;
Alex Deucher89d35802012-07-17 14:02:31 -0400825 u64 next_rptr_gpu_addr;
826 volatile u32 *next_rptr_cpu_addr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200827 unsigned wptr;
828 unsigned wptr_old;
829 unsigned ring_size;
830 unsigned ring_free_dw;
831 int count_dw;
Christian Königaee4aa72014-02-18 15:24:06 +0100832 atomic_t last_rptr;
833 atomic64_t last_activity;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200834 uint64_t gpu_addr;
835 uint32_t align_mask;
836 uint32_t ptr_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200837 bool ready;
Alex Deucher78c55602011-11-17 14:25:56 -0500838 u32 nop;
Alex Deucher8b25ed32012-07-17 14:02:30 -0400839 u32 idx;
Jerome Glisse5f0839c2013-01-11 15:19:43 -0500840 u64 last_semaphore_signal_addr;
841 u64 last_semaphore_wait_addr;
Alex Deucher963e81f2013-06-26 17:37:11 -0400842 /* for CIK queues */
843 u32 me;
844 u32 pipe;
845 u32 queue;
846 struct radeon_bo *mqd_obj;
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500847 u32 doorbell_index;
Alex Deucher963e81f2013-06-26 17:37:11 -0400848 unsigned wptr_offs;
849};
850
851struct radeon_mec {
852 struct radeon_bo *hpd_eop_obj;
853 u64 hpd_eop_gpu_addr;
854 u32 num_pipe;
855 u32 num_mec;
856 u32 num_queue;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200857};
858
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500859/*
Jerome Glisse721604a2012-01-05 22:11:05 -0500860 * VM
861 */
Christian Königee60e292012-08-09 16:21:08 +0200862
Dmitry Cherkasovfa87e622012-09-17 19:36:19 +0200863/* maximum number of VMIDs */
Christian Königee60e292012-08-09 16:21:08 +0200864#define RADEON_NUM_VM 16
865
Dmitry Cherkasovfa87e622012-09-17 19:36:19 +0200866/* number of entries in page table */
Christian König4510fb92014-06-05 23:56:50 -0400867#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
Dmitry Cherkasovfa87e622012-09-17 19:36:19 +0200868
Alex Deucher1c011032013-07-12 15:56:02 -0400869/* PTBs (Page Table Blocks) need to be aligned to 32K */
870#define RADEON_VM_PTB_ALIGN_SIZE 32768
871#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
872#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
873
Christian König24c16432013-10-30 11:51:09 -0400874#define R600_PTE_VALID (1 << 0)
875#define R600_PTE_SYSTEM (1 << 1)
876#define R600_PTE_SNOOPED (1 << 2)
877#define R600_PTE_READABLE (1 << 5)
878#define R600_PTE_WRITEABLE (1 << 6)
879
Christian Königec3dbbc2014-05-10 12:17:55 +0200880/* PTE (Page Table Entry) fragment field for different page sizes */
881#define R600_PTE_FRAG_4KB (0 << 7)
882#define R600_PTE_FRAG_64KB (4 << 7)
883#define R600_PTE_FRAG_256KB (6 << 7)
884
Christian König33fa9fe2014-07-22 17:42:20 +0200885/* flags needed to be set so we can copy directly from the GART table */
886#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
887 R600_PTE_SYSTEM | R600_PTE_VALID )
Christian König0e977032014-05-27 16:47:37 +0200888
Christian König6d2f2942014-02-20 13:42:17 +0100889struct radeon_vm_pt {
890 struct radeon_bo *bo;
891 uint64_t addr;
892};
893
Jerome Glisse721604a2012-01-05 22:11:05 -0500894struct radeon_vm {
Alex Deucher0aea5e42014-07-30 11:49:56 -0400895 struct rb_root va;
Christian Königee60e292012-08-09 16:21:08 +0200896 unsigned id;
Christian König90a51a32012-10-09 13:31:17 +0200897
Christian Könige31ad962014-07-18 09:24:53 +0200898 /* BOs moved, but not yet updated in the PT */
899 struct list_head invalidated;
900
Christian König036bf462014-07-18 08:56:40 +0200901 /* BOs freed, but not yet updated in the PT */
902 struct list_head freed;
903
Christian König90a51a32012-10-09 13:31:17 +0200904 /* contains the page directory */
Christian König6d2f2942014-02-20 13:42:17 +0100905 struct radeon_bo *page_directory;
Christian König90a51a32012-10-09 13:31:17 +0200906 uint64_t pd_gpu_addr;
Christian König6d2f2942014-02-20 13:42:17 +0100907 unsigned max_pde_used;
Christian König90a51a32012-10-09 13:31:17 +0200908
909 /* array of page tables, one for each page directory entry */
Christian König6d2f2942014-02-20 13:42:17 +0100910 struct radeon_vm_pt *page_tables;
Christian König90a51a32012-10-09 13:31:17 +0200911
Christian Königcc9e67e2014-07-18 13:48:10 +0200912 struct radeon_bo_va *ib_bo_va;
913
Jerome Glisse721604a2012-01-05 22:11:05 -0500914 struct mutex mutex;
915 /* last fence for cs using this vm */
916 struct radeon_fence *fence;
Christian König9b40e5d2012-08-08 12:22:43 +0200917 /* last flush or NULL if we still need to flush */
918 struct radeon_fence *last_flush;
Christian König593b2632014-01-23 14:24:15 +0100919 /* last use of vmid */
920 struct radeon_fence *last_id_use;
Jerome Glisse721604a2012-01-05 22:11:05 -0500921};
922
Jerome Glisse721604a2012-01-05 22:11:05 -0500923struct radeon_vm_manager {
Christian Königee60e292012-08-09 16:21:08 +0200924 struct radeon_fence *active[RADEON_NUM_VM];
Jerome Glisse721604a2012-01-05 22:11:05 -0500925 uint32_t max_pfn;
Jerome Glisse721604a2012-01-05 22:11:05 -0500926 /* number of VMIDs */
927 unsigned nvm;
928 /* vram base address for page table entry */
929 u64 vram_base_offset;
Alex Deucher67e915e2012-01-06 09:38:15 -0500930 /* is vm enabled? */
931 bool enabled;
Christian König054e01d2014-08-26 14:45:54 +0200932 /* for hw to save the PD addr on suspend/resume */
933 uint32_t saved_table_addr[RADEON_NUM_VM];
Jerome Glisse721604a2012-01-05 22:11:05 -0500934};
935
936/*
937 * file private structure
938 */
939struct radeon_fpriv {
940 struct radeon_vm vm;
941};
942
943/*
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500944 * R6xx+ IH ring
945 */
946struct r600_ih {
Jerome Glisse4c788672009-11-20 14:29:23 +0100947 struct radeon_bo *ring_obj;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500948 volatile uint32_t *ring;
949 unsigned rptr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500950 unsigned ring_size;
951 uint64_t gpu_addr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500952 uint32_t ptr_mask;
Christian Koenigc20dc362012-05-16 21:45:24 +0200953 atomic_t lock;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500954 bool enabled;
955};
956
Alex Deucher347e7592012-03-20 17:18:21 -0400957/*
Alex Deucher2948f5e2013-04-12 13:52:52 -0400958 * RLC stuff
Alex Deucher347e7592012-03-20 17:18:21 -0400959 */
Alex Deucher2948f5e2013-04-12 13:52:52 -0400960#include "clearstate_defs.h"
961
962struct radeon_rlc {
Alex Deucher347e7592012-03-20 17:18:21 -0400963 /* for power gating */
964 struct radeon_bo *save_restore_obj;
965 uint64_t save_restore_gpu_addr;
Alex Deucher2948f5e2013-04-12 13:52:52 -0400966 volatile uint32_t *sr_ptr;
Alex Deucher1fd11772013-04-17 17:53:50 -0400967 const u32 *reg_list;
Alex Deucher2948f5e2013-04-12 13:52:52 -0400968 u32 reg_list_size;
Alex Deucher347e7592012-03-20 17:18:21 -0400969 /* for clear state */
970 struct radeon_bo *clear_state_obj;
971 uint64_t clear_state_gpu_addr;
Alex Deucher2948f5e2013-04-12 13:52:52 -0400972 volatile uint32_t *cs_ptr;
Alex Deucher1fd11772013-04-17 17:53:50 -0400973 const struct cs_section_def *cs_data;
Alex Deucher22c775c2013-07-23 09:41:05 -0400974 u32 clear_state_size;
975 /* for cp tables */
976 struct radeon_bo *cp_table_obj;
977 uint64_t cp_table_gpu_addr;
978 volatile uint32_t *cp_table_ptr;
979 u32 cp_table_size;
Alex Deucher347e7592012-03-20 17:18:21 -0400980};
981
Jerome Glisse69e130a2011-12-21 12:13:46 -0500982int radeon_ib_get(struct radeon_device *rdev, int ring,
Christian König4bf3dd92012-08-06 18:57:44 +0200983 struct radeon_ib *ib, struct radeon_vm *vm,
984 unsigned size);
Jerome Glissef2e39222012-05-09 15:35:02 +0200985void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
Christian König4ef72562012-07-13 13:06:00 +0200986int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
Michel Dänzer1538a9e2014-08-18 17:34:55 +0900987 struct radeon_ib *const_ib, bool hdp_flush);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200988int radeon_ib_pool_init(struct radeon_device *rdev);
989void radeon_ib_pool_fini(struct radeon_device *rdev);
Christian König7bd560e2012-05-02 15:11:12 +0200990int radeon_ib_ring_tests(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200991/* Ring access between begin & end cannot sleep */
Alex Deucher89d35802012-07-17 14:02:31 -0400992bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
993 struct radeon_ring *ring);
Christian Könige32eb502011-10-23 12:56:27 +0200994void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
995int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
996int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
Michel Dänzer1538a9e2014-08-18 17:34:55 +0900997void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
998 bool hdp_flush);
999void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1000 bool hdp_flush);
Christian Königd6999bc2012-05-09 15:34:45 +02001001void radeon_ring_undo(struct radeon_ring *ring);
Christian Könige32eb502011-10-23 12:56:27 +02001002void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1003int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Christian Königff212f22014-02-18 14:52:33 +01001004void radeon_ring_lockup_update(struct radeon_device *rdev,
1005 struct radeon_ring *ring);
Christian König069211e2012-05-02 15:11:20 +02001006bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König55d7c222012-07-09 11:52:44 +02001007unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1008 uint32_t **data);
1009int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1010 unsigned size, uint32_t *data);
Christian Könige32eb502011-10-23 12:56:27 +02001011int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
Alex Deucherea31bf62013-12-09 19:44:30 -05001012 unsigned rptr_offs, u32 nop);
Christian Könige32eb502011-10-23 12:56:27 +02001013void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001014
1015
Alex Deucher4d756582012-09-27 15:08:35 -04001016/* r600 async dma */
1017void r600_dma_stop(struct radeon_device *rdev);
1018int r600_dma_resume(struct radeon_device *rdev);
1019void r600_dma_fini(struct radeon_device *rdev);
1020
Alex Deucher8c5fd7e2012-12-04 15:28:18 -05001021void cayman_dma_stop(struct radeon_device *rdev);
1022int cayman_dma_resume(struct radeon_device *rdev);
1023void cayman_dma_fini(struct radeon_device *rdev);
1024
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001025/*
1026 * CS.
1027 */
1028struct radeon_cs_reloc {
1029 struct drm_gem_object *gobj;
Jerome Glisse4c788672009-11-20 14:29:23 +01001030 struct radeon_bo *robj;
Christian Königdf0af442014-03-03 12:38:08 +01001031 struct ttm_validate_buffer tv;
1032 uint64_t gpu_offset;
Christian Königce6758c2014-06-02 17:33:07 +02001033 unsigned prefered_domains;
1034 unsigned allowed_domains;
Christian Königdf0af442014-03-03 12:38:08 +01001035 uint32_t tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001036 uint32_t handle;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001037};
1038
1039struct radeon_cs_chunk {
1040 uint32_t chunk_id;
1041 uint32_t length_dw;
1042 uint32_t *kdata;
Jerome Glisse721604a2012-01-05 22:11:05 -05001043 void __user *user_ptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001044};
1045
1046struct radeon_cs_parser {
Jerome Glissec8c15ff2010-01-18 13:01:36 +01001047 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001048 struct radeon_device *rdev;
1049 struct drm_file *filp;
1050 /* chunks */
1051 unsigned nchunks;
1052 struct radeon_cs_chunk *chunks;
1053 uint64_t *chunks_array;
1054 /* IB */
1055 unsigned idx;
1056 /* relocations */
1057 unsigned nrelocs;
1058 struct radeon_cs_reloc *relocs;
1059 struct radeon_cs_reloc **relocs_ptr;
Christian Königdf0af442014-03-03 12:38:08 +01001060 struct radeon_cs_reloc *vm_bos;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001061 struct list_head validated;
Alex Deuchercf4ccd02011-11-18 10:19:47 -05001062 unsigned dma_reloc_idx;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001063 /* indices of various chunks */
1064 int chunk_ib_idx;
1065 int chunk_relocs_idx;
Jerome Glisse721604a2012-01-05 22:11:05 -05001066 int chunk_flags_idx;
Alex Deucherdfcf5f32012-03-20 17:18:14 -04001067 int chunk_const_ib_idx;
Jerome Glissef2e39222012-05-09 15:35:02 +02001068 struct radeon_ib ib;
1069 struct radeon_ib const_ib;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001070 void *track;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001071 unsigned family;
Marek Olšáke70f2242011-10-25 01:38:45 +02001072 int parser_error;
Jerome Glisse721604a2012-01-05 22:11:05 -05001073 u32 cs_flags;
1074 u32 ring;
1075 s32 priority;
Maarten Lankhorstecff6652013-06-27 13:48:17 +02001076 struct ww_acquire_ctx ticket;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001077};
1078
Maarten Lankhorst28a326c2013-10-09 14:36:57 +02001079static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1080{
1081 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1082
1083 if (ibc->kdata)
1084 return ibc->kdata[idx];
1085 return p->ib.ptr[idx];
1086}
1087
Dave Airlie513bcb42009-09-23 16:56:27 +10001088
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001089struct radeon_cs_packet {
1090 unsigned idx;
1091 unsigned type;
1092 unsigned reg;
1093 unsigned opcode;
1094 int count;
1095 unsigned one_reg_wr;
1096};
1097
1098typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1099 struct radeon_cs_packet *pkt,
1100 unsigned idx, unsigned reg);
1101typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1102 struct radeon_cs_packet *pkt);
1103
1104
1105/*
1106 * AGP
1107 */
1108int radeon_agp_init(struct radeon_device *rdev);
Dave Airlie0ebf1712009-11-05 15:39:10 +10001109void radeon_agp_resume(struct radeon_device *rdev);
Jerome Glisse10b06122010-05-21 18:48:54 +02001110void radeon_agp_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001111void radeon_agp_fini(struct radeon_device *rdev);
1112
1113
1114/*
1115 * Writeback
1116 */
1117struct radeon_wb {
Jerome Glisse4c788672009-11-20 14:29:23 +01001118 struct radeon_bo *wb_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001119 volatile uint32_t *wb;
1120 uint64_t gpu_addr;
Alex Deucher724c80e2010-08-27 18:25:25 -04001121 bool enabled;
Alex Deucherd0f8a852010-09-04 05:04:34 -04001122 bool use_event;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001123};
1124
Alex Deucher724c80e2010-08-27 18:25:25 -04001125#define RADEON_WB_SCRATCH_OFFSET 0
Alex Deucher89d35802012-07-17 14:02:31 -04001126#define RADEON_WB_RING0_NEXT_RPTR 256
Alex Deucher724c80e2010-08-27 18:25:25 -04001127#define RADEON_WB_CP_RPTR_OFFSET 1024
Alex Deucher0c88a022011-03-02 20:07:31 -05001128#define RADEON_WB_CP1_RPTR_OFFSET 1280
1129#define RADEON_WB_CP2_RPTR_OFFSET 1536
Alex Deucher4d756582012-09-27 15:08:35 -04001130#define R600_WB_DMA_RPTR_OFFSET 1792
Alex Deucher724c80e2010-08-27 18:25:25 -04001131#define R600_WB_IH_WPTR_OFFSET 2048
Alex Deucherf60cbd12012-12-04 15:27:33 -05001132#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
Alex Deucherd0f8a852010-09-04 05:04:34 -04001133#define R600_WB_EVENT_OFFSET 3072
Alex Deucher963e81f2013-06-26 17:37:11 -04001134#define CIK_WB_CP1_WPTR_OFFSET 3328
1135#define CIK_WB_CP2_WPTR_OFFSET 3584
Alex Deucheradfed2b02014-10-13 13:20:02 -04001136#define R600_WB_DMA_RING_TEST_OFFSET 3588
1137#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
Alex Deucher724c80e2010-08-27 18:25:25 -04001138
Jerome Glissec93bb852009-07-13 21:04:08 +02001139/**
1140 * struct radeon_pm - power management datas
1141 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1142 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1143 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1144 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1145 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1146 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1147 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1148 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1149 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001150 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
Jerome Glissec93bb852009-07-13 21:04:08 +02001151 * @needed_bandwidth: current bandwidth needs
1152 *
1153 * It keeps track of various data needed to take powermanagement decision.
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001154 * Bandwidth need is used to determine minimun clock of the GPU and memory.
Jerome Glissec93bb852009-07-13 21:04:08 +02001155 * Equation between gpu/memory clock and available bandwidth is hw dependent
1156 * (type of memory, bus size, efficiency, ...)
1157 */
Alex Deucherce8f5372010-05-07 15:10:16 -04001158
1159enum radeon_pm_method {
1160 PM_METHOD_PROFILE,
1161 PM_METHOD_DYNPM,
Alex Deucherda321c82013-04-12 13:55:22 -04001162 PM_METHOD_DPM,
Rafał Miłeckic913e232009-12-22 23:02:16 +01001163};
Alex Deucherce8f5372010-05-07 15:10:16 -04001164
1165enum radeon_dynpm_state {
1166 DYNPM_STATE_DISABLED,
1167 DYNPM_STATE_MINIMUM,
1168 DYNPM_STATE_PAUSED,
Rafael J. Wysocki3f53eb62010-06-17 23:02:27 +00001169 DYNPM_STATE_ACTIVE,
1170 DYNPM_STATE_SUSPENDED,
Alex Deucherce8f5372010-05-07 15:10:16 -04001171};
1172enum radeon_dynpm_action {
1173 DYNPM_ACTION_NONE,
1174 DYNPM_ACTION_MINIMUM,
1175 DYNPM_ACTION_DOWNCLOCK,
1176 DYNPM_ACTION_UPCLOCK,
1177 DYNPM_ACTION_DEFAULT
Rafał Miłeckic913e232009-12-22 23:02:16 +01001178};
Alex Deucher56278a82009-12-28 13:58:44 -05001179
1180enum radeon_voltage_type {
1181 VOLTAGE_NONE = 0,
1182 VOLTAGE_GPIO,
1183 VOLTAGE_VDDC,
1184 VOLTAGE_SW
1185};
1186
Alex Deucher0ec0e742009-12-23 13:21:58 -05001187enum radeon_pm_state_type {
Alex Deucherda321c82013-04-12 13:55:22 -04001188 /* not used for dpm */
Alex Deucher0ec0e742009-12-23 13:21:58 -05001189 POWER_STATE_TYPE_DEFAULT,
1190 POWER_STATE_TYPE_POWERSAVE,
Alex Deucherda321c82013-04-12 13:55:22 -04001191 /* user selectable states */
Alex Deucher0ec0e742009-12-23 13:21:58 -05001192 POWER_STATE_TYPE_BATTERY,
1193 POWER_STATE_TYPE_BALANCED,
1194 POWER_STATE_TYPE_PERFORMANCE,
Alex Deucherda321c82013-04-12 13:55:22 -04001195 /* internal states */
1196 POWER_STATE_TYPE_INTERNAL_UVD,
1197 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1198 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1199 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1200 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1201 POWER_STATE_TYPE_INTERNAL_BOOT,
1202 POWER_STATE_TYPE_INTERNAL_THERMAL,
1203 POWER_STATE_TYPE_INTERNAL_ACPI,
1204 POWER_STATE_TYPE_INTERNAL_ULV,
Alex Deucheredcaa5b2013-07-05 11:48:31 -04001205 POWER_STATE_TYPE_INTERNAL_3DPERF,
Alex Deucher0ec0e742009-12-23 13:21:58 -05001206};
1207
Alex Deucherce8f5372010-05-07 15:10:16 -04001208enum radeon_pm_profile_type {
1209 PM_PROFILE_DEFAULT,
1210 PM_PROFILE_AUTO,
1211 PM_PROFILE_LOW,
Alex Deucherc9e75b22010-06-02 17:56:01 -04001212 PM_PROFILE_MID,
Alex Deucherce8f5372010-05-07 15:10:16 -04001213 PM_PROFILE_HIGH,
1214};
1215
1216#define PM_PROFILE_DEFAULT_IDX 0
1217#define PM_PROFILE_LOW_SH_IDX 1
Alex Deucherc9e75b22010-06-02 17:56:01 -04001218#define PM_PROFILE_MID_SH_IDX 2
1219#define PM_PROFILE_HIGH_SH_IDX 3
1220#define PM_PROFILE_LOW_MH_IDX 4
1221#define PM_PROFILE_MID_MH_IDX 5
1222#define PM_PROFILE_HIGH_MH_IDX 6
1223#define PM_PROFILE_MAX 7
Alex Deucherce8f5372010-05-07 15:10:16 -04001224
1225struct radeon_pm_profile {
1226 int dpms_off_ps_idx;
1227 int dpms_on_ps_idx;
1228 int dpms_off_cm_idx;
1229 int dpms_on_cm_idx;
Alex Deucher516d0e42009-12-23 14:28:05 -05001230};
1231
Alex Deucher21a81222010-07-02 12:58:16 -04001232enum radeon_int_thermal_type {
1233 THERMAL_TYPE_NONE,
Alex Deucherda321c82013-04-12 13:55:22 -04001234 THERMAL_TYPE_EXTERNAL,
1235 THERMAL_TYPE_EXTERNAL_GPIO,
Alex Deucher21a81222010-07-02 12:58:16 -04001236 THERMAL_TYPE_RV6XX,
1237 THERMAL_TYPE_RV770,
Alex Deucherda321c82013-04-12 13:55:22 -04001238 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
Alex Deucher21a81222010-07-02 12:58:16 -04001239 THERMAL_TYPE_EVERGREEN,
Alex Deuchere33df252010-11-22 17:56:32 -05001240 THERMAL_TYPE_SUMO,
Alex Deucher4fddba12011-01-06 21:19:22 -05001241 THERMAL_TYPE_NI,
Alex Deucher14607d02012-03-20 17:18:09 -04001242 THERMAL_TYPE_SI,
Alex Deucherda321c82013-04-12 13:55:22 -04001243 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
Alex Deucher51150202012-12-18 22:07:14 -05001244 THERMAL_TYPE_CI,
Alex Deucher16fbe002013-04-22 21:41:26 -04001245 THERMAL_TYPE_KV,
Alex Deucher21a81222010-07-02 12:58:16 -04001246};
1247
Alex Deucher56278a82009-12-28 13:58:44 -05001248struct radeon_voltage {
1249 enum radeon_voltage_type type;
1250 /* gpio voltage */
1251 struct radeon_gpio_rec gpio;
1252 u32 delay; /* delay in usec from voltage drop to sclk change */
1253 bool active_high; /* voltage drop is active when bit is high */
1254 /* VDDC voltage */
1255 u8 vddc_id; /* index into vddc voltage table */
1256 u8 vddci_id; /* index into vddci voltage table */
1257 bool vddci_enabled;
1258 /* r6xx+ sw */
Alex Deucher2feea492011-04-12 14:49:24 -04001259 u16 voltage;
1260 /* evergreen+ vddci */
1261 u16 vddci;
Alex Deucher56278a82009-12-28 13:58:44 -05001262};
1263
Alex Deucherd7311172010-05-03 01:13:14 -04001264/* clock mode flags */
1265#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1266
Alex Deucher56278a82009-12-28 13:58:44 -05001267struct radeon_pm_clock_info {
1268 /* memory clock */
1269 u32 mclk;
1270 /* engine clock */
1271 u32 sclk;
1272 /* voltage info */
1273 struct radeon_voltage voltage;
Alex Deucherd7311172010-05-03 01:13:14 -04001274 /* standardized clock flags */
Alex Deucher56278a82009-12-28 13:58:44 -05001275 u32 flags;
1276};
1277
Alex Deuchera48b9b42010-04-22 14:03:55 -04001278/* state flags */
Alex Deucherd7311172010-05-03 01:13:14 -04001279#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
Alex Deuchera48b9b42010-04-22 14:03:55 -04001280
Alex Deucher56278a82009-12-28 13:58:44 -05001281struct radeon_power_state {
Alex Deucher0ec0e742009-12-23 13:21:58 -05001282 enum radeon_pm_state_type type;
Alex Deucher8f3f1c92011-11-04 10:09:43 -04001283 struct radeon_pm_clock_info *clock_info;
Alex Deucher56278a82009-12-28 13:58:44 -05001284 /* number of valid clock modes in this power state */
1285 int num_clock_modes;
Alex Deucher56278a82009-12-28 13:58:44 -05001286 struct radeon_pm_clock_info *default_clock_mode;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001287 /* standardized state flags */
1288 u32 flags;
Alex Deucher79daedc2010-04-22 14:25:19 -04001289 u32 misc; /* vbios specific flags */
1290 u32 misc2; /* vbios specific flags */
1291 int pcie_lanes; /* pcie lanes */
Alex Deucher56278a82009-12-28 13:58:44 -05001292};
1293
Rafał Miłecki27459322010-02-11 22:16:36 +00001294/*
1295 * Some modes are overclocked by very low value, accept them
1296 */
1297#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1298
Alex Deucher2e9d4c02013-04-12 13:58:03 -04001299enum radeon_dpm_auto_throttle_src {
1300 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1301 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1302};
1303
1304enum radeon_dpm_event_src {
1305 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1306 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1307 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1308 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1309 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1310};
1311
Alex Deucher58bd2a82013-09-04 16:13:56 -04001312#define RADEON_MAX_VCE_LEVELS 6
1313
Alex Deucherb62d6282013-08-20 20:29:05 -04001314enum radeon_vce_level {
1315 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1316 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1317 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1318 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1319 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1320 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1321};
1322
Alex Deucherda321c82013-04-12 13:55:22 -04001323struct radeon_ps {
1324 u32 caps; /* vbios flags */
1325 u32 class; /* vbios flags */
1326 u32 class2; /* vbios flags */
1327 /* UVD clocks */
1328 u32 vclk;
1329 u32 dclk;
Alex Deucherc4453e62013-05-15 15:53:57 -04001330 /* VCE clocks */
1331 u32 evclk;
1332 u32 ecclk;
Alex Deucherb62d6282013-08-20 20:29:05 -04001333 bool vce_active;
1334 enum radeon_vce_level vce_level;
Alex Deucherda321c82013-04-12 13:55:22 -04001335 /* asic priv */
1336 void *ps_priv;
1337};
1338
1339struct radeon_dpm_thermal {
1340 /* thermal interrupt work */
1341 struct work_struct work;
1342 /* low temperature threshold */
1343 int min_temp;
1344 /* high temperature threshold */
1345 int max_temp;
1346 /* was interrupt low to high or high to low */
1347 bool high_to_low;
1348};
1349
Alex Deucherd22b7e42012-11-29 19:27:56 -05001350enum radeon_clk_action
1351{
1352 RADEON_SCLK_UP = 1,
1353 RADEON_SCLK_DOWN
1354};
1355
1356struct radeon_blacklist_clocks
1357{
1358 u32 sclk;
1359 u32 mclk;
1360 enum radeon_clk_action action;
1361};
1362
Alex Deucher61b7d602012-11-14 19:57:42 -05001363struct radeon_clock_and_voltage_limits {
1364 u32 sclk;
1365 u32 mclk;
Alex Deuchercdf6e802013-10-23 16:13:42 -04001366 u16 vddc;
1367 u16 vddci;
Alex Deucher61b7d602012-11-14 19:57:42 -05001368};
1369
1370struct radeon_clock_array {
1371 u32 count;
1372 u32 *values;
1373};
1374
1375struct radeon_clock_voltage_dependency_entry {
1376 u32 clk;
1377 u16 v;
1378};
1379
1380struct radeon_clock_voltage_dependency_table {
1381 u32 count;
1382 struct radeon_clock_voltage_dependency_entry *entries;
1383};
1384
Alex Deucheref976ec2013-05-06 11:31:04 -04001385union radeon_cac_leakage_entry {
1386 struct {
1387 u16 vddc;
1388 u32 leakage;
1389 };
1390 struct {
1391 u16 vddc1;
1392 u16 vddc2;
1393 u16 vddc3;
1394 };
Alex Deucher61b7d602012-11-14 19:57:42 -05001395};
1396
1397struct radeon_cac_leakage_table {
1398 u32 count;
Alex Deucheref976ec2013-05-06 11:31:04 -04001399 union radeon_cac_leakage_entry *entries;
Alex Deucher61b7d602012-11-14 19:57:42 -05001400};
1401
Alex Deucher929ee7a2013-03-20 12:30:25 -04001402struct radeon_phase_shedding_limits_entry {
1403 u16 voltage;
1404 u32 sclk;
1405 u32 mclk;
1406};
1407
1408struct radeon_phase_shedding_limits_table {
1409 u32 count;
1410 struct radeon_phase_shedding_limits_entry *entries;
1411};
1412
Alex Deucher84a9d9e2013-04-19 19:11:37 -04001413struct radeon_uvd_clock_voltage_dependency_entry {
1414 u32 vclk;
1415 u32 dclk;
1416 u16 v;
1417};
1418
1419struct radeon_uvd_clock_voltage_dependency_table {
1420 u8 count;
1421 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1422};
1423
Alex Deucherd29f0132013-05-09 16:37:28 -04001424struct radeon_vce_clock_voltage_dependency_entry {
1425 u32 ecclk;
1426 u32 evclk;
1427 u16 v;
1428};
1429
1430struct radeon_vce_clock_voltage_dependency_table {
1431 u8 count;
1432 struct radeon_vce_clock_voltage_dependency_entry *entries;
1433};
1434
Alex Deuchera5cb3182013-03-20 13:00:18 -04001435struct radeon_ppm_table {
1436 u8 ppm_design;
1437 u16 cpu_core_number;
1438 u32 platform_tdp;
1439 u32 small_ac_platform_tdp;
1440 u32 platform_tdc;
1441 u32 small_ac_platform_tdc;
1442 u32 apu_tdp;
1443 u32 dgpu_tdp;
1444 u32 dgpu_ulv_power;
1445 u32 tj_max;
1446};
1447
Alex Deucher58cb7632013-05-06 12:15:33 -04001448struct radeon_cac_tdp_table {
1449 u16 tdp;
1450 u16 configurable_tdp;
1451 u16 tdc;
1452 u16 battery_power_limit;
1453 u16 small_power_limit;
1454 u16 low_cac_leakage;
1455 u16 high_cac_leakage;
1456 u16 maximum_power_delivery_limit;
1457};
1458
Alex Deucher61b7d602012-11-14 19:57:42 -05001459struct radeon_dpm_dynamic_state {
1460 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1461 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1462 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
Alex Deucherdd621a22013-05-06 14:37:56 -04001463 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
Alex Deucher4489cd622013-03-22 15:59:10 -04001464 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
Alex Deucher84a9d9e2013-04-19 19:11:37 -04001465 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
Alex Deucherd29f0132013-05-09 16:37:28 -04001466 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
Alex Deucher94a914f2013-05-09 16:42:33 -04001467 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1468 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
Alex Deucher61b7d602012-11-14 19:57:42 -05001469 struct radeon_clock_array valid_sclk_values;
1470 struct radeon_clock_array valid_mclk_values;
1471 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1472 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1473 u32 mclk_sclk_ratio;
1474 u32 sclk_mclk_delta;
1475 u16 vddc_vddci_delta;
1476 u16 min_vddc_for_pcie_gen2;
1477 struct radeon_cac_leakage_table cac_leakage_table;
Alex Deucher929ee7a2013-03-20 12:30:25 -04001478 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
Alex Deuchera5cb3182013-03-20 13:00:18 -04001479 struct radeon_ppm_table *ppm_table;
Alex Deucher58cb7632013-05-06 12:15:33 -04001480 struct radeon_cac_tdp_table *cac_tdp_table;
Alex Deucher61b7d602012-11-14 19:57:42 -05001481};
1482
1483struct radeon_dpm_fan {
1484 u16 t_min;
1485 u16 t_med;
1486 u16 t_high;
1487 u16 pwm_min;
1488 u16 pwm_med;
1489 u16 pwm_high;
1490 u8 t_hyst;
1491 u32 cycle_delay;
1492 u16 t_max;
1493 bool ucode_fan_control;
1494};
1495
Alex Deucher32ce4652013-03-18 17:03:01 -04001496enum radeon_pcie_gen {
1497 RADEON_PCIE_GEN1 = 0,
1498 RADEON_PCIE_GEN2 = 1,
1499 RADEON_PCIE_GEN3 = 2,
1500 RADEON_PCIE_GEN_INVALID = 0xffff
1501};
1502
Alex Deucher70d01a52013-07-02 18:38:02 -04001503enum radeon_dpm_forced_level {
1504 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1505 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1506 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1507};
1508
Alex Deucher58bd2a82013-09-04 16:13:56 -04001509struct radeon_vce_state {
1510 /* vce clocks */
1511 u32 evclk;
1512 u32 ecclk;
1513 /* gpu clocks */
1514 u32 sclk;
1515 u32 mclk;
1516 u8 clk_idx;
1517 u8 pstate;
1518};
1519
Alex Deucherda321c82013-04-12 13:55:22 -04001520struct radeon_dpm {
1521 struct radeon_ps *ps;
1522 /* number of valid power states */
1523 int num_ps;
1524 /* current power state that is active */
1525 struct radeon_ps *current_ps;
1526 /* requested power state */
1527 struct radeon_ps *requested_ps;
1528 /* boot up power state */
1529 struct radeon_ps *boot_ps;
1530 /* default uvd power state */
1531 struct radeon_ps *uvd_ps;
Alex Deucher58bd2a82013-09-04 16:13:56 -04001532 /* vce requirements */
1533 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1534 enum radeon_vce_level vce_level;
Alex Deucherda321c82013-04-12 13:55:22 -04001535 enum radeon_pm_state_type state;
1536 enum radeon_pm_state_type user_state;
1537 u32 platform_caps;
1538 u32 voltage_response_time;
1539 u32 backbias_response_time;
1540 void *priv;
1541 u32 new_active_crtcs;
1542 int new_active_crtc_count;
1543 u32 current_active_crtcs;
1544 int current_active_crtc_count;
Alex Deucher61b7d602012-11-14 19:57:42 -05001545 struct radeon_dpm_dynamic_state dyn_state;
1546 struct radeon_dpm_fan fan;
1547 u32 tdp_limit;
1548 u32 near_tdp_limit;
Alex Deuchera9e61412013-06-25 17:56:16 -04001549 u32 near_tdp_limit_adjusted;
Alex Deucher61b7d602012-11-14 19:57:42 -05001550 u32 sq_ramping_threshold;
1551 u32 cac_leakage;
1552 u16 tdp_od_limit;
1553 u32 tdp_adjustment;
1554 u16 load_line_slope;
1555 bool power_control;
Alex Deucher5ca302f2012-11-30 10:56:57 -05001556 bool ac_power;
Alex Deucherda321c82013-04-12 13:55:22 -04001557 /* special states active */
1558 bool thermal_active;
Alex Deucher8a227552013-06-21 15:12:57 -04001559 bool uvd_active;
Alex Deucherb62d6282013-08-20 20:29:05 -04001560 bool vce_active;
Alex Deucherda321c82013-04-12 13:55:22 -04001561 /* thermal handling */
1562 struct radeon_dpm_thermal thermal;
Alex Deucher70d01a52013-07-02 18:38:02 -04001563 /* forced levels */
1564 enum radeon_dpm_forced_level forced_level;
Alex Deucherce3537d2013-07-24 12:12:49 -04001565 /* track UVD streams */
1566 unsigned sd;
1567 unsigned hd;
Alex Deucherda321c82013-04-12 13:55:22 -04001568};
1569
Alex Deucherce3537d2013-07-24 12:12:49 -04001570void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
Alex Deucher03afe6f2013-08-23 11:56:26 -04001571void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
Alex Deucherda321c82013-04-12 13:55:22 -04001572
Jerome Glissec93bb852009-07-13 21:04:08 +02001573struct radeon_pm {
Rafał Miłeckic913e232009-12-22 23:02:16 +01001574 struct mutex mutex;
Christian Königdb7fce32012-05-11 14:57:18 +02001575 /* write locked while reprogramming mclk */
1576 struct rw_semaphore mclk_lock;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001577 u32 active_crtcs;
1578 int active_crtc_count;
Rafał Miłeckic913e232009-12-22 23:02:16 +01001579 int req_vblank;
Rafał Miłecki839461d2010-03-02 22:06:51 +01001580 bool vblank_sync;
Jerome Glissec93bb852009-07-13 21:04:08 +02001581 fixed20_12 max_bandwidth;
1582 fixed20_12 igp_sideport_mclk;
1583 fixed20_12 igp_system_mclk;
1584 fixed20_12 igp_ht_link_clk;
1585 fixed20_12 igp_ht_link_width;
1586 fixed20_12 k8_bandwidth;
1587 fixed20_12 sideport_bandwidth;
1588 fixed20_12 ht_bandwidth;
1589 fixed20_12 core_bandwidth;
1590 fixed20_12 sclk;
Alex Deucherf47299c2010-03-16 20:54:38 -04001591 fixed20_12 mclk;
Jerome Glissec93bb852009-07-13 21:04:08 +02001592 fixed20_12 needed_bandwidth;
Alex Deucher0975b162011-02-02 18:42:03 -05001593 struct radeon_power_state *power_state;
Alex Deucher56278a82009-12-28 13:58:44 -05001594 /* number of valid power states */
1595 int num_power_states;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001596 int current_power_state_index;
1597 int current_clock_mode_index;
1598 int requested_power_state_index;
1599 int requested_clock_mode_index;
1600 int default_power_state_index;
1601 u32 current_sclk;
1602 u32 current_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -04001603 u16 current_vddc;
1604 u16 current_vddci;
Alex Deucher9ace9f72011-01-06 21:19:26 -05001605 u32 default_sclk;
1606 u32 default_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -04001607 u16 default_vddc;
1608 u16 default_vddci;
Alex Deucher29fb52c2010-03-11 10:01:17 -05001609 struct radeon_i2c_chan *i2c_bus;
Alex Deucherce8f5372010-05-07 15:10:16 -04001610 /* selected pm method */
1611 enum radeon_pm_method pm_method;
1612 /* dynpm power management */
1613 struct delayed_work dynpm_idle_work;
1614 enum radeon_dynpm_state dynpm_state;
1615 enum radeon_dynpm_action dynpm_planned_action;
1616 unsigned long dynpm_action_timeout;
1617 bool dynpm_can_upclock;
1618 bool dynpm_can_downclock;
1619 /* profile-based power management */
1620 enum radeon_pm_profile_type profile;
1621 int profile_index;
1622 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
Alex Deucher21a81222010-07-02 12:58:16 -04001623 /* internal thermal controller on rv6xx+ */
1624 enum radeon_int_thermal_type int_thermal_type;
1625 struct device *int_hwmon_dev;
Alex Deucherda321c82013-04-12 13:55:22 -04001626 /* dpm */
1627 bool dpm_enabled;
1628 struct radeon_dpm dpm;
Jerome Glissec93bb852009-07-13 21:04:08 +02001629};
1630
Alex Deuchera4c9e2e2011-11-04 10:09:41 -04001631int radeon_pm_get_type_index(struct radeon_device *rdev,
1632 enum radeon_pm_state_type ps_type,
1633 int instance);
Christian Königf2ba57b2013-04-08 12:41:29 +02001634/*
1635 * UVD
1636 */
1637#define RADEON_MAX_UVD_HANDLES 10
1638#define RADEON_UVD_STACK_SIZE (1024*1024)
1639#define RADEON_UVD_HEAP_SIZE (1024*1024)
1640
1641struct radeon_uvd {
1642 struct radeon_bo *vcpu_bo;
1643 void *cpu_addr;
1644 uint64_t gpu_addr;
Christian König9cc2e0e2013-07-12 10:18:09 -04001645 void *saved_bo;
Christian Königf2ba57b2013-04-08 12:41:29 +02001646 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1647 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
Alex Deucher85a129c2013-08-05 12:41:20 -04001648 unsigned img_size[RADEON_MAX_UVD_HANDLES];
Christian König55b51c82013-04-18 15:25:59 +02001649 struct delayed_work idle_work;
Christian Königf2ba57b2013-04-08 12:41:29 +02001650};
1651
1652int radeon_uvd_init(struct radeon_device *rdev);
1653void radeon_uvd_fini(struct radeon_device *rdev);
1654int radeon_uvd_suspend(struct radeon_device *rdev);
1655int radeon_uvd_resume(struct radeon_device *rdev);
1656int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1657 uint32_t handle, struct radeon_fence **fence);
1658int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1659 uint32_t handle, struct radeon_fence **fence);
Christian König38527522014-08-21 12:18:12 +02001660void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1661 uint32_t allowed_domains);
Christian Königf2ba57b2013-04-08 12:41:29 +02001662void radeon_uvd_free_handles(struct radeon_device *rdev,
1663 struct drm_file *filp);
1664int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
Christian König55b51c82013-04-18 15:25:59 +02001665void radeon_uvd_note_usage(struct radeon_device *rdev);
Christian Königfacd1122013-04-29 11:55:02 +02001666int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1667 unsigned vclk, unsigned dclk,
1668 unsigned vco_min, unsigned vco_max,
1669 unsigned fb_factor, unsigned fb_mask,
1670 unsigned pd_min, unsigned pd_max,
1671 unsigned pd_even,
1672 unsigned *optimal_fb_div,
1673 unsigned *optimal_vclk_div,
1674 unsigned *optimal_dclk_div);
1675int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1676 unsigned cg_upll_func_cntl);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001677
Christian Königd93f7932013-05-23 12:10:04 +02001678/*
1679 * VCE
1680 */
1681#define RADEON_MAX_VCE_HANDLES 16
1682#define RADEON_VCE_STACK_SIZE (1024*1024)
1683#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1684
1685struct radeon_vce {
1686 struct radeon_bo *vcpu_bo;
Christian Königd93f7932013-05-23 12:10:04 +02001687 uint64_t gpu_addr;
Christian König98ccc292014-01-23 09:50:49 -07001688 unsigned fw_version;
1689 unsigned fb_version;
Christian Königd93f7932013-05-23 12:10:04 +02001690 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1691 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
Leo Liu2fc57032014-05-05 15:42:18 -04001692 unsigned img_size[RADEON_MAX_VCE_HANDLES];
Alex Deucher03afe6f2013-08-23 11:56:26 -04001693 struct delayed_work idle_work;
Christian Königd93f7932013-05-23 12:10:04 +02001694};
1695
1696int radeon_vce_init(struct radeon_device *rdev);
1697void radeon_vce_fini(struct radeon_device *rdev);
1698int radeon_vce_suspend(struct radeon_device *rdev);
1699int radeon_vce_resume(struct radeon_device *rdev);
1700int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1701 uint32_t handle, struct radeon_fence **fence);
1702int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1703 uint32_t handle, struct radeon_fence **fence);
1704void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
Alex Deucher03afe6f2013-08-23 11:56:26 -04001705void radeon_vce_note_usage(struct radeon_device *rdev);
Leo Liu2fc57032014-05-05 15:42:18 -04001706int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
Christian Königd93f7932013-05-23 12:10:04 +02001707int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1708bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1709 struct radeon_ring *ring,
1710 struct radeon_semaphore *semaphore,
1711 bool emit_wait);
1712void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1713void radeon_vce_fence_emit(struct radeon_device *rdev,
1714 struct radeon_fence *fence);
1715int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1716int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1717
Alex Deucherb5306022013-07-31 16:51:33 -04001718struct r600_audio_pin {
Rafał Miłeckia92553a2012-04-28 23:35:20 +02001719 int channels;
1720 int rate;
1721 int bits_per_sample;
1722 u8 status_bits;
1723 u8 category_code;
Alex Deucherb5306022013-07-31 16:51:33 -04001724 u32 offset;
1725 bool connected;
1726 u32 id;
1727};
1728
1729struct r600_audio {
1730 bool enabled;
1731 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1732 int num_pins;
Rafał Miłeckia92553a2012-04-28 23:35:20 +02001733};
1734
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001735/*
1736 * Benchmarking
1737 */
Ilija Hadzic638dd7d2011-10-12 23:29:39 -04001738void radeon_benchmark(struct radeon_device *rdev, int test_number);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001739
1740
1741/*
Michel Dänzerecc0b322009-07-21 11:23:57 +02001742 * Testing
1743 */
1744void radeon_test_moves(struct radeon_device *rdev);
Christian König60a7e392011-09-27 12:31:00 +02001745void radeon_test_ring_sync(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +02001746 struct radeon_ring *cpA,
1747 struct radeon_ring *cpB);
Christian König60a7e392011-09-27 12:31:00 +02001748void radeon_test_syncing(struct radeon_device *rdev);
Michel Dänzerecc0b322009-07-21 11:23:57 +02001749
Christian König341cb9e2014-08-07 09:36:03 +02001750/*
1751 * MMU Notifier
1752 */
1753int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1754void radeon_mn_unregister(struct radeon_bo *bo);
Michel Dänzerecc0b322009-07-21 11:23:57 +02001755
1756/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001757 * Debugfs
1758 */
Christian König4d8bf9a2011-10-24 14:54:54 +02001759struct radeon_debugfs {
1760 struct drm_info_list *files;
1761 unsigned num_files;
1762};
1763
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001764int radeon_debugfs_add_files(struct radeon_device *rdev,
1765 struct drm_info_list *files,
1766 unsigned nfiles);
1767int radeon_debugfs_fence_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001768
Christian König76a0df82013-08-13 11:56:50 +02001769/*
1770 * ASIC ring specific functions.
1771 */
1772struct radeon_asic_ring {
1773 /* ring read/write ptr handling */
1774 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1775 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1776 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1777
1778 /* validating and patching of IBs */
1779 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1780 int (*cs_parse)(struct radeon_cs_parser *p);
1781
1782 /* command emmit functions */
1783 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1784 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
Michel Dänzer72a99872014-07-31 18:43:49 +09001785 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König1654b812013-11-12 12:58:05 +01001786 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
Christian König76a0df82013-08-13 11:56:50 +02001787 struct radeon_semaphore *semaphore, bool emit_wait);
1788 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1789
1790 /* testing functions */
1791 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1792 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1793 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1794
1795 /* deprecated */
1796 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1797};
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001798
1799/*
1800 * ASIC specific functions.
1801 */
1802struct radeon_asic {
Jerome Glisse068a1172009-06-17 13:28:30 +02001803 int (*init)(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001804 void (*fini)(struct radeon_device *rdev);
1805 int (*resume)(struct radeon_device *rdev);
1806 int (*suspend)(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +10001807 void (*vga_set_state)(struct radeon_device *rdev, bool state);
Jerome Glissea2d07b72010-03-09 14:45:11 +00001808 int (*asic_reset)(struct radeon_device *rdev);
Michel Dänzer124764f2014-07-31 18:43:48 +09001809 /* Flush the HDP cache via MMIO */
1810 void (*mmio_hdp_flush)(struct radeon_device *rdev);
Alex Deucher54e88e02012-02-23 18:10:29 -05001811 /* check if 3D engine is idle */
1812 bool (*gui_idle)(struct radeon_device *rdev);
1813 /* wait for mc_idle */
1814 int (*mc_wait_for_idle)(struct radeon_device *rdev);
Alex Deucher454d2e22013-02-14 10:04:02 -05001815 /* get the reference clock */
1816 u32 (*get_xclk)(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -05001817 /* get the gpu clock counter */
1818 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
Alex Deucher54e88e02012-02-23 18:10:29 -05001819 /* gart */
Alex Deucherc5b3b852012-02-23 17:53:46 -05001820 struct {
1821 void (*tlb_flush)(struct radeon_device *rdev);
Christian König7f90fc92014-06-04 15:29:57 +02001822 void (*set_page)(struct radeon_device *rdev, unsigned i,
Michel Dänzer77497f22014-07-17 19:01:07 +09001823 uint64_t addr, uint32_t flags);
Alex Deucherc5b3b852012-02-23 17:53:46 -05001824 } gart;
Christian König05b07142012-08-06 20:21:10 +02001825 struct {
1826 int (*init)(struct radeon_device *rdev);
1827 void (*fini)(struct radeon_device *rdev);
Christian König03f62ab2014-07-30 21:05:17 +02001828 void (*copy_pages)(struct radeon_device *rdev,
1829 struct radeon_ib *ib,
1830 uint64_t pe, uint64_t src,
1831 unsigned count);
1832 void (*write_pages)(struct radeon_device *rdev,
1833 struct radeon_ib *ib,
1834 uint64_t pe,
1835 uint64_t addr, unsigned count,
1836 uint32_t incr, uint32_t flags);
1837 void (*set_pages)(struct radeon_device *rdev,
1838 struct radeon_ib *ib,
1839 uint64_t pe,
1840 uint64_t addr, unsigned count,
1841 uint32_t incr, uint32_t flags);
1842 void (*pad_ib)(struct radeon_ib *ib);
Christian König05b07142012-08-06 20:21:10 +02001843 } vm;
Alex Deucher54e88e02012-02-23 18:10:29 -05001844 /* ring specific callbacks */
Christian König76a0df82013-08-13 11:56:50 +02001845 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
Alex Deucher54e88e02012-02-23 18:10:29 -05001846 /* irqs */
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001847 struct {
1848 int (*set)(struct radeon_device *rdev);
1849 int (*process)(struct radeon_device *rdev);
1850 } irq;
Alex Deucher54e88e02012-02-23 18:10:29 -05001851 /* displays */
Alex Deucherc79a49c2012-02-23 17:53:47 -05001852 struct {
1853 /* display watermarks */
1854 void (*bandwidth_update)(struct radeon_device *rdev);
1855 /* get frame count */
1856 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1857 /* wait for vblank */
1858 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001859 /* set backlight level */
1860 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -04001861 /* get backlight level */
1862 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
Alex Deuchera973bea2013-04-18 11:32:16 -04001863 /* audio callbacks */
1864 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1865 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucherc79a49c2012-02-23 17:53:47 -05001866 } display;
Alex Deucher54e88e02012-02-23 18:10:29 -05001867 /* copy functions for bo handling */
Alex Deucher27cd7762012-02-23 17:53:42 -05001868 struct {
Christian König57d20a42014-09-04 20:01:53 +02001869 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1870 uint64_t src_offset,
1871 uint64_t dst_offset,
1872 unsigned num_gpu_pages,
1873 struct reservation_object *resv);
Alex Deucher27cd7762012-02-23 17:53:42 -05001874 u32 blit_ring_index;
Christian König57d20a42014-09-04 20:01:53 +02001875 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1876 uint64_t src_offset,
1877 uint64_t dst_offset,
1878 unsigned num_gpu_pages,
1879 struct reservation_object *resv);
Alex Deucher27cd7762012-02-23 17:53:42 -05001880 u32 dma_ring_index;
1881 /* method used for bo copy */
Christian König57d20a42014-09-04 20:01:53 +02001882 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1883 uint64_t src_offset,
1884 uint64_t dst_offset,
1885 unsigned num_gpu_pages,
1886 struct reservation_object *resv);
Alex Deucher27cd7762012-02-23 17:53:42 -05001887 /* ring used for bo copies */
1888 u32 copy_ring_index;
1889 } copy;
Alex Deucher54e88e02012-02-23 18:10:29 -05001890 /* surfaces */
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001891 struct {
1892 int (*set_reg)(struct radeon_device *rdev, int reg,
1893 uint32_t tiling_flags, uint32_t pitch,
1894 uint32_t offset, uint32_t obj_size);
1895 void (*clear_reg)(struct radeon_device *rdev, int reg);
1896 } surface;
Alex Deucher54e88e02012-02-23 18:10:29 -05001897 /* hotplug detect */
Alex Deucher901ea572012-02-23 17:53:39 -05001898 struct {
1899 void (*init)(struct radeon_device *rdev);
1900 void (*fini)(struct radeon_device *rdev);
1901 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1902 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1903 } hpd;
Alex Deucherda321c82013-04-12 13:55:22 -04001904 /* static power management */
Alex Deuchera02fa392012-02-23 17:53:41 -05001905 struct {
1906 void (*misc)(struct radeon_device *rdev);
1907 void (*prepare)(struct radeon_device *rdev);
1908 void (*finish)(struct radeon_device *rdev);
1909 void (*init_profile)(struct radeon_device *rdev);
1910 void (*get_dynpm_state)(struct radeon_device *rdev);
Alex Deucher798bcf72012-02-23 17:53:48 -05001911 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1912 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1913 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1914 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1915 int (*get_pcie_lanes)(struct radeon_device *rdev);
1916 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1917 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
Alex Deucher73afc702013-04-08 12:41:30 +02001918 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucherb59b7332013-08-20 20:01:18 -04001919 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -04001920 int (*get_temperature)(struct radeon_device *rdev);
Alex Deuchera02fa392012-02-23 17:53:41 -05001921 } pm;
Alex Deucherda321c82013-04-12 13:55:22 -04001922 /* dynamic power management */
1923 struct {
1924 int (*init)(struct radeon_device *rdev);
1925 void (*setup_asic)(struct radeon_device *rdev);
1926 int (*enable)(struct radeon_device *rdev);
Alex Deucher914a8982013-12-19 11:37:22 -05001927 int (*late_enable)(struct radeon_device *rdev);
Alex Deucherda321c82013-04-12 13:55:22 -04001928 void (*disable)(struct radeon_device *rdev);
Alex Deucher84dd1922013-01-16 12:52:04 -05001929 int (*pre_set_power_state)(struct radeon_device *rdev);
Alex Deucherda321c82013-04-12 13:55:22 -04001930 int (*set_power_state)(struct radeon_device *rdev);
Alex Deucher84dd1922013-01-16 12:52:04 -05001931 void (*post_set_power_state)(struct radeon_device *rdev);
Alex Deucherda321c82013-04-12 13:55:22 -04001932 void (*display_configuration_changed)(struct radeon_device *rdev);
1933 void (*fini)(struct radeon_device *rdev);
1934 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1935 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1936 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
Alex Deucher1316b792013-06-28 09:28:39 -04001937 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
Alex Deucher70d01a52013-07-02 18:38:02 -04001938 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
Alex Deucher48783062013-07-08 11:35:06 -04001939 bool (*vblank_too_short)(struct radeon_device *rdev);
Alex Deucher9e9d9762013-07-31 18:13:23 -04001940 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
Alex Deucher1c71bda2013-09-09 19:11:52 -04001941 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
Alex Deucherda321c82013-04-12 13:55:22 -04001942 } dpm;
Alex Deucher6f34be52010-11-21 10:59:01 -05001943 /* pageflipping */
Alex Deucher0f9e0062012-02-23 17:53:40 -05001944 struct {
Christian König157fa142014-05-27 16:49:20 +02001945 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1946 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
Alex Deucher0f9e0062012-02-23 17:53:40 -05001947 } pflip;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001948};
1949
Jerome Glisse21f9a4372009-09-11 15:55:33 +02001950/*
1951 * Asic structures
1952 */
Dave Airlie551ebd82009-09-01 15:25:57 +10001953struct r100_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001954 const unsigned *reg_safe_bm;
1955 unsigned reg_safe_bm_size;
1956 u32 hdp_cntl;
Dave Airlie551ebd82009-09-01 15:25:57 +10001957};
1958
Jerome Glisse21f9a4372009-09-11 15:55:33 +02001959struct r300_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001960 const unsigned *reg_safe_bm;
1961 unsigned reg_safe_bm_size;
1962 u32 resync_scratch;
1963 u32 hdp_cntl;
Jerome Glisse21f9a4372009-09-11 15:55:33 +02001964};
1965
1966struct r600_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001967 unsigned max_pipes;
1968 unsigned max_tile_pipes;
1969 unsigned max_simds;
1970 unsigned max_backends;
1971 unsigned max_gprs;
1972 unsigned max_threads;
1973 unsigned max_stack_entries;
1974 unsigned max_hw_contexts;
1975 unsigned max_gs_threads;
1976 unsigned sx_max_export_size;
1977 unsigned sx_max_export_pos_size;
1978 unsigned sx_max_export_smx_size;
1979 unsigned sq_num_cf_insts;
1980 unsigned tiling_nbanks;
1981 unsigned tiling_npipes;
1982 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001983 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001984 unsigned backend_map;
Alex Deucher65fcf662014-06-02 16:13:21 -04001985 unsigned active_simds;
Jerome Glisse21f9a4372009-09-11 15:55:33 +02001986};
1987
1988struct rv770_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001989 unsigned max_pipes;
1990 unsigned max_tile_pipes;
1991 unsigned max_simds;
1992 unsigned max_backends;
1993 unsigned max_gprs;
1994 unsigned max_threads;
1995 unsigned max_stack_entries;
1996 unsigned max_hw_contexts;
1997 unsigned max_gs_threads;
1998 unsigned sx_max_export_size;
1999 unsigned sx_max_export_pos_size;
2000 unsigned sx_max_export_smx_size;
2001 unsigned sq_num_cf_insts;
2002 unsigned sx_num_of_sets;
2003 unsigned sc_prim_fifo_size;
2004 unsigned sc_hiz_tile_fifo_size;
2005 unsigned sc_earlyz_tile_fifo_fize;
2006 unsigned tiling_nbanks;
2007 unsigned tiling_npipes;
2008 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04002009 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00002010 unsigned backend_map;
Alex Deucher65fcf662014-06-02 16:13:21 -04002011 unsigned active_simds;
Jerome Glisse21f9a4372009-09-11 15:55:33 +02002012};
2013
Alex Deucher32fcdbf2010-03-24 13:33:47 -04002014struct evergreen_asic {
2015 unsigned num_ses;
2016 unsigned max_pipes;
2017 unsigned max_tile_pipes;
2018 unsigned max_simds;
2019 unsigned max_backends;
2020 unsigned max_gprs;
2021 unsigned max_threads;
2022 unsigned max_stack_entries;
2023 unsigned max_hw_contexts;
2024 unsigned max_gs_threads;
2025 unsigned sx_max_export_size;
2026 unsigned sx_max_export_pos_size;
2027 unsigned sx_max_export_smx_size;
2028 unsigned sq_num_cf_insts;
2029 unsigned sx_num_of_sets;
2030 unsigned sc_prim_fifo_size;
2031 unsigned sc_hiz_tile_fifo_size;
2032 unsigned sc_earlyz_tile_fifo_size;
2033 unsigned tiling_nbanks;
2034 unsigned tiling_npipes;
2035 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04002036 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00002037 unsigned backend_map;
Alex Deucher65fcf662014-06-02 16:13:21 -04002038 unsigned active_simds;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04002039};
2040
Alex Deucherfecf1d02011-03-02 20:07:29 -05002041struct cayman_asic {
2042 unsigned max_shader_engines;
2043 unsigned max_pipes_per_simd;
2044 unsigned max_tile_pipes;
2045 unsigned max_simds_per_se;
2046 unsigned max_backends_per_se;
2047 unsigned max_texture_channel_caches;
2048 unsigned max_gprs;
2049 unsigned max_threads;
2050 unsigned max_gs_threads;
2051 unsigned max_stack_entries;
2052 unsigned sx_num_of_sets;
2053 unsigned sx_max_export_size;
2054 unsigned sx_max_export_pos_size;
2055 unsigned sx_max_export_smx_size;
2056 unsigned max_hw_contexts;
2057 unsigned sq_num_cf_insts;
2058 unsigned sc_prim_fifo_size;
2059 unsigned sc_hiz_tile_fifo_size;
2060 unsigned sc_earlyz_tile_fifo_size;
2061
2062 unsigned num_shader_engines;
2063 unsigned num_shader_pipes_per_simd;
2064 unsigned num_tile_pipes;
2065 unsigned num_simds_per_se;
2066 unsigned num_backends_per_se;
2067 unsigned backend_disable_mask_per_asic;
2068 unsigned backend_map;
2069 unsigned num_texture_channel_caches;
2070 unsigned mem_max_burst_length_bytes;
2071 unsigned mem_row_size_in_kb;
2072 unsigned shader_engine_tile_size;
2073 unsigned num_gpus;
2074 unsigned multi_gpu_tile_size;
2075
2076 unsigned tile_config;
Alex Deucher65fcf662014-06-02 16:13:21 -04002077 unsigned active_simds;
Alex Deucherfecf1d02011-03-02 20:07:29 -05002078};
2079
Alex Deucher0a96d722012-03-20 17:18:11 -04002080struct si_asic {
2081 unsigned max_shader_engines;
Alex Deucher0a96d722012-03-20 17:18:11 -04002082 unsigned max_tile_pipes;
Alex Deucher1a8ca752012-06-01 18:58:22 -04002083 unsigned max_cu_per_sh;
2084 unsigned max_sh_per_se;
Alex Deucher0a96d722012-03-20 17:18:11 -04002085 unsigned max_backends_per_se;
2086 unsigned max_texture_channel_caches;
2087 unsigned max_gprs;
2088 unsigned max_gs_threads;
2089 unsigned max_hw_contexts;
2090 unsigned sc_prim_fifo_size_frontend;
2091 unsigned sc_prim_fifo_size_backend;
2092 unsigned sc_hiz_tile_fifo_size;
2093 unsigned sc_earlyz_tile_fifo_size;
2094
Alex Deucher0a96d722012-03-20 17:18:11 -04002095 unsigned num_tile_pipes;
Marek Olšák439a1cf2013-12-22 02:18:01 +01002096 unsigned backend_enable_mask;
Alex Deucher0a96d722012-03-20 17:18:11 -04002097 unsigned backend_disable_mask_per_asic;
2098 unsigned backend_map;
2099 unsigned num_texture_channel_caches;
2100 unsigned mem_max_burst_length_bytes;
2101 unsigned mem_row_size_in_kb;
2102 unsigned shader_engine_tile_size;
2103 unsigned num_gpus;
2104 unsigned multi_gpu_tile_size;
2105
2106 unsigned tile_config;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -04002107 uint32_t tile_mode_array[32];
Alex Deucher65fcf662014-06-02 16:13:21 -04002108 uint32_t active_cus;
Alex Deucher0a96d722012-03-20 17:18:11 -04002109};
2110
Alex Deucher8cc1a532013-04-09 12:41:24 -04002111struct cik_asic {
2112 unsigned max_shader_engines;
2113 unsigned max_tile_pipes;
2114 unsigned max_cu_per_sh;
2115 unsigned max_sh_per_se;
2116 unsigned max_backends_per_se;
2117 unsigned max_texture_channel_caches;
2118 unsigned max_gprs;
2119 unsigned max_gs_threads;
2120 unsigned max_hw_contexts;
2121 unsigned sc_prim_fifo_size_frontend;
2122 unsigned sc_prim_fifo_size_backend;
2123 unsigned sc_hiz_tile_fifo_size;
2124 unsigned sc_earlyz_tile_fifo_size;
2125
2126 unsigned num_tile_pipes;
Marek Olšák439a1cf2013-12-22 02:18:01 +01002127 unsigned backend_enable_mask;
Alex Deucher8cc1a532013-04-09 12:41:24 -04002128 unsigned backend_disable_mask_per_asic;
2129 unsigned backend_map;
2130 unsigned num_texture_channel_caches;
2131 unsigned mem_max_burst_length_bytes;
2132 unsigned mem_row_size_in_kb;
2133 unsigned shader_engine_tile_size;
2134 unsigned num_gpus;
2135 unsigned multi_gpu_tile_size;
2136
2137 unsigned tile_config;
Alex Deucher39aee492013-04-10 13:41:25 -04002138 uint32_t tile_mode_array[32];
Michel Dänzer32f79a82013-11-18 18:26:00 +09002139 uint32_t macrotile_mode_array[16];
Alex Deucher65fcf662014-06-02 16:13:21 -04002140 uint32_t active_cus;
Alex Deucher8cc1a532013-04-09 12:41:24 -04002141};
2142
Jerome Glisse068a1172009-06-17 13:28:30 +02002143union radeon_asic_config {
2144 struct r300_asic r300;
Dave Airlie551ebd82009-09-01 15:25:57 +10002145 struct r100_asic r100;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002146 struct r600_asic r600;
2147 struct rv770_asic rv770;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04002148 struct evergreen_asic evergreen;
Alex Deucherfecf1d02011-03-02 20:07:29 -05002149 struct cayman_asic cayman;
Alex Deucher0a96d722012-03-20 17:18:11 -04002150 struct si_asic si;
Alex Deucher8cc1a532013-04-09 12:41:24 -04002151 struct cik_asic cik;
Jerome Glisse068a1172009-06-17 13:28:30 +02002152};
2153
Daniel Vetter0a10c852010-03-11 21:19:14 +00002154/*
2155 * asic initizalization from radeon_asic.c
2156 */
2157void radeon_agp_disable(struct radeon_device *rdev);
2158int radeon_asic_init(struct radeon_device *rdev);
2159
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002160
2161/*
2162 * IOCTL.
2163 */
2164int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2165 struct drm_file *filp);
2166int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2167 struct drm_file *filp);
Christian Königf72a113a2014-08-07 09:36:00 +02002168int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2169 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002170int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2171 struct drm_file *file_priv);
2172int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2173 struct drm_file *file_priv);
2174int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2175 struct drm_file *file_priv);
2176int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2177 struct drm_file *file_priv);
2178int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2179 struct drm_file *filp);
2180int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2181 struct drm_file *filp);
2182int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2183 struct drm_file *filp);
2184int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2185 struct drm_file *filp);
Jerome Glisse721604a2012-01-05 22:11:05 -05002186int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2187 struct drm_file *filp);
Marek Olšákbda72d52014-03-02 00:56:17 +01002188int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2189 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002190int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Dave Airliee024e112009-06-24 09:48:08 +10002191int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2192 struct drm_file *filp);
2193int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2194 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002195
Alex Deucher16cdf042011-10-28 10:30:02 -04002196/* VRAM scratch page for HDP bug, default vram page */
2197struct r600_vram_scratch {
Alex Deucher87cbf8f2010-08-27 13:59:54 -04002198 struct radeon_bo *robj;
2199 volatile uint32_t *ptr;
Alex Deucher16cdf042011-10-28 10:30:02 -04002200 u64 gpu_addr;
Alex Deucher87cbf8f2010-08-27 13:59:54 -04002201};
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002202
Luca Tettamantifd64ca82012-08-16 11:11:18 -04002203/*
2204 * ACPI
2205 */
2206struct radeon_atif_notification_cfg {
2207 bool enabled;
2208 int command_code;
2209};
2210
2211struct radeon_atif_notifications {
2212 bool display_switch;
2213 bool expansion_mode_change;
2214 bool thermal_state;
2215 bool forced_power_state;
2216 bool system_power_state;
2217 bool display_conf_change;
2218 bool px_gfx_switch;
2219 bool brightness_change;
2220 bool dgpu_display_event;
2221};
2222
2223struct radeon_atif_functions {
2224 bool system_params;
2225 bool sbios_requests;
2226 bool select_active_disp;
2227 bool lid_state;
2228 bool get_tv_standard;
2229 bool set_tv_standard;
2230 bool get_panel_expansion_mode;
2231 bool set_panel_expansion_mode;
2232 bool temperature_change;
2233 bool graphics_device_types;
2234};
2235
2236struct radeon_atif {
2237 struct radeon_atif_notifications notifications;
2238 struct radeon_atif_functions functions;
2239 struct radeon_atif_notification_cfg notification_cfg;
Alex Deucher37e9b6a2012-08-03 11:39:43 -04002240 struct radeon_encoder *encoder_for_bl;
Luca Tettamantifd64ca82012-08-16 11:11:18 -04002241};
Michel Dänzer7a1619b2011-11-10 18:57:26 +01002242
Alex Deuchere3a15922012-08-16 11:13:43 -04002243struct radeon_atcs_functions {
2244 bool get_ext_state;
2245 bool pcie_perf_req;
2246 bool pcie_dev_rdy;
2247 bool pcie_bus_width;
2248};
2249
2250struct radeon_atcs {
2251 struct radeon_atcs_functions functions;
2252};
2253
Michel Dänzer7a1619b2011-11-10 18:57:26 +01002254/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002255 * Core structure, functions and helpers.
2256 */
2257typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2258typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2259
2260struct radeon_device {
Jerome Glisse9f022dd2009-09-11 15:35:22 +02002261 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002262 struct drm_device *ddev;
2263 struct pci_dev *pdev;
Jerome Glissedee53e72012-07-02 12:45:19 -04002264 struct rw_semaphore exclusive_lock;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002265 /* ASIC */
Jerome Glisse068a1172009-06-17 13:28:30 +02002266 union radeon_asic_config config;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002267 enum radeon_family family;
2268 unsigned long flags;
2269 int usec_timeout;
2270 enum radeon_pll_errata pll_errata;
2271 int num_gb_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -04002272 int num_z_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002273 int disp_priority;
2274 /* BIOS */
2275 uint8_t *bios;
2276 bool is_atom_bios;
2277 uint16_t bios_header_start;
Jerome Glisse4c788672009-11-20 14:29:23 +01002278 struct radeon_bo *stollen_vga_memory;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002279 /* Register mmio */
Dave Airlie4c9bc752009-06-29 18:29:12 +10002280 resource_size_t rmmio_base;
2281 resource_size_t rmmio_size;
Daniel Vetter2c385152012-12-02 14:06:15 +01002282 /* protects concurrent MM_INDEX/DATA based register access */
2283 spinlock_t mmio_idx_lock;
Alex Deucherfe781182013-09-03 18:19:42 -04002284 /* protects concurrent SMC based register access */
2285 spinlock_t smc_idx_lock;
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002286 /* protects concurrent PLL register access */
2287 spinlock_t pll_idx_lock;
2288 /* protects concurrent MC register access */
2289 spinlock_t mc_idx_lock;
2290 /* protects concurrent PCIE register access */
2291 spinlock_t pcie_idx_lock;
2292 /* protects concurrent PCIE_PORT register access */
2293 spinlock_t pciep_idx_lock;
2294 /* protects concurrent PIF register access */
2295 spinlock_t pif_idx_lock;
2296 /* protects concurrent CG register access */
2297 spinlock_t cg_idx_lock;
2298 /* protects concurrent UVD register access */
2299 spinlock_t uvd_idx_lock;
2300 /* protects concurrent RCU register access */
2301 spinlock_t rcu_idx_lock;
2302 /* protects concurrent DIDT register access */
2303 spinlock_t didt_idx_lock;
2304 /* protects concurrent ENDPOINT (audio) register access */
2305 spinlock_t end_idx_lock;
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00002306 void __iomem *rmmio;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002307 radeon_rreg_t mc_rreg;
2308 radeon_wreg_t mc_wreg;
2309 radeon_rreg_t pll_rreg;
2310 radeon_wreg_t pll_wreg;
Dave Airliede1b2892009-08-12 18:43:14 +10002311 uint32_t pcie_reg_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002312 radeon_rreg_t pciep_rreg;
2313 radeon_wreg_t pciep_wreg;
Alex Deucher351a52a2010-06-30 11:52:50 -04002314 /* io port */
2315 void __iomem *rio_mem;
2316 resource_size_t rio_mem_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002317 struct radeon_clock clock;
2318 struct radeon_mc mc;
2319 struct radeon_gart gart;
2320 struct radeon_mode_info mode_info;
2321 struct radeon_scratch scratch;
Alex Deucher75efdee2013-03-04 12:47:46 -05002322 struct radeon_doorbell doorbell;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002323 struct radeon_mman mman;
Alex Deucher74652802011-08-25 13:39:48 -04002324 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
Jerome Glisse0085c9502012-05-09 15:34:55 +02002325 wait_queue_head_t fence_queue;
Maarten Lankhorst954605c2014-01-09 11:03:12 +01002326 unsigned fence_context;
Christian Königd6999bc2012-05-09 15:34:45 +02002327 struct mutex ring_lock;
Christian Könige32eb502011-10-23 12:56:27 +02002328 struct radeon_ring ring[RADEON_NUM_RINGS];
Jerome Glissec507f7e2012-05-09 15:34:58 +02002329 bool ib_pool_ready;
2330 struct radeon_sa_manager ring_tmp_bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002331 struct radeon_irq irq;
2332 struct radeon_asic *asic;
2333 struct radeon_gem gem;
Jerome Glissec93bb852009-07-13 21:04:08 +02002334 struct radeon_pm pm;
Christian Königf2ba57b2013-04-08 12:41:29 +02002335 struct radeon_uvd uvd;
Christian Königd93f7932013-05-23 12:10:04 +02002336 struct radeon_vce vce;
Yang Zhaof657c2a2009-09-15 12:21:01 +10002337 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002338 struct radeon_wb wb;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002339 struct radeon_dummy_page dummy_page;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002340 bool shutdown;
2341 bool suspend;
Dave Airliead49f502009-07-10 22:36:26 +10002342 bool need_dma32;
Jerome Glisse733289c2009-09-16 15:24:21 +02002343 bool accel_working;
Samuel Lia0a53aa2013-04-08 17:25:47 -04002344 bool fastfb_working; /* IGP feature*/
Maarten Lankhorst9bb39ff2014-08-27 16:45:18 -04002345 bool needs_reset, in_reset;
Dave Airliee024e112009-06-24 09:48:08 +10002346 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002347 const struct firmware *me_fw; /* all family ME firmware */
2348 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002349 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
Alex Deucher0af62b02011-01-06 21:19:31 -05002350 const struct firmware *mc_fw; /* NI MC firmware */
Alex Deucher0f0de062012-03-20 17:18:17 -04002351 const struct firmware *ce_fw; /* SI CE firmware */
Alex Deucher02c81322012-12-18 21:43:07 -05002352 const struct firmware *mec_fw; /* CIK MEC firmware */
Alex Deucherf2c6b0f2014-06-25 19:32:36 -04002353 const struct firmware *mec2_fw; /* KV MEC2 firmware */
Alex Deucher21a93e12013-04-09 12:47:11 -04002354 const struct firmware *sdma_fw; /* CIK SDMA firmware */
Alex Deucher66229b22013-06-26 00:11:19 -04002355 const struct firmware *smc_fw; /* SMC firmware */
Christian König4ad9c1c2013-08-05 14:10:55 +02002356 const struct firmware *uvd_fw; /* UVD firmware */
Christian Königd93f7932013-05-23 12:10:04 +02002357 const struct firmware *vce_fw; /* VCE firmware */
Alex Deucher629bd332014-06-25 18:41:34 -04002358 bool new_fw;
Alex Deucher16cdf042011-10-28 10:30:02 -04002359 struct r600_vram_scratch vram_scratch;
Alex Deucher3e5cb982009-10-16 12:21:24 -04002360 int msi_enabled; /* msi enabled */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002361 struct r600_ih ih; /* r6/700 interrupt ring */
Alex Deucher2948f5e2013-04-12 13:52:52 -04002362 struct radeon_rlc rlc;
Alex Deucher963e81f2013-06-26 17:37:11 -04002363 struct radeon_mec mec;
Alex Deucherd4877cf2009-12-04 16:56:37 -05002364 struct work_struct hotplug_work;
Alex Deucherf122c612012-03-30 08:59:57 -04002365 struct work_struct audio_work;
Alex Deucher18917b62010-02-01 16:02:25 -05002366 int num_crtc; /* number of crtcs */
Alex Deucher40bacf12009-12-23 03:23:21 -05002367 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
Alex Deucher948bee32013-05-14 12:08:35 -04002368 bool has_uvd;
Alex Deucherb5306022013-07-31 16:51:33 -04002369 struct r600_audio audio; /* audio stuff */
Alex Deucherce8f5372010-05-07 15:10:16 -04002370 struct notifier_block acpi_nb;
Marek Olšák9eba4a92011-01-05 05:46:48 +01002371 /* only one userspace can use Hyperz features or CMASK at a time */
Dave Airlieab9e1f52010-07-13 11:11:11 +10002372 struct drm_file *hyperz_filp;
Marek Olšák9eba4a92011-01-05 05:46:48 +01002373 struct drm_file *cmask_filp;
Alex Deucherf376b942010-08-05 21:21:16 -04002374 /* i2c buses */
2375 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
Christian König4d8bf9a2011-10-24 14:54:54 +02002376 /* debugfs */
2377 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2378 unsigned debugfs_count;
Jerome Glisse721604a2012-01-05 22:11:05 -05002379 /* virtual memory */
2380 struct radeon_vm_manager vm_manager;
Marek Olšák6759a0a2012-08-09 16:34:17 +02002381 struct mutex gpu_clock_mutex;
Marek Olšák67e8e3f2014-03-02 00:56:18 +01002382 /* memory stats */
2383 atomic64_t vram_usage;
2384 atomic64_t gtt_usage;
2385 atomic64_t num_bytes_moved;
Luca Tettamantifd64ca82012-08-16 11:11:18 -04002386 /* ACPI interface */
2387 struct radeon_atif atif;
Alex Deuchere3a15922012-08-16 11:13:43 -04002388 struct radeon_atcs atcs;
Alex Deucherf61d5b462013-08-06 12:40:16 -04002389 /* srbm instance registers */
2390 struct mutex srbm_mutex;
Alex Deucher64d8a722013-08-08 16:31:25 -04002391 /* clock, powergating flags */
2392 u32 cg_flags;
2393 u32 pg_flags;
Dave Airlie10ebc0b2012-09-17 14:40:31 +10002394
2395 struct dev_pm_domain vga_pm_domain;
2396 bool have_disp_power_ref;
Alex Deucher4807c5a2014-07-18 11:54:20 -04002397 u32 px_quirk_flags;
Alex Deucher71ecc972014-07-17 12:09:25 -04002398
2399 /* tracking pinned memory */
2400 u64 vram_pin_size;
2401 u64 gart_pin_size;
Christian König341cb9e2014-08-07 09:36:03 +02002402
2403 struct mutex mn_lock;
2404 DECLARE_HASHTABLE(mn_hash, 7);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002405};
2406
Alex Deucher90c4cde2014-04-10 22:29:01 -04002407bool radeon_is_px(struct drm_device *dev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002408int radeon_device_init(struct radeon_device *rdev,
2409 struct drm_device *ddev,
2410 struct pci_dev *pdev,
2411 uint32_t flags);
2412void radeon_device_fini(struct radeon_device *rdev);
2413int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2414
Lauri Kasanen59bc1d82014-04-20 20:29:33 +03002415#define RADEON_MIN_MMIO_SIZE 0x10000
2416
2417static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2418 bool always_indirect)
2419{
2420 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2421 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2422 return readl(((void __iomem *)rdev->rmmio) + reg);
2423 else {
2424 unsigned long flags;
2425 uint32_t ret;
2426
2427 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2428 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2429 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2430 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2431
2432 return ret;
2433 }
2434}
2435
2436static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2437 bool always_indirect)
2438{
2439 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2440 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2441 else {
2442 unsigned long flags;
2443
2444 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2445 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2446 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2447 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2448 }
2449}
2450
Andi Kleen6fcbef72011-10-13 16:08:42 -07002451u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2452void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
Alex Deucher351a52a2010-06-30 11:52:50 -04002453
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -05002454u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2455void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
Alex Deucher75efdee2013-03-04 12:47:46 -05002456
Jerome Glisse4c788672009-11-20 14:29:23 +01002457/*
2458 * Cast helper
2459 */
Maarten Lankhorst954605c2014-01-09 11:03:12 +01002460extern const struct fence_ops radeon_fence_ops;
2461
2462static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2463{
2464 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2465
2466 if (__f->base.ops == &radeon_fence_ops)
2467 return __f;
2468
2469 return NULL;
2470}
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002471
2472/*
2473 * Registers read & write functions.
2474 */
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00002475#define RREG8(reg) readb((rdev->rmmio) + (reg))
2476#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2477#define RREG16(reg) readw((rdev->rmmio) + (reg))
2478#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
Daniel Vetter2ef9bdf2012-12-02 14:02:51 +01002479#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2480#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2481#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2482#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2483#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002484#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2485#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2486#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2487#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2488#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2489#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
Dave Airliede1b2892009-08-12 18:43:14 +10002490#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2491#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
Alex Deucher492d2b62012-10-25 16:06:59 -04002492#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2493#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002494#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2495#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
Alex Deucherff82bbc2013-04-12 11:27:20 -04002496#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2497#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
Alex Deucher46f95642013-04-12 11:49:51 -04002498#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2499#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
Alex Deucher792edd62013-02-14 18:18:12 -05002500#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2501#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2502#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2503#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
Alex Deucher93656cd2013-02-25 15:18:39 -05002504#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2505#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
Alex Deucher1d582342013-04-19 13:03:37 -04002506#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2507#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002508#define WREG32_P(reg, val, mask) \
2509 do { \
2510 uint32_t tmp_ = RREG32(reg); \
2511 tmp_ &= (mask); \
2512 tmp_ |= ((val) & ~(mask)); \
2513 WREG32(reg, tmp_); \
2514 } while (0)
Rafał Miłeckid5169fc2013-04-14 01:26:19 +02002515#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
Rafał Miłeckid43a93c2013-08-15 18:55:22 +02002516#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002517#define WREG32_PLL_P(reg, val, mask) \
2518 do { \
2519 uint32_t tmp_ = RREG32_PLL(reg); \
2520 tmp_ &= (mask); \
2521 tmp_ |= ((val) & ~(mask)); \
2522 WREG32_PLL(reg, tmp_); \
2523 } while (0)
Daniel Vetter2ef9bdf2012-12-02 14:02:51 +01002524#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
Alex Deucher351a52a2010-06-30 11:52:50 -04002525#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2526#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002527
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -05002528#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2529#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
Alex Deucher75efdee2013-03-04 12:47:46 -05002530
Dave Airliede1b2892009-08-12 18:43:14 +10002531/*
2532 * Indirect registers accessor
2533 */
2534static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2535{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002536 unsigned long flags;
Dave Airliede1b2892009-08-12 18:43:14 +10002537 uint32_t r;
2538
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002539 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002540 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2541 r = RREG32(RADEON_PCIE_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002542 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002543 return r;
2544}
2545
2546static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2547{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002548 unsigned long flags;
2549
2550 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002551 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2552 WREG32(RADEON_PCIE_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002553 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002554}
2555
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002556static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2557{
Alex Deucherfe781182013-09-03 18:19:42 -04002558 unsigned long flags;
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002559 u32 r;
2560
Alex Deucherfe781182013-09-03 18:19:42 -04002561 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002562 WREG32(TN_SMC_IND_INDEX_0, (reg));
2563 r = RREG32(TN_SMC_IND_DATA_0);
Alex Deucherfe781182013-09-03 18:19:42 -04002564 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002565 return r;
2566}
2567
2568static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2569{
Alex Deucherfe781182013-09-03 18:19:42 -04002570 unsigned long flags;
2571
2572 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002573 WREG32(TN_SMC_IND_INDEX_0, (reg));
2574 WREG32(TN_SMC_IND_DATA_0, (v));
Alex Deucherfe781182013-09-03 18:19:42 -04002575 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002576}
2577
Alex Deucherff82bbc2013-04-12 11:27:20 -04002578static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2579{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002580 unsigned long flags;
Alex Deucherff82bbc2013-04-12 11:27:20 -04002581 u32 r;
2582
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002583 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002584 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2585 r = RREG32(R600_RCU_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002586 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002587 return r;
2588}
2589
2590static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2591{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002592 unsigned long flags;
2593
2594 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002595 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2596 WREG32(R600_RCU_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002597 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002598}
2599
Alex Deucher46f95642013-04-12 11:49:51 -04002600static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2601{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002602 unsigned long flags;
Alex Deucher46f95642013-04-12 11:49:51 -04002603 u32 r;
2604
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002605 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002606 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2607 r = RREG32(EVERGREEN_CG_IND_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002608 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002609 return r;
2610}
2611
2612static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2613{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002614 unsigned long flags;
2615
2616 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002617 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2618 WREG32(EVERGREEN_CG_IND_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002619 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002620}
2621
Alex Deucher792edd62013-02-14 18:18:12 -05002622static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2623{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002624 unsigned long flags;
Alex Deucher792edd62013-02-14 18:18:12 -05002625 u32 r;
2626
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002627 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002628 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2629 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002630 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002631 return r;
2632}
2633
2634static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2635{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002636 unsigned long flags;
2637
2638 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002639 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2640 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002641 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002642}
2643
2644static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2645{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002646 unsigned long flags;
Alex Deucher792edd62013-02-14 18:18:12 -05002647 u32 r;
2648
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002649 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002650 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2651 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002652 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002653 return r;
2654}
2655
2656static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2657{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002658 unsigned long flags;
2659
2660 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002661 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2662 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002663 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002664}
2665
Alex Deucher93656cd2013-02-25 15:18:39 -05002666static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2667{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002668 unsigned long flags;
Alex Deucher93656cd2013-02-25 15:18:39 -05002669 u32 r;
2670
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002671 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002672 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2673 r = RREG32(R600_UVD_CTX_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002674 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002675 return r;
2676}
2677
2678static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2679{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002680 unsigned long flags;
2681
2682 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002683 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2684 WREG32(R600_UVD_CTX_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002685 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002686}
2687
Alex Deucher1d582342013-04-19 13:03:37 -04002688
2689static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2690{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002691 unsigned long flags;
Alex Deucher1d582342013-04-19 13:03:37 -04002692 u32 r;
2693
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002694 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002695 WREG32(CIK_DIDT_IND_INDEX, (reg));
2696 r = RREG32(CIK_DIDT_IND_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002697 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002698 return r;
2699}
2700
2701static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2702{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002703 unsigned long flags;
2704
2705 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002706 WREG32(CIK_DIDT_IND_INDEX, (reg));
2707 WREG32(CIK_DIDT_IND_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002708 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002709}
2710
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002711void r100_pll_errata_after_index(struct radeon_device *rdev);
2712
2713
2714/*
2715 * ASICs helpers.
2716 */
Dave Airlieb995e432009-07-14 02:02:32 +10002717#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2718 (rdev->pdev->device == 0x5969))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002719#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2720 (rdev->family == CHIP_RV200) || \
2721 (rdev->family == CHIP_RS100) || \
2722 (rdev->family == CHIP_RS200) || \
2723 (rdev->family == CHIP_RV250) || \
2724 (rdev->family == CHIP_RV280) || \
2725 (rdev->family == CHIP_RS300))
2726#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2727 (rdev->family == CHIP_RV350) || \
2728 (rdev->family == CHIP_R350) || \
2729 (rdev->family == CHIP_RV380) || \
2730 (rdev->family == CHIP_R420) || \
2731 (rdev->family == CHIP_R423) || \
2732 (rdev->family == CHIP_RV410) || \
2733 (rdev->family == CHIP_RS400) || \
2734 (rdev->family == CHIP_RS480))
Alex Deucher3313e3d2011-01-06 18:49:34 -05002735#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2736 (rdev->ddev->pdev->device == 0x9443) || \
2737 (rdev->ddev->pdev->device == 0x944B) || \
2738 (rdev->ddev->pdev->device == 0x9506) || \
2739 (rdev->ddev->pdev->device == 0x9509) || \
2740 (rdev->ddev->pdev->device == 0x950F) || \
2741 (rdev->ddev->pdev->device == 0x689C) || \
2742 (rdev->ddev->pdev->device == 0x689D))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002743#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
Alex Deucher99999aa2010-11-16 12:09:41 -05002744#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2745 (rdev->family == CHIP_RS690) || \
2746 (rdev->family == CHIP_RS740) || \
2747 (rdev->family >= CHIP_R600))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002748#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2749#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
Alex Deucherbcc1c2a2010-01-12 17:54:34 -05002750#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
Alex Deucher633b9162011-01-06 21:19:11 -05002751#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2752 (rdev->flags & RADEON_IS_IGP))
Alex Deucher1fe18302011-01-06 21:19:12 -05002753#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
Alex Deucher8848f752012-03-20 17:18:28 -04002754#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2755#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2756 (rdev->flags & RADEON_IS_IGP))
Alex Deucher624d3522012-12-18 17:01:35 -05002757#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
Alex Deucherb5d9d722012-07-26 18:53:55 -04002758#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
Alex Deuchere2829172013-06-07 11:37:11 -04002759#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
Alex Deucherbe0949f2014-04-08 11:28:54 -04002760#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2761#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
Alex Deucher89d26182014-05-08 18:26:23 -04002762#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2763 (rdev->family == CHIP_MULLINS))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002764
Alex Deucherdc50ba72013-06-26 00:33:35 -04002765#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2766 (rdev->ddev->pdev->device == 0x6850) || \
2767 (rdev->ddev->pdev->device == 0x6858) || \
2768 (rdev->ddev->pdev->device == 0x6859) || \
2769 (rdev->ddev->pdev->device == 0x6840) || \
2770 (rdev->ddev->pdev->device == 0x6841) || \
2771 (rdev->ddev->pdev->device == 0x6842) || \
2772 (rdev->ddev->pdev->device == 0x6843))
2773
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002774/*
2775 * BIOS helpers.
2776 */
2777#define RBIOS8(i) (rdev->bios[i])
2778#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2779#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2780
2781int radeon_combios_init(struct radeon_device *rdev);
2782void radeon_combios_fini(struct radeon_device *rdev);
2783int radeon_atombios_init(struct radeon_device *rdev);
2784void radeon_atombios_fini(struct radeon_device *rdev);
2785
2786
2787/*
2788 * RING helpers.
2789 */
David Herrmannedf0ac72014-08-29 12:12:38 +02002790
2791/**
2792 * radeon_ring_write - write a value to the ring
2793 *
2794 * @ring: radeon_ring structure holding ring information
2795 * @v: dword (dw) value to write
2796 *
2797 * Write a value to the requested ring buffer (all asics).
2798 */
Christian Könige32eb502011-10-23 12:56:27 +02002799static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002800{
David Herrmannedf0ac72014-08-29 12:12:38 +02002801 if (ring->count_dw <= 0)
2802 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2803
Christian Könige32eb502011-10-23 12:56:27 +02002804 ring->ring[ring->wptr++] = v;
2805 ring->wptr &= ring->ptr_mask;
2806 ring->count_dw--;
2807 ring->ring_free_dw--;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002808}
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002809
2810/*
2811 * ASICs macro.
2812 */
Jerome Glisse068a1172009-06-17 13:28:30 +02002813#define radeon_init(rdev) (rdev)->asic->init((rdev))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002814#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2815#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2816#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
Christian König76a0df82013-08-13 11:56:50 +02002817#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
Dave Airlie28d52042009-09-21 14:33:58 +10002818#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
Jerome Glissea2d07b72010-03-09 14:45:11 +00002819#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
Alex Deucherc5b3b852012-02-23 17:53:46 -05002820#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
Michel Dänzer77497f22014-07-17 19:01:07 +09002821#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
Christian König05b07142012-08-06 20:21:10 +02002822#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2823#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
Christian König03f62ab2014-07-30 21:05:17 +02002824#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2825#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2826#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2827#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
Christian König76a0df82013-08-13 11:56:50 +02002828#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2829#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2830#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2831#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2832#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2833#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2834#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2835#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2836#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2837#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
Alex Deucherb35ea4a2012-02-23 17:53:43 -05002838#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2839#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
Alex Deucherc79a49c2012-02-23 17:53:47 -05002840#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
Alex Deucher37e9b6a2012-08-03 11:39:43 -04002841#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
Alex Deucher6d92f812012-09-14 09:59:26 -04002842#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
Alex Deuchera973bea2013-04-18 11:32:16 -04002843#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2844#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
Christian König76a0df82013-08-13 11:56:50 +02002845#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2846#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
Christian König57d20a42014-09-04 20:01:53 +02002847#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2848#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2849#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
Alex Deucher27cd7762012-02-23 17:53:42 -05002850#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2851#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2852#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
Alex Deucher798bcf72012-02-23 17:53:48 -05002853#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2854#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2855#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2856#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2857#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2858#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2859#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
Alex Deucher73afc702013-04-08 12:41:30 +02002860#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
Alex Deucherb59b7332013-08-20 20:01:18 -04002861#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
Alex Deucher6bd1c382013-06-21 14:38:03 -04002862#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
Alex Deucher9e6f3d02012-02-23 17:53:49 -05002863#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2864#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
Alex Deucherc79a49c2012-02-23 17:53:47 -05002865#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
Alex Deucher901ea572012-02-23 17:53:39 -05002866#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2867#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2868#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2869#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
Alex Deucherdef9ba92010-04-22 12:39:58 -04002870#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
Alex Deuchera02fa392012-02-23 17:53:41 -05002871#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2872#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2873#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2874#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2875#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
Alex Deucher69b62ad2012-08-03 11:50:54 -04002876#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
Christian König157fa142014-05-27 16:49:20 +02002877#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
Alex Deucher69b62ad2012-08-03 11:50:54 -04002878#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2879#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
Alex Deucher454d2e22013-02-14 10:04:02 -05002880#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
Alex Deucherd0418892013-01-24 10:35:23 -05002881#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002882#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2883#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2884#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
Alex Deucher914a8982013-12-19 11:37:22 -05002885#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002886#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
Alex Deucher84dd1922013-01-16 12:52:04 -05002887#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002888#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
Alex Deucher84dd1922013-01-16 12:52:04 -05002889#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002890#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2891#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2892#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2893#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2894#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
Alex Deucher1316b792013-06-28 09:28:39 -04002895#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
Alex Deucher70d01a52013-07-02 18:38:02 -04002896#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
Alex Deucher48783062013-07-08 11:35:06 -04002897#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
Alex Deucher9e9d9762013-07-31 18:13:23 -04002898#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
Alex Deucher1c71bda2013-09-09 19:11:52 -04002899#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002900
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02002901/* Common functions */
Jerome Glisse700a0cc2010-01-13 15:16:38 +01002902/* AGP */
Jerome Glisse90aca4d2010-03-09 14:45:12 +00002903extern int radeon_gpu_reset(struct radeon_device *rdev);
Alex Deucher1a0041b2013-10-02 13:01:36 -04002904extern void radeon_pci_config_reset(struct radeon_device *rdev);
Alex Deucher410a3412013-01-18 13:05:39 -05002905extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
Jerome Glisse700a0cc2010-01-13 15:16:38 +01002906extern void radeon_agp_disable(struct radeon_device *rdev);
Jerome Glisse21f9a4372009-09-11 15:55:33 +02002907extern int radeon_modeset_init(struct radeon_device *rdev);
2908extern void radeon_modeset_fini(struct radeon_device *rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02002909extern bool radeon_card_posted(struct radeon_device *rdev);
Alex Deucherf47299c2010-03-16 20:54:38 -04002910extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
Alex Deucherf46c0122010-03-31 00:33:27 -04002911extern void radeon_update_display_priority(struct radeon_device *rdev);
Dave Airlie72542d72009-12-01 14:06:31 +10002912extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
Jerome Glisse21f9a4372009-09-11 15:55:33 +02002913extern void radeon_scratch_init(struct radeon_device *rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04002914extern void radeon_wb_fini(struct radeon_device *rdev);
2915extern int radeon_wb_init(struct radeon_device *rdev);
2916extern void radeon_wb_disable(struct radeon_device *rdev);
Jerome Glisse21f9a4372009-09-11 15:55:33 +02002917extern void radeon_surface_init(struct radeon_device *rdev);
2918extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
Jerome Glisseca6ffc62009-10-01 10:20:52 +02002919extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glissed39c3b82009-09-28 18:34:43 +02002920extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glisse312ea8d2009-12-07 15:52:58 +01002921extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
Jerome Glissed03d8582009-12-14 21:02:09 +01002922extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
Christian Königf72a113a2014-08-07 09:36:00 +02002923extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2924 uint32_t flags);
2925extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2926extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
Jerome Glissed594e462010-02-17 21:54:29 +00002927extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2928extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
Dave Airlie10ebc0b2012-09-17 14:40:31 +10002929extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2930extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
Dave Airlie53595332011-03-14 09:47:24 +10002931extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
Alex Deucher2e1b65f2013-02-26 11:26:51 -05002932extern void radeon_program_register_sequence(struct radeon_device *rdev,
2933 const u32 *registers,
2934 const u32 array_size);
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02002935
Daniel Vetter3574dda2011-02-18 17:59:19 +01002936/*
Jerome Glisse721604a2012-01-05 22:11:05 -05002937 * vm
2938 */
2939int radeon_vm_manager_init(struct radeon_device *rdev);
2940void radeon_vm_manager_fini(struct radeon_device *rdev);
Christian König6d2f2942014-02-20 13:42:17 +01002941int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
Jerome Glisse721604a2012-01-05 22:11:05 -05002942void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
Christian Königdf0af442014-03-03 12:38:08 +01002943struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2944 struct radeon_vm *vm,
2945 struct list_head *head);
Christian Königee60e292012-08-09 16:21:08 +02002946struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2947 struct radeon_vm *vm, int ring);
Christian Königfa688342014-02-20 10:47:05 +01002948void radeon_vm_flush(struct radeon_device *rdev,
2949 struct radeon_vm *vm,
2950 int ring);
Christian Königee60e292012-08-09 16:21:08 +02002951void radeon_vm_fence(struct radeon_device *rdev,
2952 struct radeon_vm *vm,
2953 struct radeon_fence *fence);
Christian Königdce34bf2012-09-17 19:36:18 +02002954uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
Christian König6d2f2942014-02-20 13:42:17 +01002955int radeon_vm_update_page_directory(struct radeon_device *rdev,
2956 struct radeon_vm *vm);
Christian König036bf462014-07-18 08:56:40 +02002957int radeon_vm_clear_freed(struct radeon_device *rdev,
2958 struct radeon_vm *vm);
Christian Könige31ad962014-07-18 09:24:53 +02002959int radeon_vm_clear_invalids(struct radeon_device *rdev,
2960 struct radeon_vm *vm);
Christian König9c57a6b2013-11-25 15:42:11 +01002961int radeon_vm_bo_update(struct radeon_device *rdev,
Christian König036bf462014-07-18 08:56:40 +02002962 struct radeon_bo_va *bo_va,
Christian König9c57a6b2013-11-25 15:42:11 +01002963 struct ttm_mem_reg *mem);
Jerome Glisse721604a2012-01-05 22:11:05 -05002964void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2965 struct radeon_bo *bo);
Christian König421ca7a2012-09-11 16:10:00 +02002966struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2967 struct radeon_bo *bo);
Christian Könige971bd52012-09-11 16:10:04 +02002968struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2969 struct radeon_vm *vm,
2970 struct radeon_bo *bo);
2971int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2972 struct radeon_bo_va *bo_va,
2973 uint64_t offset,
2974 uint32_t flags);
Christian König036bf462014-07-18 08:56:40 +02002975void radeon_vm_bo_rmv(struct radeon_device *rdev,
2976 struct radeon_bo_va *bo_va);
Jerome Glisse721604a2012-01-05 22:11:05 -05002977
Alex Deucherf122c612012-03-30 08:59:57 -04002978/* audio */
2979void r600_audio_update_hdmi(struct work_struct *work);
Alex Deucherb5306022013-07-31 16:51:33 -04002980struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2981struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
Alex Deucher832eafa2014-02-18 11:07:55 -05002982void r600_audio_enable(struct radeon_device *rdev,
2983 struct r600_audio_pin *pin,
Alex Deucherd3d8c142014-09-18 17:26:39 -04002984 u8 enable_mask);
Alex Deucher832eafa2014-02-18 11:07:55 -05002985void dce6_audio_enable(struct radeon_device *rdev,
2986 struct r600_audio_pin *pin,
Alex Deucherd3d8c142014-09-18 17:26:39 -04002987 u8 enable_mask);
Jerome Glisse721604a2012-01-05 22:11:05 -05002988
2989/*
Alex Deucher16cdf042011-10-28 10:30:02 -04002990 * R600 vram scratch functions
2991 */
2992int r600_vram_scratch_init(struct radeon_device *rdev);
2993void r600_vram_scratch_fini(struct radeon_device *rdev);
2994
2995/*
Jerome Glisse285484e2011-12-16 17:03:42 -05002996 * r600 cs checking helper
2997 */
2998unsigned r600_mip_minify(unsigned size, unsigned level);
2999bool r600_fmt_is_valid_color(u32 format);
3000bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
3001int r600_fmt_get_blocksize(u32 format);
3002int r600_fmt_get_nblocksx(u32 format, u32 w);
3003int r600_fmt_get_nblocksy(u32 format, u32 h);
3004
3005/*
Daniel Vetter3574dda2011-02-18 17:59:19 +01003006 * r600 functions used by radeon_encoder.c
3007 */
Rafał Miłecki1b688d02012-04-30 15:44:54 +02003008struct radeon_hdmi_acr {
3009 u32 clock;
3010
3011 int n_32khz;
3012 int cts_32khz;
3013
3014 int n_44_1khz;
3015 int cts_44_1khz;
3016
3017 int n_48khz;
3018 int cts_48khz;
3019
3020};
3021
Rafał Miłeckie55d3e62012-05-06 17:29:44 +02003022extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3023
Alex Deucher416a2bd2012-05-31 19:00:25 -04003024extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3025 u32 tiling_pipe_num,
3026 u32 max_rb_num,
3027 u32 total_max_rb_num,
3028 u32 enabled_rb_mask);
Alex Deucherfe251e22010-03-24 13:36:43 -04003029
Rafał Miłeckie55d3e62012-05-06 17:29:44 +02003030/*
3031 * evergreen functions used by radeon_encoder.c
3032 */
3033
Alex Deucher0af62b02011-01-06 21:19:31 -05003034extern int ni_init_microcode(struct radeon_device *rdev);
Alex Deucher755d8192011-03-02 20:07:34 -05003035extern int ni_mc_load_microcode(struct radeon_device *rdev);
Alex Deucher0af62b02011-01-06 21:19:31 -05003036
Alex Deucherc4917072012-07-31 17:14:35 -04003037/* radeon_acpi.c */
3038#if defined(CONFIG_ACPI)
3039extern int radeon_acpi_init(struct radeon_device *rdev);
3040extern void radeon_acpi_fini(struct radeon_device *rdev);
Alex Deucherdc50ba72013-06-26 00:33:35 -04003041extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3042extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
Alex Deuchere37e6a02013-02-13 15:47:24 -05003043 u8 perf_req, bool advertise);
Alex Deucherdc50ba72013-06-26 00:33:35 -04003044extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
Alex Deucherc4917072012-07-31 17:14:35 -04003045#else
3046static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3047static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3048#endif
Alberto Miloned7a29522010-07-06 11:40:24 -04003049
Ilija Hadzicc38f34b2013-01-02 18:27:41 -05003050int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3051 struct radeon_cs_packet *pkt,
3052 unsigned idx);
Ilija Hadzic9ffb7a62013-01-02 18:27:42 -05003053bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
Ilija Hadzicc3ad63a2013-01-02 18:27:45 -05003054void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3055 struct radeon_cs_packet *pkt);
Ilija Hadzice9716992013-01-02 18:27:46 -05003056int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3057 struct radeon_cs_reloc **cs_reloc,
3058 int nomm);
Ilija Hadzic40592a12013-01-02 18:27:43 -05003059int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3060 uint32_t *vline_start_end,
3061 uint32_t *vline_status);
Ilija Hadzicc38f34b2013-01-02 18:27:41 -05003062
Jerome Glisse4c788672009-11-20 14:29:23 +01003063#include "radeon_object.h"
3064
Jerome Glisse771fe6b2009-06-05 14:42:42 +02003065#endif