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Viresh Kumar07658d92012-04-16 23:57:51 +05301/*
2 * DTS file for all SPEAr13xx SoCs
3 *
Viresh Kumar10d89352012-06-20 12:53:02 -07004 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
Viresh Kumar07658d92012-04-16 23:57:51 +05305 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a9";
25 reg = <0>;
26 next-level-cache = <&L2>;
27 };
28
29 cpu@1 {
30 compatible = "arm,cortex-a9";
31 reg = <1>;
32 next-level-cache = <&L2>;
33 };
34 };
35
36 gic: interrupt-controller@ec801000 {
37 compatible = "arm,cortex-a9-gic";
38 interrupt-controller;
39 #interrupt-cells = <3>;
40 reg = < 0xec801000 0x1000 >,
41 < 0xec800100 0x0100 >;
42 };
43
44 pmu {
45 compatible = "arm,cortex-a9-pmu";
Vipul Kumar Samar465e4f2b2012-07-04 18:52:17 +080046 interrupts = <0 6 0x04
47 0 7 0x04>;
Viresh Kumar07658d92012-04-16 23:57:51 +053048 };
49
50 L2: l2-cache {
51 compatible = "arm,pl310-cache";
52 reg = <0xed000000 0x1000>;
53 cache-unified;
54 cache-level = <2>;
55 };
56
57 memory {
58 name = "memory";
59 device_type = "memory";
60 reg = <0 0x40000000>;
61 };
62
63 chosen {
64 bootargs = "console=ttyAMA0,115200";
65 };
66
Shiraz Hashim8113ba92012-11-10 17:31:01 +053067 cpufreq {
68 compatible = "st,cpufreq-spear";
69 cpufreq_tbl = < 166000
70 200000
71 250000
72 300000
73 400000
74 500000
75 600000 >;
Linus Torvaldsca2a88f2012-12-19 12:47:41 -080076 status = "disabled";
Shiraz Hashim8113ba92012-11-10 17:31:01 +053077 };
78
Viresh Kumar07658d92012-04-16 23:57:51 +053079 ahb {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "simple-bus";
83 ranges = <0x50000000 0x50000000 0x10000000
84 0xb0000000 0xb0000000 0x10000000
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +080085 0xd0000000 0xd0000000 0x02000000
86 0xd8000000 0xd8000000 0x01000000
Viresh Kumar07658d92012-04-16 23:57:51 +053087 0xe0000000 0xe0000000 0x10000000>;
88
89 sdhci@b3000000 {
90 compatible = "st,sdhci-spear";
91 reg = <0xb3000000 0x100>;
92 interrupts = <0 28 0x4>;
93 status = "disabled";
94 };
95
96 cf@b2800000 {
97 compatible = "arasan,cf-spear1340";
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +080098 reg = <0xb2800000 0x1000>;
Viresh Kumar07658d92012-04-16 23:57:51 +053099 interrupts = <0 29 0x4>;
100 status = "disabled";
101 };
102
103 dma@ea800000 {
104 compatible = "snps,dma-spear1340";
105 reg = <0xea800000 0x1000>;
106 interrupts = <0 19 0x4>;
107 status = "disabled";
108 };
109
110 dma@eb000000 {
111 compatible = "snps,dma-spear1340";
112 reg = <0xeb000000 0x1000>;
113 interrupts = <0 59 0x4>;
114 status = "disabled";
115 };
116
117 fsmc: flash@b0000000 {
118 compatible = "st,spear600-fsmc-nand";
119 #address-cells = <1>;
120 #size-cells = <1>;
Jean-Christophe PLAGNIOL-VILLARD6d7b42a2012-10-04 15:14:16 +0200121 reg = <0xb0000000 0x1000 /* FSMC Register*/
122 0xb0800000 0x0010 /* NAND Base DATA */
123 0xb0820000 0x0010 /* NAND Base ADDR */
124 0xb0810000 0x0010>; /* NAND Base CMD */
125 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
Viresh Kumar07658d92012-04-16 23:57:51 +0530126 interrupts = <0 20 0x4
127 0 21 0x4
128 0 22 0x4
129 0 23 0x4>;
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800130 st,mode = <2>;
Viresh Kumar07658d92012-04-16 23:57:51 +0530131 status = "disabled";
132 };
133
134 gmac0: eth@e2000000 {
135 compatible = "st,spear600-gmac";
136 reg = <0xe2000000 0x8000>;
Vipul Kumar Samar465e4f2b2012-07-04 18:52:17 +0800137 interrupts = <0 33 0x4
138 0 34 0x4>;
Viresh Kumar07658d92012-04-16 23:57:51 +0530139 interrupt-names = "macirq", "eth_wake_irq";
140 status = "disabled";
141 };
142
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530143 pcm {
144 compatible = "st,pcm-audio";
145 #address-cells = <0>;
146 #size-cells = <0>;
Linus Torvaldsca2a88f2012-12-19 12:47:41 -0800147 status = "disabled";
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530148 };
149
Viresh Kumar07658d92012-04-16 23:57:51 +0530150 smi: flash@ea000000 {
151 compatible = "st,spear600-smi";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 reg = <0xea000000 0x1000>;
155 interrupts = <0 30 0x4>;
156 status = "disabled";
157 };
158
Viresh Kumar07658d92012-04-16 23:57:51 +0530159 ehci@e4800000 {
160 compatible = "st,spear600-ehci", "usb-ehci";
161 reg = <0xe4800000 0x1000>;
162 interrupts = <0 64 0x4>;
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800163 usbh0_id = <0>;
Viresh Kumar07658d92012-04-16 23:57:51 +0530164 status = "disabled";
165 };
166
167 ehci@e5800000 {
168 compatible = "st,spear600-ehci", "usb-ehci";
169 reg = <0xe5800000 0x1000>;
170 interrupts = <0 66 0x4>;
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800171 usbh1_id = <1>;
Viresh Kumar07658d92012-04-16 23:57:51 +0530172 status = "disabled";
173 };
174
175 ohci@e4000000 {
176 compatible = "st,spear600-ohci", "usb-ohci";
177 reg = <0xe4000000 0x1000>;
178 interrupts = <0 65 0x4>;
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800179 usbh0_id = <0>;
Viresh Kumar07658d92012-04-16 23:57:51 +0530180 status = "disabled";
181 };
182
183 ohci@e5000000 {
184 compatible = "st,spear600-ohci", "usb-ohci";
185 reg = <0xe5000000 0x1000>;
186 interrupts = <0 67 0x4>;
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800187 usbh1_id = <1>;
Viresh Kumar07658d92012-04-16 23:57:51 +0530188 status = "disabled";
189 };
190
191 apb {
192 #address-cells = <1>;
193 #size-cells = <1>;
194 compatible = "simple-bus";
195 ranges = <0x50000000 0x50000000 0x10000000
196 0xb0000000 0xb0000000 0x10000000
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800197 0xd0000000 0xd0000000 0x02000000
198 0xd8000000 0xd8000000 0x01000000
Viresh Kumar07658d92012-04-16 23:57:51 +0530199 0xe0000000 0xe0000000 0x10000000>;
200
201 gpio0: gpio@e0600000 {
202 compatible = "arm,pl061", "arm,primecell";
203 reg = <0xe0600000 0x1000>;
204 interrupts = <0 24 0x4>;
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 status = "disabled";
210 };
211
212 gpio1: gpio@e0680000 {
213 compatible = "arm,pl061", "arm,primecell";
214 reg = <0xe0680000 0x1000>;
215 interrupts = <0 25 0x4>;
216 gpio-controller;
217 #gpio-cells = <2>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
220 status = "disabled";
221 };
222
223 kbd@e0300000 {
224 compatible = "st,spear300-kbd";
225 reg = <0xe0300000 0x1000>;
Vipul Kumar Samar465e4f2b2012-07-04 18:52:17 +0800226 interrupts = <0 52 0x4>;
Viresh Kumar07658d92012-04-16 23:57:51 +0530227 status = "disabled";
228 };
229
230 i2c0: i2c@e0280000 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "snps,designware-i2c";
234 reg = <0xe0280000 0x1000>;
235 interrupts = <0 41 0x4>;
236 status = "disabled";
237 };
238
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530239 i2s@e0180000 {
240 compatible = "st,designware-i2s";
241 reg = <0xe0180000 0x1000>;
242 interrupt-names = "play_irq", "record_irq";
243 interrupts = <0 10 0x4
244 0 11 0x4 >;
245 status = "disabled";
246 };
247
248 i2s@e0200000 {
249 compatible = "st,designware-i2s";
250 reg = <0xe0200000 0x1000>;
251 interrupt-names = "play_irq", "record_irq";
252 interrupts = <0 26 0x4
253 0 53 0x4>;
254 status = "disabled";
255 };
256
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800257 spi0: spi@e0100000 {
258 compatible = "arm,pl022", "arm,primecell";
259 reg = <0xe0100000 0x1000>;
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530260 #address-cells = <1>;
261 #size-cells = <0>;
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800262 interrupts = <0 31 0x4>;
263 status = "disabled";
264 };
265
Viresh Kumar07658d92012-04-16 23:57:51 +0530266 rtc@e0580000 {
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800267 compatible = "st,spear600-rtc";
Viresh Kumar07658d92012-04-16 23:57:51 +0530268 reg = <0xe0580000 0x1000>;
269 interrupts = <0 36 0x4>;
270 status = "disabled";
271 };
272
273 serial@e0000000 {
274 compatible = "arm,pl011", "arm,primecell";
275 reg = <0xe0000000 0x1000>;
Vipul Kumar Samar465e4f2b2012-07-04 18:52:17 +0800276 interrupts = <0 35 0x4>;
Viresh Kumar07658d92012-04-16 23:57:51 +0530277 status = "disabled";
278 };
279
280 adc@e0080000 {
281 compatible = "st,spear600-adc";
282 reg = <0xe0080000 0x1000>;
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800283 interrupts = <0 12 0x4>;
Viresh Kumar07658d92012-04-16 23:57:51 +0530284 status = "disabled";
285 };
286
287 timer@e0380000 {
288 compatible = "st,spear-timer";
289 reg = <0xe0380000 0x400>;
290 interrupts = <0 37 0x4>;
291 };
292
293 timer@ec800600 {
294 compatible = "arm,cortex-a9-twd-timer";
295 reg = <0xec800600 0x20>;
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800296 interrupts = <1 13 0x4>;
297 status = "disabled";
Viresh Kumar07658d92012-04-16 23:57:51 +0530298 };
299
300 wdt@ec800620 {
301 compatible = "arm,cortex-a9-twd-wdt";
302 reg = <0xec800620 0x20>;
303 status = "disabled";
304 };
305
306 thermal@e07008c4 {
307 compatible = "st,thermal-spear1340";
308 reg = <0xe07008c4 0x4>;
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800309 thermal_flags = <0x7000>;
Viresh Kumar07658d92012-04-16 23:57:51 +0530310 };
311 };
312 };
313};