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Colin Cross7056d422010-04-22 20:30:13 -07001/*
2 * arch/arm/mach-tegra/cpu-tegra.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/types.h>
24#include <linux/sched.h>
25#include <linux/cpufreq.h>
26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/err.h>
29#include <linux/clk.h>
30#include <linux/io.h>
Colin Cross1eb2ecf2010-08-05 17:40:39 -070031#include <linux/suspend.h>
Colin Cross7056d422010-04-22 20:30:13 -070032
Colin Cross7056d422010-04-22 20:30:13 -070033
Colin Cross7056d422010-04-22 20:30:13 -070034#include <mach/clk.h>
35
36/* Frequency table index must be sequential starting at 0 */
37static struct cpufreq_frequency_table freq_table[] = {
Colin Cross1eb2ecf2010-08-05 17:40:39 -070038 { 0, 216000 },
39 { 1, 312000 },
40 { 2, 456000 },
41 { 3, 608000 },
42 { 4, 760000 },
43 { 5, 816000 },
44 { 6, 912000 },
45 { 7, 1000000 },
46 { 8, CPUFREQ_TABLE_END },
Colin Cross7056d422010-04-22 20:30:13 -070047};
48
49#define NUM_CPUS 2
50
51static struct clk *cpu_clk;
Stephen Warrence32dda2012-09-10 17:05:01 -060052static struct clk *pll_x_clk;
53static struct clk *pll_p_clk;
Colin Cross7a281282010-11-22 18:54:36 -080054static struct clk *emc_clk;
Colin Cross7056d422010-04-22 20:30:13 -070055
56static unsigned long target_cpu_speed[NUM_CPUS];
Colin Cross1eb2ecf2010-08-05 17:40:39 -070057static DEFINE_MUTEX(tegra_cpu_lock);
58static bool is_suspended;
Colin Cross7056d422010-04-22 20:30:13 -070059
Olof Johansson6686c732011-10-09 21:57:04 -070060static int tegra_verify_speed(struct cpufreq_policy *policy)
Colin Cross7056d422010-04-22 20:30:13 -070061{
62 return cpufreq_frequency_table_verify(policy, freq_table);
63}
64
Olof Johansson6686c732011-10-09 21:57:04 -070065static unsigned int tegra_getspeed(unsigned int cpu)
Colin Cross7056d422010-04-22 20:30:13 -070066{
67 unsigned long rate;
68
69 if (cpu >= NUM_CPUS)
70 return 0;
71
72 rate = clk_get_rate(cpu_clk) / 1000;
73 return rate;
74}
75
Stephen Warrence32dda2012-09-10 17:05:01 -060076static int tegra_cpu_clk_set_rate(unsigned long rate)
77{
78 int ret;
79
80 /*
81 * Take an extra reference to the main pll so it doesn't turn
82 * off when we move the cpu off of it
83 */
84 clk_prepare_enable(pll_x_clk);
85
86 ret = clk_set_parent(cpu_clk, pll_p_clk);
87 if (ret) {
88 pr_err("Failed to switch cpu to clock pll_p\n");
89 goto out;
90 }
91
92 if (rate == clk_get_rate(pll_p_clk))
93 goto out;
94
95 ret = clk_set_rate(pll_x_clk, rate);
96 if (ret) {
97 pr_err("Failed to change pll_x to %lu\n", rate);
98 goto out;
99 }
100
101 ret = clk_set_parent(cpu_clk, pll_x_clk);
102 if (ret) {
103 pr_err("Failed to switch cpu to clock pll_x\n");
104 goto out;
105 }
106
107out:
108 clk_disable_unprepare(pll_x_clk);
109 return ret;
110}
111
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700112static int tegra_update_cpu_speed(unsigned long rate)
Colin Cross7056d422010-04-22 20:30:13 -0700113{
Colin Cross7056d422010-04-22 20:30:13 -0700114 int ret = 0;
115 struct cpufreq_freqs freqs;
116
Colin Cross7056d422010-04-22 20:30:13 -0700117 freqs.old = tegra_getspeed(0);
118 freqs.new = rate;
119
120 if (freqs.old == freqs.new)
121 return ret;
122
Colin Cross7a281282010-11-22 18:54:36 -0800123 /*
124 * Vote on memory bus frequency based on cpu frequency
125 * This sets the minimum frequency, display or avp may request higher
126 */
127 if (rate >= 816000)
128 clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
129 else if (rate >= 456000)
130 clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
131 else
132 clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
133
Colin Cross7056d422010-04-22 20:30:13 -0700134 for_each_online_cpu(freqs.cpu)
135 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
136
137#ifdef CONFIG_CPU_FREQ_DEBUG
138 printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
139 freqs.old, freqs.new);
140#endif
141
Stephen Warrence32dda2012-09-10 17:05:01 -0600142 ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
Colin Cross7056d422010-04-22 20:30:13 -0700143 if (ret) {
144 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
145 freqs.new);
146 return ret;
147 }
148
149 for_each_online_cpu(freqs.cpu)
150 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
151
152 return 0;
153}
154
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700155static unsigned long tegra_cpu_highest_speed(void)
156{
157 unsigned long rate = 0;
158 int i;
159
160 for_each_online_cpu(i)
161 rate = max(rate, target_cpu_speed[i]);
162 return rate;
163}
164
Colin Cross7056d422010-04-22 20:30:13 -0700165static int tegra_target(struct cpufreq_policy *policy,
166 unsigned int target_freq,
167 unsigned int relation)
168{
Olof Johanssonfdb684a2011-10-09 21:31:23 -0700169 unsigned int idx;
Colin Cross7056d422010-04-22 20:30:13 -0700170 unsigned int freq;
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700171 int ret = 0;
172
173 mutex_lock(&tegra_cpu_lock);
174
175 if (is_suspended) {
176 ret = -EBUSY;
177 goto out;
178 }
Colin Cross7056d422010-04-22 20:30:13 -0700179
180 cpufreq_frequency_table_target(policy, freq_table, target_freq,
181 relation, &idx);
182
183 freq = freq_table[idx].frequency;
184
185 target_cpu_speed[policy->cpu] = freq;
186
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700187 ret = tegra_update_cpu_speed(tegra_cpu_highest_speed());
188
189out:
190 mutex_unlock(&tegra_cpu_lock);
191 return ret;
Colin Cross7056d422010-04-22 20:30:13 -0700192}
193
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700194static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
195 void *dummy)
196{
197 mutex_lock(&tegra_cpu_lock);
198 if (event == PM_SUSPEND_PREPARE) {
199 is_suspended = true;
200 pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
201 freq_table[0].frequency);
202 tegra_update_cpu_speed(freq_table[0].frequency);
203 } else if (event == PM_POST_SUSPEND) {
204 is_suspended = false;
205 }
206 mutex_unlock(&tegra_cpu_lock);
207
208 return NOTIFY_OK;
209}
210
211static struct notifier_block tegra_cpu_pm_notifier = {
212 .notifier_call = tegra_pm_notify,
213};
214
Colin Cross7056d422010-04-22 20:30:13 -0700215static int tegra_cpu_init(struct cpufreq_policy *policy)
216{
217 if (policy->cpu >= NUM_CPUS)
218 return -EINVAL;
219
220 cpu_clk = clk_get_sys(NULL, "cpu");
221 if (IS_ERR(cpu_clk))
222 return PTR_ERR(cpu_clk);
223
Stephen Warrence32dda2012-09-10 17:05:01 -0600224 pll_x_clk = clk_get_sys(NULL, "pll_x");
225 if (IS_ERR(pll_x_clk))
226 return PTR_ERR(pll_x_clk);
227
228 pll_p_clk = clk_get_sys(NULL, "pll_p");
229 if (IS_ERR(pll_p_clk))
230 return PTR_ERR(pll_p_clk);
231
Colin Cross7a281282010-11-22 18:54:36 -0800232 emc_clk = clk_get_sys("cpu", "emc");
233 if (IS_ERR(emc_clk)) {
234 clk_put(cpu_clk);
235 return PTR_ERR(emc_clk);
236 }
237
Prashant Gaikwad6a5278d2012-06-05 09:59:35 +0530238 clk_prepare_enable(emc_clk);
239 clk_prepare_enable(cpu_clk);
Colin Cross89a5fb82010-10-20 17:47:59 -0700240
Colin Cross7056d422010-04-22 20:30:13 -0700241 cpufreq_frequency_table_cpuinfo(policy, freq_table);
242 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
243 policy->cur = tegra_getspeed(policy->cpu);
244 target_cpu_speed[policy->cpu] = policy->cur;
245
246 /* FIXME: what's the actual transition time? */
247 policy->cpuinfo.transition_latency = 300 * 1000;
248
249 policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
250 cpumask_copy(policy->related_cpus, cpu_possible_mask);
251
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700252 if (policy->cpu == 0)
253 register_pm_notifier(&tegra_cpu_pm_notifier);
254
Colin Cross7056d422010-04-22 20:30:13 -0700255 return 0;
256}
257
258static int tegra_cpu_exit(struct cpufreq_policy *policy)
259{
260 cpufreq_frequency_table_cpuinfo(policy, freq_table);
Prashant Gaikwad6a5278d2012-06-05 09:59:35 +0530261 clk_disable_unprepare(emc_clk);
Colin Cross7a281282010-11-22 18:54:36 -0800262 clk_put(emc_clk);
Colin Cross7056d422010-04-22 20:30:13 -0700263 clk_put(cpu_clk);
264 return 0;
265}
266
267static struct freq_attr *tegra_cpufreq_attr[] = {
268 &cpufreq_freq_attr_scaling_available_freqs,
269 NULL,
270};
271
272static struct cpufreq_driver tegra_cpufreq_driver = {
273 .verify = tegra_verify_speed,
274 .target = tegra_target,
275 .get = tegra_getspeed,
276 .init = tegra_cpu_init,
277 .exit = tegra_cpu_exit,
278 .name = "tegra",
279 .attr = tegra_cpufreq_attr,
280};
281
282static int __init tegra_cpufreq_init(void)
283{
284 return cpufreq_register_driver(&tegra_cpufreq_driver);
285}
286
287static void __exit tegra_cpufreq_exit(void)
288{
289 cpufreq_unregister_driver(&tegra_cpufreq_driver);
290}
291
292
293MODULE_AUTHOR("Colin Cross <ccross@android.com>");
294MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
295MODULE_LICENSE("GPL");
296module_init(tegra_cpufreq_init);
297module_exit(tegra_cpufreq_exit);