Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel(R) Gigabit Ethernet Linux driver |
Alexander Duyck | 86d5d38 | 2009-02-06 23:23:12 +0000 | [diff] [blame] | 4 | Copyright(c) 2007-2009 Intel Corporation. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include <linux/if_ether.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/pci.h> |
| 31 | #include <linux/netdevice.h> |
| 32 | |
| 33 | #include "e1000_mac.h" |
| 34 | |
| 35 | #include "igb.h" |
| 36 | |
| 37 | static s32 igb_set_default_fc(struct e1000_hw *hw); |
| 38 | static s32 igb_set_fc_watermarks(struct e1000_hw *hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 39 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 40 | static s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
| 41 | { |
| 42 | struct igb_adapter *adapter = hw->back; |
| 43 | u16 cap_offset; |
| 44 | |
| 45 | cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); |
| 46 | if (!cap_offset) |
| 47 | return -E1000_ERR_CONFIG; |
| 48 | |
| 49 | pci_read_config_word(adapter->pdev, cap_offset + reg, value); |
| 50 | |
| 51 | return 0; |
| 52 | } |
| 53 | |
| 54 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 55 | * igb_get_bus_info_pcie - Get PCIe bus information |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 56 | * @hw: pointer to the HW structure |
| 57 | * |
| 58 | * Determines and stores the system bus information for a particular |
| 59 | * network interface. The following bus information is determined and stored: |
| 60 | * bus speed, bus width, type (PCIe), and PCIe function. |
| 61 | **/ |
| 62 | s32 igb_get_bus_info_pcie(struct e1000_hw *hw) |
| 63 | { |
| 64 | struct e1000_bus_info *bus = &hw->bus; |
| 65 | s32 ret_val; |
Alexander Duyck | 5e8427e | 2008-12-10 01:09:53 -0800 | [diff] [blame] | 66 | u32 reg; |
| 67 | u16 pcie_link_status; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 68 | |
| 69 | bus->type = e1000_bus_type_pci_express; |
| 70 | bus->speed = e1000_bus_speed_2500; |
| 71 | |
| 72 | ret_val = igb_read_pcie_cap_reg(hw, |
| 73 | PCIE_LINK_STATUS, |
| 74 | &pcie_link_status); |
| 75 | if (ret_val) |
| 76 | bus->width = e1000_bus_width_unknown; |
| 77 | else |
| 78 | bus->width = (enum e1000_bus_width)((pcie_link_status & |
| 79 | PCIE_LINK_WIDTH_MASK) >> |
| 80 | PCIE_LINK_WIDTH_SHIFT); |
| 81 | |
Alexander Duyck | 5e8427e | 2008-12-10 01:09:53 -0800 | [diff] [blame] | 82 | reg = rd32(E1000_STATUS); |
| 83 | bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 89 | * igb_clear_vfta - Clear VLAN filter table |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 90 | * @hw: pointer to the HW structure |
| 91 | * |
| 92 | * Clears the register array which contains the VLAN filter table by |
| 93 | * setting all the values to 0. |
| 94 | **/ |
| 95 | void igb_clear_vfta(struct e1000_hw *hw) |
| 96 | { |
| 97 | u32 offset; |
| 98 | |
| 99 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
| 100 | array_wr32(E1000_VFTA, offset, 0); |
| 101 | wrfl(); |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 106 | * igb_write_vfta - Write value to VLAN filter table |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 107 | * @hw: pointer to the HW structure |
| 108 | * @offset: register offset in VLAN filter table |
| 109 | * @value: register value written to VLAN filter table |
| 110 | * |
| 111 | * Writes value at the given offset in the register array which stores |
| 112 | * the VLAN filter table. |
| 113 | **/ |
| 114 | void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) |
| 115 | { |
| 116 | array_wr32(E1000_VFTA, offset, value); |
| 117 | wrfl(); |
| 118 | } |
| 119 | |
| 120 | /** |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 121 | * igb_vfta_set - enable or disable vlan in VLAN filter table |
| 122 | * @hw: pointer to the HW structure |
| 123 | * @vid: VLAN id to add or remove |
| 124 | * @add: if true add filter, if false remove |
| 125 | * |
| 126 | * Sets or clears a bit in the VLAN filter table array based on VLAN id |
| 127 | * and if we are adding or removing the filter |
| 128 | **/ |
Alexander Duyck | cad6d05 | 2009-03-13 20:41:37 +0000 | [diff] [blame^] | 129 | s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add) |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 130 | { |
| 131 | u32 index = (vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; |
| 132 | u32 mask = 1 < (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK); |
Alexander Duyck | cad6d05 | 2009-03-13 20:41:37 +0000 | [diff] [blame^] | 133 | u32 vfta = array_rd32(E1000_VFTA, index); |
| 134 | s32 ret_val = 0; |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 135 | |
Alexander Duyck | cad6d05 | 2009-03-13 20:41:37 +0000 | [diff] [blame^] | 136 | /* bit was set/cleared before we started */ |
| 137 | if ((!!(vfta & mask)) == add) { |
| 138 | ret_val = -E1000_ERR_CONFIG; |
| 139 | } else { |
| 140 | if (add) |
| 141 | vfta |= mask; |
| 142 | else |
| 143 | vfta &= ~mask; |
| 144 | } |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 145 | |
| 146 | igb_write_vfta(hw, index, vfta); |
Alexander Duyck | cad6d05 | 2009-03-13 20:41:37 +0000 | [diff] [blame^] | 147 | |
| 148 | return ret_val; |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 152 | * igb_check_alt_mac_addr - Check for alternate MAC addr |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 153 | * @hw: pointer to the HW structure |
| 154 | * |
| 155 | * Checks the nvm for an alternate MAC address. An alternate MAC address |
| 156 | * can be setup by pre-boot software and must be treated like a permanent |
| 157 | * address and must override the actual permanent MAC address. If an |
| 158 | * alternate MAC address is fopund it is saved in the hw struct and |
| 159 | * prgrammed into RAR0 and the cuntion returns success, otherwise the |
| 160 | * fucntion returns an error. |
| 161 | **/ |
| 162 | s32 igb_check_alt_mac_addr(struct e1000_hw *hw) |
| 163 | { |
| 164 | u32 i; |
| 165 | s32 ret_val = 0; |
| 166 | u16 offset, nvm_alt_mac_addr_offset, nvm_data; |
| 167 | u8 alt_mac_addr[ETH_ALEN]; |
| 168 | |
Alexander Duyck | 312c75a | 2009-02-06 23:17:47 +0000 | [diff] [blame] | 169 | ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 170 | &nvm_alt_mac_addr_offset); |
| 171 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 172 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 173 | goto out; |
| 174 | } |
| 175 | |
| 176 | if (nvm_alt_mac_addr_offset == 0xFFFF) { |
| 177 | ret_val = -(E1000_NOT_IMPLEMENTED); |
| 178 | goto out; |
| 179 | } |
| 180 | |
| 181 | if (hw->bus.func == E1000_FUNC_1) |
| 182 | nvm_alt_mac_addr_offset += ETH_ALEN/sizeof(u16); |
| 183 | |
| 184 | for (i = 0; i < ETH_ALEN; i += 2) { |
| 185 | offset = nvm_alt_mac_addr_offset + (i >> 1); |
Alexander Duyck | 312c75a | 2009-02-06 23:17:47 +0000 | [diff] [blame] | 186 | ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 187 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 188 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 189 | goto out; |
| 190 | } |
| 191 | |
| 192 | alt_mac_addr[i] = (u8)(nvm_data & 0xFF); |
| 193 | alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); |
| 194 | } |
| 195 | |
| 196 | /* if multicast bit is set, the alternate address will not be used */ |
| 197 | if (alt_mac_addr[0] & 0x01) { |
| 198 | ret_val = -(E1000_NOT_IMPLEMENTED); |
| 199 | goto out; |
| 200 | } |
| 201 | |
| 202 | for (i = 0; i < ETH_ALEN; i++) |
| 203 | hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i]; |
| 204 | |
| 205 | hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0); |
| 206 | |
| 207 | out: |
| 208 | return ret_val; |
| 209 | } |
| 210 | |
| 211 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 212 | * igb_rar_set - Set receive address register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 213 | * @hw: pointer to the HW structure |
| 214 | * @addr: pointer to the receive address |
| 215 | * @index: receive address array register |
| 216 | * |
| 217 | * Sets the receive address array register at index to the address passed |
| 218 | * in by addr. |
| 219 | **/ |
| 220 | void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) |
| 221 | { |
| 222 | u32 rar_low, rar_high; |
| 223 | |
| 224 | /* |
| 225 | * HW expects these in little endian so we reverse the byte order |
| 226 | * from network order (big endian) to little endian |
| 227 | */ |
| 228 | rar_low = ((u32) addr[0] | |
| 229 | ((u32) addr[1] << 8) | |
| 230 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); |
| 231 | |
| 232 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
| 233 | |
Alexander Duyck | 8675737 | 2009-02-06 23:21:51 +0000 | [diff] [blame] | 234 | /* If MAC address zero, no need to set the AV bit */ |
| 235 | if (rar_low || rar_high) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 236 | rar_high |= E1000_RAH_AV; |
| 237 | |
Alexander Duyck | 5e8427e | 2008-12-10 01:09:53 -0800 | [diff] [blame] | 238 | wr32(E1000_RAL(index), rar_low); |
| 239 | wr32(E1000_RAH(index), rar_high); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 240 | } |
| 241 | |
| 242 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 243 | * igb_mta_set - Set multicast filter table address |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 244 | * @hw: pointer to the HW structure |
| 245 | * @hash_value: determines the MTA register and bit to set |
| 246 | * |
| 247 | * The multicast table address is a register array of 32-bit registers. |
| 248 | * The hash_value is used to determine what register the bit is in, the |
| 249 | * current value is read, the new bit is OR'd in and the new value is |
| 250 | * written back into the register. |
| 251 | **/ |
Alexander Duyck | 549bdd8 | 2008-08-04 15:00:06 -0700 | [diff] [blame] | 252 | void igb_mta_set(struct e1000_hw *hw, u32 hash_value) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 253 | { |
| 254 | u32 hash_bit, hash_reg, mta; |
| 255 | |
| 256 | /* |
| 257 | * The MTA is a register array of 32-bit registers. It is |
| 258 | * treated like an array of (32*mta_reg_count) bits. We want to |
| 259 | * set bit BitArray[hash_value]. So we figure out what register |
| 260 | * the bit is in, read it, OR in the new bit, then write |
| 261 | * back the new value. The (hw->mac.mta_reg_count - 1) serves as a |
| 262 | * mask to bits 31:5 of the hash value which gives us the |
| 263 | * register we're modifying. The hash bit within that register |
| 264 | * is determined by the lower 5 bits of the hash value. |
| 265 | */ |
| 266 | hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); |
| 267 | hash_bit = hash_value & 0x1F; |
| 268 | |
| 269 | mta = array_rd32(E1000_MTA, hash_reg); |
| 270 | |
| 271 | mta |= (1 << hash_bit); |
| 272 | |
| 273 | array_wr32(E1000_MTA, hash_reg, mta); |
| 274 | wrfl(); |
| 275 | } |
| 276 | |
| 277 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 278 | * igb_hash_mc_addr - Generate a multicast hash value |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 279 | * @hw: pointer to the HW structure |
| 280 | * @mc_addr: pointer to a multicast address |
| 281 | * |
| 282 | * Generates a multicast address hash value which is used to determine |
| 283 | * the multicast filter table array address and new table value. See |
| 284 | * igb_mta_set() |
| 285 | **/ |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 286 | u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 287 | { |
| 288 | u32 hash_value, hash_mask; |
| 289 | u8 bit_shift = 0; |
| 290 | |
| 291 | /* Register count multiplied by bits per register */ |
| 292 | hash_mask = (hw->mac.mta_reg_count * 32) - 1; |
| 293 | |
| 294 | /* |
| 295 | * For a mc_filter_type of 0, bit_shift is the number of left-shifts |
| 296 | * where 0xFF would still fall within the hash mask. |
| 297 | */ |
| 298 | while (hash_mask >> bit_shift != 0xFF) |
| 299 | bit_shift++; |
| 300 | |
| 301 | /* |
| 302 | * The portion of the address that is used for the hash table |
| 303 | * is determined by the mc_filter_type setting. |
| 304 | * The algorithm is such that there is a total of 8 bits of shifting. |
| 305 | * The bit_shift for a mc_filter_type of 0 represents the number of |
| 306 | * left-shifts where the MSB of mc_addr[5] would still fall within |
| 307 | * the hash_mask. Case 0 does this exactly. Since there are a total |
| 308 | * of 8 bits of shifting, then mc_addr[4] will shift right the |
| 309 | * remaining number of bits. Thus 8 - bit_shift. The rest of the |
| 310 | * cases are a variation of this algorithm...essentially raising the |
| 311 | * number of bits to shift mc_addr[5] left, while still keeping the |
| 312 | * 8-bit shifting total. |
| 313 | * |
| 314 | * For example, given the following Destination MAC Address and an |
| 315 | * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), |
| 316 | * we can see that the bit_shift for case 0 is 4. These are the hash |
| 317 | * values resulting from each mc_filter_type... |
| 318 | * [0] [1] [2] [3] [4] [5] |
| 319 | * 01 AA 00 12 34 56 |
| 320 | * LSB MSB |
| 321 | * |
| 322 | * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 |
| 323 | * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 |
| 324 | * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 |
| 325 | * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 |
| 326 | */ |
| 327 | switch (hw->mac.mc_filter_type) { |
| 328 | default: |
| 329 | case 0: |
| 330 | break; |
| 331 | case 1: |
| 332 | bit_shift += 1; |
| 333 | break; |
| 334 | case 2: |
| 335 | bit_shift += 2; |
| 336 | break; |
| 337 | case 3: |
| 338 | bit_shift += 4; |
| 339 | break; |
| 340 | } |
| 341 | |
| 342 | hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | |
| 343 | (((u16) mc_addr[5]) << bit_shift))); |
| 344 | |
| 345 | return hash_value; |
| 346 | } |
| 347 | |
| 348 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 349 | * igb_clear_hw_cntrs_base - Clear base hardware counters |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 350 | * @hw: pointer to the HW structure |
| 351 | * |
| 352 | * Clears the base hardware counters by reading the counter registers. |
| 353 | **/ |
| 354 | void igb_clear_hw_cntrs_base(struct e1000_hw *hw) |
| 355 | { |
| 356 | u32 temp; |
| 357 | |
| 358 | temp = rd32(E1000_CRCERRS); |
| 359 | temp = rd32(E1000_SYMERRS); |
| 360 | temp = rd32(E1000_MPC); |
| 361 | temp = rd32(E1000_SCC); |
| 362 | temp = rd32(E1000_ECOL); |
| 363 | temp = rd32(E1000_MCC); |
| 364 | temp = rd32(E1000_LATECOL); |
| 365 | temp = rd32(E1000_COLC); |
| 366 | temp = rd32(E1000_DC); |
| 367 | temp = rd32(E1000_SEC); |
| 368 | temp = rd32(E1000_RLEC); |
| 369 | temp = rd32(E1000_XONRXC); |
| 370 | temp = rd32(E1000_XONTXC); |
| 371 | temp = rd32(E1000_XOFFRXC); |
| 372 | temp = rd32(E1000_XOFFTXC); |
| 373 | temp = rd32(E1000_FCRUC); |
| 374 | temp = rd32(E1000_GPRC); |
| 375 | temp = rd32(E1000_BPRC); |
| 376 | temp = rd32(E1000_MPRC); |
| 377 | temp = rd32(E1000_GPTC); |
| 378 | temp = rd32(E1000_GORCL); |
| 379 | temp = rd32(E1000_GORCH); |
| 380 | temp = rd32(E1000_GOTCL); |
| 381 | temp = rd32(E1000_GOTCH); |
| 382 | temp = rd32(E1000_RNBC); |
| 383 | temp = rd32(E1000_RUC); |
| 384 | temp = rd32(E1000_RFC); |
| 385 | temp = rd32(E1000_ROC); |
| 386 | temp = rd32(E1000_RJC); |
| 387 | temp = rd32(E1000_TORL); |
| 388 | temp = rd32(E1000_TORH); |
| 389 | temp = rd32(E1000_TOTL); |
| 390 | temp = rd32(E1000_TOTH); |
| 391 | temp = rd32(E1000_TPR); |
| 392 | temp = rd32(E1000_TPT); |
| 393 | temp = rd32(E1000_MPTC); |
| 394 | temp = rd32(E1000_BPTC); |
| 395 | } |
| 396 | |
| 397 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 398 | * igb_check_for_copper_link - Check for link (Copper) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 399 | * @hw: pointer to the HW structure |
| 400 | * |
| 401 | * Checks to see of the link status of the hardware has changed. If a |
| 402 | * change in link status has been detected, then we read the PHY registers |
| 403 | * to get the current speed/duplex if link exists. |
| 404 | **/ |
| 405 | s32 igb_check_for_copper_link(struct e1000_hw *hw) |
| 406 | { |
| 407 | struct e1000_mac_info *mac = &hw->mac; |
| 408 | s32 ret_val; |
| 409 | bool link; |
| 410 | |
| 411 | /* |
| 412 | * We only want to go out to the PHY registers to see if Auto-Neg |
| 413 | * has completed and/or if our link status has changed. The |
| 414 | * get_link_status flag is set upon receiving a Link Status |
| 415 | * Change or Rx Sequence Error interrupt. |
| 416 | */ |
| 417 | if (!mac->get_link_status) { |
| 418 | ret_val = 0; |
| 419 | goto out; |
| 420 | } |
| 421 | |
| 422 | /* |
| 423 | * First we want to see if the MII Status Register reports |
| 424 | * link. If so, then we want to get the current speed/duplex |
| 425 | * of the PHY. |
| 426 | */ |
| 427 | ret_val = igb_phy_has_link(hw, 1, 0, &link); |
| 428 | if (ret_val) |
| 429 | goto out; |
| 430 | |
| 431 | if (!link) |
| 432 | goto out; /* No link detected */ |
| 433 | |
| 434 | mac->get_link_status = false; |
| 435 | |
| 436 | /* |
| 437 | * Check if there was DownShift, must be checked |
| 438 | * immediately after link-up |
| 439 | */ |
| 440 | igb_check_downshift(hw); |
| 441 | |
| 442 | /* |
| 443 | * If we are forcing speed/duplex, then we simply return since |
| 444 | * we have already determined whether we have link or not. |
| 445 | */ |
| 446 | if (!mac->autoneg) { |
| 447 | ret_val = -E1000_ERR_CONFIG; |
| 448 | goto out; |
| 449 | } |
| 450 | |
| 451 | /* |
| 452 | * Auto-Neg is enabled. Auto Speed Detection takes care |
| 453 | * of MAC speed/duplex configuration. So we only need to |
| 454 | * configure Collision Distance in the MAC. |
| 455 | */ |
| 456 | igb_config_collision_dist(hw); |
| 457 | |
| 458 | /* |
| 459 | * Configure Flow Control now that Auto-Neg has completed. |
| 460 | * First, we need to restore the desired flow control |
| 461 | * settings because we may have had to re-autoneg with a |
| 462 | * different link partner. |
| 463 | */ |
| 464 | ret_val = igb_config_fc_after_link_up(hw); |
| 465 | if (ret_val) |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 466 | hw_dbg("Error configuring flow control\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 467 | |
| 468 | out: |
| 469 | return ret_val; |
| 470 | } |
| 471 | |
| 472 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 473 | * igb_setup_link - Setup flow control and link settings |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 474 | * @hw: pointer to the HW structure |
| 475 | * |
| 476 | * Determines which flow control settings to use, then configures flow |
| 477 | * control. Calls the appropriate media-specific link configuration |
| 478 | * function. Assuming the adapter has a valid link partner, a valid link |
| 479 | * should be established. Assumes the hardware has previously been reset |
| 480 | * and the transmitter and receiver are not enabled. |
| 481 | **/ |
| 482 | s32 igb_setup_link(struct e1000_hw *hw) |
| 483 | { |
| 484 | s32 ret_val = 0; |
| 485 | |
| 486 | /* |
| 487 | * In the case of the phy reset being blocked, we already have a link. |
| 488 | * We do not need to set it up again. |
| 489 | */ |
| 490 | if (igb_check_reset_block(hw)) |
| 491 | goto out; |
| 492 | |
| 493 | ret_val = igb_set_default_fc(hw); |
| 494 | if (ret_val) |
| 495 | goto out; |
| 496 | |
| 497 | /* |
| 498 | * We want to save off the original Flow Control configuration just |
| 499 | * in case we get disconnected and then reconnected into a different |
| 500 | * hub or switch with different Flow Control capabilities. |
| 501 | */ |
| 502 | hw->fc.original_type = hw->fc.type; |
| 503 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 504 | hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.type); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 505 | |
| 506 | /* Call the necessary media_type subroutine to configure the link. */ |
| 507 | ret_val = hw->mac.ops.setup_physical_interface(hw); |
| 508 | if (ret_val) |
| 509 | goto out; |
| 510 | |
| 511 | /* |
| 512 | * Initialize the flow control address, type, and PAUSE timer |
| 513 | * registers to their default values. This is done even if flow |
| 514 | * control is disabled, because it does not hurt anything to |
| 515 | * initialize these registers. |
| 516 | */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 517 | hw_dbg("Initializing the Flow Control address, type and timer regs\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 518 | wr32(E1000_FCT, FLOW_CONTROL_TYPE); |
| 519 | wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
| 520 | wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); |
| 521 | |
| 522 | wr32(E1000_FCTTV, hw->fc.pause_time); |
| 523 | |
| 524 | ret_val = igb_set_fc_watermarks(hw); |
| 525 | |
| 526 | out: |
| 527 | return ret_val; |
| 528 | } |
| 529 | |
| 530 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 531 | * igb_config_collision_dist - Configure collision distance |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 532 | * @hw: pointer to the HW structure |
| 533 | * |
| 534 | * Configures the collision distance to the default value and is used |
| 535 | * during link setup. Currently no func pointer exists and all |
| 536 | * implementations are handled in the generic version of this function. |
| 537 | **/ |
| 538 | void igb_config_collision_dist(struct e1000_hw *hw) |
| 539 | { |
| 540 | u32 tctl; |
| 541 | |
| 542 | tctl = rd32(E1000_TCTL); |
| 543 | |
| 544 | tctl &= ~E1000_TCTL_COLD; |
| 545 | tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; |
| 546 | |
| 547 | wr32(E1000_TCTL, tctl); |
| 548 | wrfl(); |
| 549 | } |
| 550 | |
| 551 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 552 | * igb_set_fc_watermarks - Set flow control high/low watermarks |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 553 | * @hw: pointer to the HW structure |
| 554 | * |
| 555 | * Sets the flow control high/low threshold (watermark) registers. If |
| 556 | * flow control XON frame transmission is enabled, then set XON frame |
| 557 | * tansmission as well. |
| 558 | **/ |
| 559 | static s32 igb_set_fc_watermarks(struct e1000_hw *hw) |
| 560 | { |
| 561 | s32 ret_val = 0; |
| 562 | u32 fcrtl = 0, fcrth = 0; |
| 563 | |
| 564 | /* |
| 565 | * Set the flow control receive threshold registers. Normally, |
| 566 | * these registers will be set to a default threshold that may be |
| 567 | * adjusted later by the driver's runtime code. However, if the |
| 568 | * ability to transmit pause frames is not enabled, then these |
| 569 | * registers will be set to 0. |
| 570 | */ |
| 571 | if (hw->fc.type & e1000_fc_tx_pause) { |
| 572 | /* |
| 573 | * We need to set up the Receive Threshold high and low water |
| 574 | * marks as well as (optionally) enabling the transmission of |
| 575 | * XON frames. |
| 576 | */ |
| 577 | fcrtl = hw->fc.low_water; |
| 578 | if (hw->fc.send_xon) |
| 579 | fcrtl |= E1000_FCRTL_XONE; |
| 580 | |
| 581 | fcrth = hw->fc.high_water; |
| 582 | } |
| 583 | wr32(E1000_FCRTL, fcrtl); |
| 584 | wr32(E1000_FCRTH, fcrth); |
| 585 | |
| 586 | return ret_val; |
| 587 | } |
| 588 | |
| 589 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 590 | * igb_set_default_fc - Set flow control default values |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 591 | * @hw: pointer to the HW structure |
| 592 | * |
| 593 | * Read the EEPROM for the default values for flow control and store the |
| 594 | * values. |
| 595 | **/ |
| 596 | static s32 igb_set_default_fc(struct e1000_hw *hw) |
| 597 | { |
| 598 | s32 ret_val = 0; |
| 599 | u16 nvm_data; |
| 600 | |
| 601 | /* |
| 602 | * Read and store word 0x0F of the EEPROM. This word contains bits |
| 603 | * that determine the hardware's default PAUSE (flow control) mode, |
| 604 | * a bit that determines whether the HW defaults to enabling or |
| 605 | * disabling auto-negotiation, and the direction of the |
| 606 | * SW defined pins. If there is no SW over-ride of the flow |
| 607 | * control setting, then the variable hw->fc will |
| 608 | * be initialized based on a value in the EEPROM. |
| 609 | */ |
Alexander Duyck | 312c75a | 2009-02-06 23:17:47 +0000 | [diff] [blame] | 610 | ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 611 | |
| 612 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 613 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 614 | goto out; |
| 615 | } |
| 616 | |
| 617 | if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) |
| 618 | hw->fc.type = e1000_fc_none; |
| 619 | else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == |
| 620 | NVM_WORD0F_ASM_DIR) |
| 621 | hw->fc.type = e1000_fc_tx_pause; |
| 622 | else |
| 623 | hw->fc.type = e1000_fc_full; |
| 624 | |
| 625 | out: |
| 626 | return ret_val; |
| 627 | } |
| 628 | |
| 629 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 630 | * igb_force_mac_fc - Force the MAC's flow control settings |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 631 | * @hw: pointer to the HW structure |
| 632 | * |
| 633 | * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the |
| 634 | * device control register to reflect the adapter settings. TFCE and RFCE |
| 635 | * need to be explicitly set by software when a copper PHY is used because |
| 636 | * autonegotiation is managed by the PHY rather than the MAC. Software must |
| 637 | * also configure these bits when link is forced on a fiber connection. |
| 638 | **/ |
| 639 | s32 igb_force_mac_fc(struct e1000_hw *hw) |
| 640 | { |
| 641 | u32 ctrl; |
| 642 | s32 ret_val = 0; |
| 643 | |
| 644 | ctrl = rd32(E1000_CTRL); |
| 645 | |
| 646 | /* |
| 647 | * Because we didn't get link via the internal auto-negotiation |
| 648 | * mechanism (we either forced link or we got link via PHY |
| 649 | * auto-neg), we have to manually enable/disable transmit an |
| 650 | * receive flow control. |
| 651 | * |
| 652 | * The "Case" statement below enables/disable flow control |
| 653 | * according to the "hw->fc.type" parameter. |
| 654 | * |
| 655 | * The possible values of the "fc" parameter are: |
| 656 | * 0: Flow control is completely disabled |
| 657 | * 1: Rx flow control is enabled (we can receive pause |
| 658 | * frames but not send pause frames). |
| 659 | * 2: Tx flow control is enabled (we can send pause frames |
| 660 | * frames but we do not receive pause frames). |
| 661 | * 3: Both Rx and TX flow control (symmetric) is enabled. |
| 662 | * other: No other values should be possible at this point. |
| 663 | */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 664 | hw_dbg("hw->fc.type = %u\n", hw->fc.type); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 665 | |
| 666 | switch (hw->fc.type) { |
| 667 | case e1000_fc_none: |
| 668 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
| 669 | break; |
| 670 | case e1000_fc_rx_pause: |
| 671 | ctrl &= (~E1000_CTRL_TFCE); |
| 672 | ctrl |= E1000_CTRL_RFCE; |
| 673 | break; |
| 674 | case e1000_fc_tx_pause: |
| 675 | ctrl &= (~E1000_CTRL_RFCE); |
| 676 | ctrl |= E1000_CTRL_TFCE; |
| 677 | break; |
| 678 | case e1000_fc_full: |
| 679 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
| 680 | break; |
| 681 | default: |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 682 | hw_dbg("Flow control param set incorrectly\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 683 | ret_val = -E1000_ERR_CONFIG; |
| 684 | goto out; |
| 685 | } |
| 686 | |
| 687 | wr32(E1000_CTRL, ctrl); |
| 688 | |
| 689 | out: |
| 690 | return ret_val; |
| 691 | } |
| 692 | |
| 693 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 694 | * igb_config_fc_after_link_up - Configures flow control after link |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 695 | * @hw: pointer to the HW structure |
| 696 | * |
| 697 | * Checks the status of auto-negotiation after link up to ensure that the |
| 698 | * speed and duplex were not forced. If the link needed to be forced, then |
| 699 | * flow control needs to be forced also. If auto-negotiation is enabled |
| 700 | * and did not fail, then we configure flow control based on our link |
| 701 | * partner. |
| 702 | **/ |
| 703 | s32 igb_config_fc_after_link_up(struct e1000_hw *hw) |
| 704 | { |
| 705 | struct e1000_mac_info *mac = &hw->mac; |
| 706 | s32 ret_val = 0; |
| 707 | u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; |
| 708 | u16 speed, duplex; |
| 709 | |
| 710 | /* |
| 711 | * Check for the case where we have fiber media and auto-neg failed |
| 712 | * so we had to force link. In this case, we need to force the |
| 713 | * configuration of the MAC to match the "fc" parameter. |
| 714 | */ |
| 715 | if (mac->autoneg_failed) { |
| 716 | if (hw->phy.media_type == e1000_media_type_fiber || |
| 717 | hw->phy.media_type == e1000_media_type_internal_serdes) |
| 718 | ret_val = igb_force_mac_fc(hw); |
| 719 | } else { |
| 720 | if (hw->phy.media_type == e1000_media_type_copper) |
| 721 | ret_val = igb_force_mac_fc(hw); |
| 722 | } |
| 723 | |
| 724 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 725 | hw_dbg("Error forcing flow control settings\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 726 | goto out; |
| 727 | } |
| 728 | |
| 729 | /* |
| 730 | * Check for the case where we have copper media and auto-neg is |
| 731 | * enabled. In this case, we need to check and see if Auto-Neg |
| 732 | * has completed, and if so, how the PHY and link partner has |
| 733 | * flow control configured. |
| 734 | */ |
| 735 | if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { |
| 736 | /* |
| 737 | * Read the MII Status Register and check to see if AutoNeg |
| 738 | * has completed. We read this twice because this reg has |
| 739 | * some "sticky" (latched) bits. |
| 740 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 741 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 742 | &mii_status_reg); |
| 743 | if (ret_val) |
| 744 | goto out; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 745 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 746 | &mii_status_reg); |
| 747 | if (ret_val) |
| 748 | goto out; |
| 749 | |
| 750 | if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 751 | hw_dbg("Copper PHY and Auto Neg " |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 752 | "has not completed.\n"); |
| 753 | goto out; |
| 754 | } |
| 755 | |
| 756 | /* |
| 757 | * The AutoNeg process has completed, so we now need to |
| 758 | * read both the Auto Negotiation Advertisement |
| 759 | * Register (Address 4) and the Auto_Negotiation Base |
| 760 | * Page Ability Register (Address 5) to determine how |
| 761 | * flow control was negotiated. |
| 762 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 763 | ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 764 | &mii_nway_adv_reg); |
| 765 | if (ret_val) |
| 766 | goto out; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 767 | ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 768 | &mii_nway_lp_ability_reg); |
| 769 | if (ret_val) |
| 770 | goto out; |
| 771 | |
| 772 | /* |
| 773 | * Two bits in the Auto Negotiation Advertisement Register |
| 774 | * (Address 4) and two bits in the Auto Negotiation Base |
| 775 | * Page Ability Register (Address 5) determine flow control |
| 776 | * for both the PHY and the link partner. The following |
| 777 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
| 778 | * 1999, describes these PAUSE resolution bits and how flow |
| 779 | * control is determined based upon these settings. |
| 780 | * NOTE: DC = Don't Care |
| 781 | * |
| 782 | * LOCAL DEVICE | LINK PARTNER |
| 783 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
| 784 | *-------|---------|-------|---------|-------------------- |
| 785 | * 0 | 0 | DC | DC | e1000_fc_none |
| 786 | * 0 | 1 | 0 | DC | e1000_fc_none |
| 787 | * 0 | 1 | 1 | 0 | e1000_fc_none |
| 788 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 789 | * 1 | 0 | 0 | DC | e1000_fc_none |
| 790 | * 1 | DC | 1 | DC | e1000_fc_full |
| 791 | * 1 | 1 | 0 | 0 | e1000_fc_none |
| 792 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 793 | * |
| 794 | * Are both PAUSE bits set to 1? If so, this implies |
| 795 | * Symmetric Flow Control is enabled at both ends. The |
| 796 | * ASM_DIR bits are irrelevant per the spec. |
| 797 | * |
| 798 | * For Symmetric Flow Control: |
| 799 | * |
| 800 | * LOCAL DEVICE | LINK PARTNER |
| 801 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 802 | *-------|---------|-------|---------|-------------------- |
| 803 | * 1 | DC | 1 | DC | E1000_fc_full |
| 804 | * |
| 805 | */ |
| 806 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 807 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
| 808 | /* |
| 809 | * Now we need to check if the user selected RX ONLY |
| 810 | * of pause frames. In this case, we had to advertise |
| 811 | * FULL flow control because we could not advertise RX |
| 812 | * ONLY. Hence, we must now check to see if we need to |
| 813 | * turn OFF the TRANSMISSION of PAUSE frames. |
| 814 | */ |
| 815 | if (hw->fc.original_type == e1000_fc_full) { |
| 816 | hw->fc.type = e1000_fc_full; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 817 | hw_dbg("Flow Control = FULL.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 818 | } else { |
| 819 | hw->fc.type = e1000_fc_rx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 820 | hw_dbg("Flow Control = " |
| 821 | "RX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 822 | } |
| 823 | } |
| 824 | /* |
| 825 | * For receiving PAUSE frames ONLY. |
| 826 | * |
| 827 | * LOCAL DEVICE | LINK PARTNER |
| 828 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 829 | *-------|---------|-------|---------|-------------------- |
| 830 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 831 | */ |
| 832 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 833 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 834 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 835 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
| 836 | hw->fc.type = e1000_fc_tx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 837 | hw_dbg("Flow Control = TX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 838 | } |
| 839 | /* |
| 840 | * For transmitting PAUSE frames ONLY. |
| 841 | * |
| 842 | * LOCAL DEVICE | LINK PARTNER |
| 843 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 844 | *-------|---------|-------|---------|-------------------- |
| 845 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 846 | */ |
| 847 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 848 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 849 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 850 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
| 851 | hw->fc.type = e1000_fc_rx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 852 | hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 853 | } |
| 854 | /* |
| 855 | * Per the IEEE spec, at this point flow control should be |
| 856 | * disabled. However, we want to consider that we could |
| 857 | * be connected to a legacy switch that doesn't advertise |
| 858 | * desired flow control, but can be forced on the link |
| 859 | * partner. So if we advertised no flow control, that is |
| 860 | * what we will resolve to. If we advertised some kind of |
| 861 | * receive capability (Rx Pause Only or Full Flow Control) |
| 862 | * and the link partner advertised none, we will configure |
| 863 | * ourselves to enable Rx Flow Control only. We can do |
| 864 | * this safely for two reasons: If the link partner really |
| 865 | * didn't want flow control enabled, and we enable Rx, no |
| 866 | * harm done since we won't be receiving any PAUSE frames |
| 867 | * anyway. If the intent on the link partner was to have |
| 868 | * flow control enabled, then by us enabling RX only, we |
| 869 | * can at least receive pause frames and process them. |
| 870 | * This is a good idea because in most cases, since we are |
| 871 | * predominantly a server NIC, more times than not we will |
| 872 | * be asked to delay transmission of packets than asking |
| 873 | * our link partner to pause transmission of frames. |
| 874 | */ |
| 875 | else if ((hw->fc.original_type == e1000_fc_none || |
| 876 | hw->fc.original_type == e1000_fc_tx_pause) || |
| 877 | hw->fc.strict_ieee) { |
| 878 | hw->fc.type = e1000_fc_none; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 879 | hw_dbg("Flow Control = NONE.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 880 | } else { |
| 881 | hw->fc.type = e1000_fc_rx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 882 | hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 883 | } |
| 884 | |
| 885 | /* |
| 886 | * Now we need to do one last check... If we auto- |
| 887 | * negotiated to HALF DUPLEX, flow control should not be |
| 888 | * enabled per IEEE 802.3 spec. |
| 889 | */ |
| 890 | ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); |
| 891 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 892 | hw_dbg("Error getting link speed and duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 893 | goto out; |
| 894 | } |
| 895 | |
| 896 | if (duplex == HALF_DUPLEX) |
| 897 | hw->fc.type = e1000_fc_none; |
| 898 | |
| 899 | /* |
| 900 | * Now we call a subroutine to actually force the MAC |
| 901 | * controller to use the correct flow control settings. |
| 902 | */ |
| 903 | ret_val = igb_force_mac_fc(hw); |
| 904 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 905 | hw_dbg("Error forcing flow control settings\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 906 | goto out; |
| 907 | } |
| 908 | } |
| 909 | |
| 910 | out: |
| 911 | return ret_val; |
| 912 | } |
| 913 | |
| 914 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 915 | * igb_get_speed_and_duplex_copper - Retreive current speed/duplex |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 916 | * @hw: pointer to the HW structure |
| 917 | * @speed: stores the current speed |
| 918 | * @duplex: stores the current duplex |
| 919 | * |
| 920 | * Read the status register for the current speed/duplex and store the current |
| 921 | * speed and duplex for copper connections. |
| 922 | **/ |
| 923 | s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, |
| 924 | u16 *duplex) |
| 925 | { |
| 926 | u32 status; |
| 927 | |
| 928 | status = rd32(E1000_STATUS); |
| 929 | if (status & E1000_STATUS_SPEED_1000) { |
| 930 | *speed = SPEED_1000; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 931 | hw_dbg("1000 Mbs, "); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 932 | } else if (status & E1000_STATUS_SPEED_100) { |
| 933 | *speed = SPEED_100; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 934 | hw_dbg("100 Mbs, "); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 935 | } else { |
| 936 | *speed = SPEED_10; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 937 | hw_dbg("10 Mbs, "); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 938 | } |
| 939 | |
| 940 | if (status & E1000_STATUS_FD) { |
| 941 | *duplex = FULL_DUPLEX; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 942 | hw_dbg("Full Duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 943 | } else { |
| 944 | *duplex = HALF_DUPLEX; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 945 | hw_dbg("Half Duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 946 | } |
| 947 | |
| 948 | return 0; |
| 949 | } |
| 950 | |
| 951 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 952 | * igb_get_hw_semaphore - Acquire hardware semaphore |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 953 | * @hw: pointer to the HW structure |
| 954 | * |
| 955 | * Acquire the HW semaphore to access the PHY or NVM |
| 956 | **/ |
| 957 | s32 igb_get_hw_semaphore(struct e1000_hw *hw) |
| 958 | { |
| 959 | u32 swsm; |
| 960 | s32 ret_val = 0; |
| 961 | s32 timeout = hw->nvm.word_size + 1; |
| 962 | s32 i = 0; |
| 963 | |
| 964 | /* Get the SW semaphore */ |
| 965 | while (i < timeout) { |
| 966 | swsm = rd32(E1000_SWSM); |
| 967 | if (!(swsm & E1000_SWSM_SMBI)) |
| 968 | break; |
| 969 | |
| 970 | udelay(50); |
| 971 | i++; |
| 972 | } |
| 973 | |
| 974 | if (i == timeout) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 975 | hw_dbg("Driver can't access device - SMBI bit is set.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 976 | ret_val = -E1000_ERR_NVM; |
| 977 | goto out; |
| 978 | } |
| 979 | |
| 980 | /* Get the FW semaphore. */ |
| 981 | for (i = 0; i < timeout; i++) { |
| 982 | swsm = rd32(E1000_SWSM); |
| 983 | wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); |
| 984 | |
| 985 | /* Semaphore acquired if bit latched */ |
| 986 | if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) |
| 987 | break; |
| 988 | |
| 989 | udelay(50); |
| 990 | } |
| 991 | |
| 992 | if (i == timeout) { |
| 993 | /* Release semaphores */ |
| 994 | igb_put_hw_semaphore(hw); |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 995 | hw_dbg("Driver can't access the NVM\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 996 | ret_val = -E1000_ERR_NVM; |
| 997 | goto out; |
| 998 | } |
| 999 | |
| 1000 | out: |
| 1001 | return ret_val; |
| 1002 | } |
| 1003 | |
| 1004 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1005 | * igb_put_hw_semaphore - Release hardware semaphore |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1006 | * @hw: pointer to the HW structure |
| 1007 | * |
| 1008 | * Release hardware semaphore used to access the PHY or NVM |
| 1009 | **/ |
| 1010 | void igb_put_hw_semaphore(struct e1000_hw *hw) |
| 1011 | { |
| 1012 | u32 swsm; |
| 1013 | |
| 1014 | swsm = rd32(E1000_SWSM); |
| 1015 | |
| 1016 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
| 1017 | |
| 1018 | wr32(E1000_SWSM, swsm); |
| 1019 | } |
| 1020 | |
| 1021 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1022 | * igb_get_auto_rd_done - Check for auto read completion |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1023 | * @hw: pointer to the HW structure |
| 1024 | * |
| 1025 | * Check EEPROM for Auto Read done bit. |
| 1026 | **/ |
| 1027 | s32 igb_get_auto_rd_done(struct e1000_hw *hw) |
| 1028 | { |
| 1029 | s32 i = 0; |
| 1030 | s32 ret_val = 0; |
| 1031 | |
| 1032 | |
| 1033 | while (i < AUTO_READ_DONE_TIMEOUT) { |
| 1034 | if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD) |
| 1035 | break; |
| 1036 | msleep(1); |
| 1037 | i++; |
| 1038 | } |
| 1039 | |
| 1040 | if (i == AUTO_READ_DONE_TIMEOUT) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1041 | hw_dbg("Auto read by HW from NVM has not completed.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1042 | ret_val = -E1000_ERR_RESET; |
| 1043 | goto out; |
| 1044 | } |
| 1045 | |
| 1046 | out: |
| 1047 | return ret_val; |
| 1048 | } |
| 1049 | |
| 1050 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1051 | * igb_valid_led_default - Verify a valid default LED config |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1052 | * @hw: pointer to the HW structure |
| 1053 | * @data: pointer to the NVM (EEPROM) |
| 1054 | * |
| 1055 | * Read the EEPROM for the current default LED configuration. If the |
| 1056 | * LED configuration is not valid, set to a valid LED configuration. |
| 1057 | **/ |
| 1058 | static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data) |
| 1059 | { |
| 1060 | s32 ret_val; |
| 1061 | |
Alexander Duyck | 312c75a | 2009-02-06 23:17:47 +0000 | [diff] [blame] | 1062 | ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1063 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1064 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1065 | goto out; |
| 1066 | } |
| 1067 | |
| 1068 | if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) |
| 1069 | *data = ID_LED_DEFAULT; |
| 1070 | |
| 1071 | out: |
| 1072 | return ret_val; |
| 1073 | } |
| 1074 | |
| 1075 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1076 | * igb_id_led_init - |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1077 | * @hw: pointer to the HW structure |
| 1078 | * |
| 1079 | **/ |
| 1080 | s32 igb_id_led_init(struct e1000_hw *hw) |
| 1081 | { |
| 1082 | struct e1000_mac_info *mac = &hw->mac; |
| 1083 | s32 ret_val; |
| 1084 | const u32 ledctl_mask = 0x000000FF; |
| 1085 | const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
| 1086 | const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
| 1087 | u16 data, i, temp; |
| 1088 | const u16 led_mask = 0x0F; |
| 1089 | |
| 1090 | ret_val = igb_valid_led_default(hw, &data); |
| 1091 | if (ret_val) |
| 1092 | goto out; |
| 1093 | |
| 1094 | mac->ledctl_default = rd32(E1000_LEDCTL); |
| 1095 | mac->ledctl_mode1 = mac->ledctl_default; |
| 1096 | mac->ledctl_mode2 = mac->ledctl_default; |
| 1097 | |
| 1098 | for (i = 0; i < 4; i++) { |
| 1099 | temp = (data >> (i << 2)) & led_mask; |
| 1100 | switch (temp) { |
| 1101 | case ID_LED_ON1_DEF2: |
| 1102 | case ID_LED_ON1_ON2: |
| 1103 | case ID_LED_ON1_OFF2: |
| 1104 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 1105 | mac->ledctl_mode1 |= ledctl_on << (i << 3); |
| 1106 | break; |
| 1107 | case ID_LED_OFF1_DEF2: |
| 1108 | case ID_LED_OFF1_ON2: |
| 1109 | case ID_LED_OFF1_OFF2: |
| 1110 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 1111 | mac->ledctl_mode1 |= ledctl_off << (i << 3); |
| 1112 | break; |
| 1113 | default: |
| 1114 | /* Do nothing */ |
| 1115 | break; |
| 1116 | } |
| 1117 | switch (temp) { |
| 1118 | case ID_LED_DEF1_ON2: |
| 1119 | case ID_LED_ON1_ON2: |
| 1120 | case ID_LED_OFF1_ON2: |
| 1121 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 1122 | mac->ledctl_mode2 |= ledctl_on << (i << 3); |
| 1123 | break; |
| 1124 | case ID_LED_DEF1_OFF2: |
| 1125 | case ID_LED_ON1_OFF2: |
| 1126 | case ID_LED_OFF1_OFF2: |
| 1127 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 1128 | mac->ledctl_mode2 |= ledctl_off << (i << 3); |
| 1129 | break; |
| 1130 | default: |
| 1131 | /* Do nothing */ |
| 1132 | break; |
| 1133 | } |
| 1134 | } |
| 1135 | |
| 1136 | out: |
| 1137 | return ret_val; |
| 1138 | } |
| 1139 | |
| 1140 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1141 | * igb_cleanup_led - Set LED config to default operation |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1142 | * @hw: pointer to the HW structure |
| 1143 | * |
| 1144 | * Remove the current LED configuration and set the LED configuration |
| 1145 | * to the default value, saved from the EEPROM. |
| 1146 | **/ |
| 1147 | s32 igb_cleanup_led(struct e1000_hw *hw) |
| 1148 | { |
| 1149 | wr32(E1000_LEDCTL, hw->mac.ledctl_default); |
| 1150 | return 0; |
| 1151 | } |
| 1152 | |
| 1153 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1154 | * igb_blink_led - Blink LED |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1155 | * @hw: pointer to the HW structure |
| 1156 | * |
| 1157 | * Blink the led's which are set to be on. |
| 1158 | **/ |
| 1159 | s32 igb_blink_led(struct e1000_hw *hw) |
| 1160 | { |
| 1161 | u32 ledctl_blink = 0; |
| 1162 | u32 i; |
| 1163 | |
| 1164 | if (hw->phy.media_type == e1000_media_type_fiber) { |
| 1165 | /* always blink LED0 for PCI-E fiber */ |
| 1166 | ledctl_blink = E1000_LEDCTL_LED0_BLINK | |
| 1167 | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); |
| 1168 | } else { |
| 1169 | /* |
| 1170 | * set the blink bit for each LED that's "on" (0x0E) |
| 1171 | * in ledctl_mode2 |
| 1172 | */ |
| 1173 | ledctl_blink = hw->mac.ledctl_mode2; |
| 1174 | for (i = 0; i < 4; i++) |
| 1175 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == |
| 1176 | E1000_LEDCTL_MODE_LED_ON) |
| 1177 | ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << |
| 1178 | (i * 8)); |
| 1179 | } |
| 1180 | |
| 1181 | wr32(E1000_LEDCTL, ledctl_blink); |
| 1182 | |
| 1183 | return 0; |
| 1184 | } |
| 1185 | |
| 1186 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1187 | * igb_led_off - Turn LED off |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1188 | * @hw: pointer to the HW structure |
| 1189 | * |
| 1190 | * Turn LED off. |
| 1191 | **/ |
| 1192 | s32 igb_led_off(struct e1000_hw *hw) |
| 1193 | { |
| 1194 | u32 ctrl; |
| 1195 | |
| 1196 | switch (hw->phy.media_type) { |
| 1197 | case e1000_media_type_fiber: |
| 1198 | ctrl = rd32(E1000_CTRL); |
| 1199 | ctrl |= E1000_CTRL_SWDPIN0; |
| 1200 | ctrl |= E1000_CTRL_SWDPIO0; |
| 1201 | wr32(E1000_CTRL, ctrl); |
| 1202 | break; |
| 1203 | case e1000_media_type_copper: |
| 1204 | wr32(E1000_LEDCTL, hw->mac.ledctl_mode1); |
| 1205 | break; |
| 1206 | default: |
| 1207 | break; |
| 1208 | } |
| 1209 | |
| 1210 | return 0; |
| 1211 | } |
| 1212 | |
| 1213 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1214 | * igb_disable_pcie_master - Disables PCI-express master access |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1215 | * @hw: pointer to the HW structure |
| 1216 | * |
| 1217 | * Returns 0 (0) if successful, else returns -10 |
| 1218 | * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued |
| 1219 | * the master requests to be disabled. |
| 1220 | * |
| 1221 | * Disables PCI-Express master access and verifies there are no pending |
| 1222 | * requests. |
| 1223 | **/ |
| 1224 | s32 igb_disable_pcie_master(struct e1000_hw *hw) |
| 1225 | { |
| 1226 | u32 ctrl; |
| 1227 | s32 timeout = MASTER_DISABLE_TIMEOUT; |
| 1228 | s32 ret_val = 0; |
| 1229 | |
| 1230 | if (hw->bus.type != e1000_bus_type_pci_express) |
| 1231 | goto out; |
| 1232 | |
| 1233 | ctrl = rd32(E1000_CTRL); |
| 1234 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
| 1235 | wr32(E1000_CTRL, ctrl); |
| 1236 | |
| 1237 | while (timeout) { |
| 1238 | if (!(rd32(E1000_STATUS) & |
| 1239 | E1000_STATUS_GIO_MASTER_ENABLE)) |
| 1240 | break; |
| 1241 | udelay(100); |
| 1242 | timeout--; |
| 1243 | } |
| 1244 | |
| 1245 | if (!timeout) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1246 | hw_dbg("Master requests are pending.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1247 | ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; |
| 1248 | goto out; |
| 1249 | } |
| 1250 | |
| 1251 | out: |
| 1252 | return ret_val; |
| 1253 | } |
| 1254 | |
| 1255 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1256 | * igb_reset_adaptive - Reset Adaptive Interframe Spacing |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1257 | * @hw: pointer to the HW structure |
| 1258 | * |
| 1259 | * Reset the Adaptive Interframe Spacing throttle to default values. |
| 1260 | **/ |
| 1261 | void igb_reset_adaptive(struct e1000_hw *hw) |
| 1262 | { |
| 1263 | struct e1000_mac_info *mac = &hw->mac; |
| 1264 | |
| 1265 | if (!mac->adaptive_ifs) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1266 | hw_dbg("Not in Adaptive IFS mode!\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1267 | goto out; |
| 1268 | } |
| 1269 | |
| 1270 | if (!mac->ifs_params_forced) { |
| 1271 | mac->current_ifs_val = 0; |
| 1272 | mac->ifs_min_val = IFS_MIN; |
| 1273 | mac->ifs_max_val = IFS_MAX; |
| 1274 | mac->ifs_step_size = IFS_STEP; |
| 1275 | mac->ifs_ratio = IFS_RATIO; |
| 1276 | } |
| 1277 | |
| 1278 | mac->in_ifs_mode = false; |
| 1279 | wr32(E1000_AIT, 0); |
| 1280 | out: |
| 1281 | return; |
| 1282 | } |
| 1283 | |
| 1284 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1285 | * igb_update_adaptive - Update Adaptive Interframe Spacing |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1286 | * @hw: pointer to the HW structure |
| 1287 | * |
| 1288 | * Update the Adaptive Interframe Spacing Throttle value based on the |
| 1289 | * time between transmitted packets and time between collisions. |
| 1290 | **/ |
| 1291 | void igb_update_adaptive(struct e1000_hw *hw) |
| 1292 | { |
| 1293 | struct e1000_mac_info *mac = &hw->mac; |
| 1294 | |
| 1295 | if (!mac->adaptive_ifs) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1296 | hw_dbg("Not in Adaptive IFS mode!\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1297 | goto out; |
| 1298 | } |
| 1299 | |
| 1300 | if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { |
| 1301 | if (mac->tx_packet_delta > MIN_NUM_XMITS) { |
| 1302 | mac->in_ifs_mode = true; |
| 1303 | if (mac->current_ifs_val < mac->ifs_max_val) { |
| 1304 | if (!mac->current_ifs_val) |
| 1305 | mac->current_ifs_val = mac->ifs_min_val; |
| 1306 | else |
| 1307 | mac->current_ifs_val += |
| 1308 | mac->ifs_step_size; |
| 1309 | wr32(E1000_AIT, |
| 1310 | mac->current_ifs_val); |
| 1311 | } |
| 1312 | } |
| 1313 | } else { |
| 1314 | if (mac->in_ifs_mode && |
| 1315 | (mac->tx_packet_delta <= MIN_NUM_XMITS)) { |
| 1316 | mac->current_ifs_val = 0; |
| 1317 | mac->in_ifs_mode = false; |
| 1318 | wr32(E1000_AIT, 0); |
| 1319 | } |
| 1320 | } |
| 1321 | out: |
| 1322 | return; |
| 1323 | } |
| 1324 | |
| 1325 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1326 | * igb_validate_mdi_setting - Verify MDI/MDIx settings |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1327 | * @hw: pointer to the HW structure |
| 1328 | * |
| 1329 | * Verify that when not using auto-negotitation that MDI/MDIx is correctly |
| 1330 | * set, which is forced to MDI mode only. |
| 1331 | **/ |
| 1332 | s32 igb_validate_mdi_setting(struct e1000_hw *hw) |
| 1333 | { |
| 1334 | s32 ret_val = 0; |
| 1335 | |
| 1336 | if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1337 | hw_dbg("Invalid MDI setting detected\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1338 | hw->phy.mdix = 1; |
| 1339 | ret_val = -E1000_ERR_CONFIG; |
| 1340 | goto out; |
| 1341 | } |
| 1342 | |
| 1343 | out: |
| 1344 | return ret_val; |
| 1345 | } |
| 1346 | |
| 1347 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1348 | * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1349 | * @hw: pointer to the HW structure |
| 1350 | * @reg: 32bit register offset such as E1000_SCTL |
| 1351 | * @offset: register offset to write to |
| 1352 | * @data: data to write at register offset |
| 1353 | * |
| 1354 | * Writes an address/data control type register. There are several of these |
| 1355 | * and they all have the format address << 8 | data and bit 31 is polled for |
| 1356 | * completion. |
| 1357 | **/ |
| 1358 | s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, |
| 1359 | u32 offset, u8 data) |
| 1360 | { |
| 1361 | u32 i, regvalue = 0; |
| 1362 | s32 ret_val = 0; |
| 1363 | |
| 1364 | /* Set up the address and data */ |
| 1365 | regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); |
| 1366 | wr32(reg, regvalue); |
| 1367 | |
| 1368 | /* Poll the ready bit to see if the MDI read completed */ |
| 1369 | for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { |
| 1370 | udelay(5); |
| 1371 | regvalue = rd32(reg); |
| 1372 | if (regvalue & E1000_GEN_CTL_READY) |
| 1373 | break; |
| 1374 | } |
| 1375 | if (!(regvalue & E1000_GEN_CTL_READY)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1376 | hw_dbg("Reg %08x did not indicate ready\n", reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1377 | ret_val = -E1000_ERR_PHY; |
| 1378 | goto out; |
| 1379 | } |
| 1380 | |
| 1381 | out: |
| 1382 | return ret_val; |
| 1383 | } |
| 1384 | |
| 1385 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1386 | * igb_enable_mng_pass_thru - Enable processing of ARP's |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1387 | * @hw: pointer to the HW structure |
| 1388 | * |
| 1389 | * Verifies the hardware needs to allow ARPs to be processed by the host. |
| 1390 | **/ |
| 1391 | bool igb_enable_mng_pass_thru(struct e1000_hw *hw) |
| 1392 | { |
| 1393 | u32 manc; |
| 1394 | u32 fwsm, factps; |
| 1395 | bool ret_val = false; |
| 1396 | |
| 1397 | if (!hw->mac.asf_firmware_present) |
| 1398 | goto out; |
| 1399 | |
| 1400 | manc = rd32(E1000_MANC); |
| 1401 | |
| 1402 | if (!(manc & E1000_MANC_RCV_TCO_EN) || |
| 1403 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
| 1404 | goto out; |
| 1405 | |
| 1406 | if (hw->mac.arc_subsystem_valid) { |
| 1407 | fwsm = rd32(E1000_FWSM); |
| 1408 | factps = rd32(E1000_FACTPS); |
| 1409 | |
| 1410 | if (!(factps & E1000_FACTPS_MNGCG) && |
| 1411 | ((fwsm & E1000_FWSM_MODE_MASK) == |
| 1412 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { |
| 1413 | ret_val = true; |
| 1414 | goto out; |
| 1415 | } |
| 1416 | } else { |
| 1417 | if ((manc & E1000_MANC_SMBUS_EN) && |
| 1418 | !(manc & E1000_MANC_ASF_EN)) { |
| 1419 | ret_val = true; |
| 1420 | goto out; |
| 1421 | } |
| 1422 | } |
| 1423 | |
| 1424 | out: |
| 1425 | return ret_val; |
| 1426 | } |