Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/include/asm/pmu.h |
| 3 | * |
| 4 | * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles |
| 5 | * Copyright (C) 2012 ARM Ltd. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | #ifndef __ASM_PMU_H |
| 20 | #define __ASM_PMU_H |
| 21 | |
| 22 | #ifdef CONFIG_HW_PERF_EVENTS |
| 23 | |
| 24 | /* The events for a given PMU register set. */ |
| 25 | struct pmu_hw_events { |
| 26 | /* |
| 27 | * The events that are active on the PMU for the given index. |
| 28 | */ |
| 29 | struct perf_event **events; |
| 30 | |
| 31 | /* |
| 32 | * A 1 bit for an index indicates that the counter is being used for |
| 33 | * an event. A 0 means that the counter can be used. |
| 34 | */ |
| 35 | unsigned long *used_mask; |
| 36 | |
| 37 | /* |
| 38 | * Hardware lock to serialize accesses to PMU registers. Needed for the |
| 39 | * read/modify/write sequences. |
| 40 | */ |
| 41 | raw_spinlock_t pmu_lock; |
| 42 | }; |
| 43 | |
| 44 | struct arm_pmu { |
| 45 | struct pmu pmu; |
| 46 | cpumask_t active_irqs; |
| 47 | const char *name; |
| 48 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
| 49 | void (*enable)(struct hw_perf_event *evt, int idx); |
| 50 | void (*disable)(struct hw_perf_event *evt, int idx); |
| 51 | int (*get_event_idx)(struct pmu_hw_events *hw_events, |
| 52 | struct hw_perf_event *hwc); |
| 53 | int (*set_event_filter)(struct hw_perf_event *evt, |
| 54 | struct perf_event_attr *attr); |
| 55 | u32 (*read_counter)(int idx); |
| 56 | void (*write_counter)(int idx, u32 val); |
| 57 | void (*start)(void); |
| 58 | void (*stop)(void); |
| 59 | void (*reset)(void *); |
| 60 | int (*map_event)(struct perf_event *event); |
| 61 | int num_events; |
| 62 | atomic_t active_events; |
| 63 | struct mutex reserve_mutex; |
| 64 | u64 max_period; |
| 65 | struct platform_device *plat_device; |
| 66 | struct pmu_hw_events *(*get_hw_events)(void); |
| 67 | }; |
| 68 | |
| 69 | #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) |
| 70 | |
| 71 | int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type); |
| 72 | |
| 73 | u64 armpmu_event_update(struct perf_event *event, |
| 74 | struct hw_perf_event *hwc, |
| 75 | int idx); |
| 76 | |
| 77 | int armpmu_event_set_period(struct perf_event *event, |
| 78 | struct hw_perf_event *hwc, |
| 79 | int idx); |
| 80 | |
| 81 | #endif /* CONFIG_HW_PERF_EVENTS */ |
| 82 | #endif /* __ASM_PMU_H */ |