Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015 MediaTek Inc. |
| 3 | * Author: Hanyi Wu <hanyi.wu@mediatek.com> |
| 4 | * Sascha Hauer <s.hauer@pengutronix.de> |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 5 | * Dawei Chien <dawei.chien@mediatek.com> |
Louis Yu | 6cf7f00 | 2017-08-01 15:28:31 +0800 | [diff] [blame] | 6 | * Louis Yu <louis.yu@mediatek.com> |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/clk.h> |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/nvmem-consumer.h> |
| 24 | #include <linux/of.h> |
| 25 | #include <linux/of_address.h> |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 26 | #include <linux/of_device.h> |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 27 | #include <linux/platform_device.h> |
| 28 | #include <linux/slab.h> |
| 29 | #include <linux/io.h> |
| 30 | #include <linux/thermal.h> |
| 31 | #include <linux/reset.h> |
| 32 | #include <linux/types.h> |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 33 | |
| 34 | /* AUXADC Registers */ |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 35 | #define AUXADC_CON1_SET_V 0x008 |
| 36 | #define AUXADC_CON1_CLR_V 0x00c |
| 37 | #define AUXADC_CON2_V 0x010 |
| 38 | #define AUXADC_DATA(channel) (0x14 + (channel) * 4) |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 39 | |
| 40 | #define APMIXED_SYS_TS_CON1 0x604 |
| 41 | |
| 42 | /* Thermal Controller Registers */ |
| 43 | #define TEMP_MONCTL0 0x000 |
| 44 | #define TEMP_MONCTL1 0x004 |
| 45 | #define TEMP_MONCTL2 0x008 |
| 46 | #define TEMP_MONIDET0 0x014 |
| 47 | #define TEMP_MONIDET1 0x018 |
| 48 | #define TEMP_MSRCTL0 0x038 |
| 49 | #define TEMP_AHBPOLL 0x040 |
| 50 | #define TEMP_AHBTO 0x044 |
| 51 | #define TEMP_ADCPNP0 0x048 |
| 52 | #define TEMP_ADCPNP1 0x04c |
| 53 | #define TEMP_ADCPNP2 0x050 |
| 54 | #define TEMP_ADCPNP3 0x0b4 |
| 55 | |
| 56 | #define TEMP_ADCMUX 0x054 |
| 57 | #define TEMP_ADCEN 0x060 |
| 58 | #define TEMP_PNPMUXADDR 0x064 |
| 59 | #define TEMP_ADCMUXADDR 0x068 |
| 60 | #define TEMP_ADCENADDR 0x074 |
| 61 | #define TEMP_ADCVALIDADDR 0x078 |
| 62 | #define TEMP_ADCVOLTADDR 0x07c |
| 63 | #define TEMP_RDCTRL 0x080 |
| 64 | #define TEMP_ADCVALIDMASK 0x084 |
| 65 | #define TEMP_ADCVOLTAGESHIFT 0x088 |
| 66 | #define TEMP_ADCWRITECTRL 0x08c |
| 67 | #define TEMP_MSR0 0x090 |
| 68 | #define TEMP_MSR1 0x094 |
| 69 | #define TEMP_MSR2 0x098 |
| 70 | #define TEMP_MSR3 0x0B8 |
| 71 | |
| 72 | #define TEMP_SPARE0 0x0f0 |
| 73 | |
| 74 | #define PTPCORESEL 0x400 |
| 75 | |
| 76 | #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) |
| 77 | |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 78 | #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 79 | #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) |
| 80 | |
| 81 | #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) |
| 82 | |
| 83 | #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) |
| 84 | #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) |
| 85 | |
| 86 | #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) |
| 87 | #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) |
| 88 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 89 | /* MT8173 thermal sensors */ |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 90 | #define MT8173_TS1 0 |
| 91 | #define MT8173_TS2 1 |
| 92 | #define MT8173_TS3 2 |
| 93 | #define MT8173_TS4 3 |
| 94 | #define MT8173_TSABB 4 |
| 95 | |
| 96 | /* AUXADC channel 11 is used for the temperature sensors */ |
| 97 | #define MT8173_TEMP_AUXADC_CHANNEL 11 |
| 98 | |
| 99 | /* The total number of temperature sensors in the MT8173 */ |
| 100 | #define MT8173_NUM_SENSORS 5 |
| 101 | |
| 102 | /* The number of banks in the MT8173 */ |
| 103 | #define MT8173_NUM_ZONES 4 |
| 104 | |
| 105 | /* The number of sensing points per bank */ |
| 106 | #define MT8173_NUM_SENSORS_PER_ZONE 4 |
| 107 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 108 | /* |
| 109 | * Layout of the fuses providing the calibration data |
Louis Yu | 0a06899 | 2017-08-01 15:28:32 +0800 | [diff] [blame] | 110 | * These macros could be used for MT8173, MT2701, and MT2712. |
| 111 | * MT8173 has 5 sensors and needs 5 VTS calibration data. |
| 112 | * MT2701 has 3 sensors and needs 3 VTS calibration data. |
| 113 | * MT2712 has 4 sensors and needs 4 VTS calibration data. |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 114 | */ |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 115 | #define MT8173_CALIB_BUF0_VALID BIT(0) |
| 116 | #define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff) |
| 117 | #define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff) |
| 118 | #define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff) |
| 119 | #define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff) |
| 120 | #define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff) |
| 121 | #define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff) |
| 122 | #define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f) |
| 123 | #define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f) |
Louis Yu | 0a06899 | 2017-08-01 15:28:32 +0800 | [diff] [blame] | 124 | #define MT8173_CALIB_BUF0_O_SLOPE_SIGN(x) (((x) >> 7) & 0x1) |
| 125 | #define MT8173_CALIB_BUF1_ID(x) (((x) >> 9) & 0x1) |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 126 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 127 | /* MT2701 thermal sensors */ |
| 128 | #define MT2701_TS1 0 |
| 129 | #define MT2701_TS2 1 |
| 130 | #define MT2701_TSABB 2 |
| 131 | |
| 132 | /* AUXADC channel 11 is used for the temperature sensors */ |
| 133 | #define MT2701_TEMP_AUXADC_CHANNEL 11 |
| 134 | |
| 135 | /* The total number of temperature sensors in the MT2701 */ |
| 136 | #define MT2701_NUM_SENSORS 3 |
| 137 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 138 | /* The number of sensing points per bank */ |
| 139 | #define MT2701_NUM_SENSORS_PER_ZONE 3 |
| 140 | |
Louis Yu | 6cf7f00 | 2017-08-01 15:28:31 +0800 | [diff] [blame] | 141 | /* MT2712 thermal sensors */ |
| 142 | #define MT2712_TS1 0 |
| 143 | #define MT2712_TS2 1 |
| 144 | #define MT2712_TS3 2 |
| 145 | #define MT2712_TS4 3 |
| 146 | |
| 147 | /* AUXADC channel 11 is used for the temperature sensors */ |
| 148 | #define MT2712_TEMP_AUXADC_CHANNEL 11 |
| 149 | |
| 150 | /* The total number of temperature sensors in the MT2712 */ |
| 151 | #define MT2712_NUM_SENSORS 4 |
| 152 | |
| 153 | /* The number of sensing points per bank */ |
| 154 | #define MT2712_NUM_SENSORS_PER_ZONE 4 |
| 155 | |
Sean Wang | 3966be3c0 | 2018-02-17 16:49:02 +0800 | [diff] [blame] | 156 | #define MT7622_TEMP_AUXADC_CHANNEL 11 |
| 157 | #define MT7622_NUM_SENSORS 1 |
| 158 | #define MT7622_NUM_ZONES 1 |
| 159 | #define MT7622_NUM_SENSORS_PER_ZONE 1 |
| 160 | #define MT7622_TS1 0 |
| 161 | |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 162 | struct mtk_thermal; |
| 163 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 164 | struct thermal_bank_cfg { |
| 165 | unsigned int num_sensors; |
| 166 | const int *sensors; |
| 167 | }; |
| 168 | |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 169 | struct mtk_thermal_bank { |
| 170 | struct mtk_thermal *mt; |
| 171 | int id; |
| 172 | }; |
| 173 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 174 | struct mtk_thermal_data { |
| 175 | s32 num_banks; |
| 176 | s32 num_sensors; |
| 177 | s32 auxadc_channel; |
| 178 | const int *sensor_mux_values; |
| 179 | const int *msr; |
| 180 | const int *adcpnp; |
| 181 | struct thermal_bank_cfg bank_data[]; |
| 182 | }; |
| 183 | |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 184 | struct mtk_thermal { |
| 185 | struct device *dev; |
| 186 | void __iomem *thermal_base; |
| 187 | |
| 188 | struct clk *clk_peri_therm; |
| 189 | struct clk *clk_auxadc; |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 190 | /* lock: for getting and putting banks */ |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 191 | struct mutex lock; |
| 192 | |
| 193 | /* Calibration values */ |
| 194 | s32 adc_ge; |
| 195 | s32 degc_cali; |
| 196 | s32 o_slope; |
| 197 | s32 vts[MT8173_NUM_SENSORS]; |
| 198 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 199 | const struct mtk_thermal_data *conf; |
| 200 | struct mtk_thermal_bank banks[]; |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 201 | }; |
| 202 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 203 | /* MT8173 thermal sensor data */ |
Vivek Gautam | 992edf3 | 2016-12-28 14:16:45 +0530 | [diff] [blame] | 204 | static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 205 | { MT8173_TS2, MT8173_TS3 }, |
| 206 | { MT8173_TS2, MT8173_TS4 }, |
| 207 | { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, |
| 208 | { MT8173_TS2 }, |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 209 | }; |
| 210 | |
Vivek Gautam | 992edf3 | 2016-12-28 14:16:45 +0530 | [diff] [blame] | 211 | static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { |
Dawei Chien | 05d7839 | 2017-02-21 20:26:52 +0800 | [diff] [blame] | 212 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 213 | }; |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 214 | |
Vivek Gautam | 992edf3 | 2016-12-28 14:16:45 +0530 | [diff] [blame] | 215 | static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 216 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 |
| 217 | }; |
| 218 | |
Vivek Gautam | 992edf3 | 2016-12-28 14:16:45 +0530 | [diff] [blame] | 219 | static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 220 | |
| 221 | /* MT2701 thermal sensor data */ |
Vivek Gautam | 992edf3 | 2016-12-28 14:16:45 +0530 | [diff] [blame] | 222 | static const int mt2701_bank_data[MT2701_NUM_SENSORS] = { |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 223 | MT2701_TS1, MT2701_TS2, MT2701_TSABB |
| 224 | }; |
| 225 | |
Vivek Gautam | 992edf3 | 2016-12-28 14:16:45 +0530 | [diff] [blame] | 226 | static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 227 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 |
| 228 | }; |
| 229 | |
Vivek Gautam | 992edf3 | 2016-12-28 14:16:45 +0530 | [diff] [blame] | 230 | static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 231 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 |
| 232 | }; |
| 233 | |
Vivek Gautam | 992edf3 | 2016-12-28 14:16:45 +0530 | [diff] [blame] | 234 | static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 235 | |
Louis Yu | 6cf7f00 | 2017-08-01 15:28:31 +0800 | [diff] [blame] | 236 | /* MT2712 thermal sensor data */ |
| 237 | static const int mt2712_bank_data[MT2712_NUM_SENSORS] = { |
| 238 | MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4 |
| 239 | }; |
| 240 | |
| 241 | static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = { |
| 242 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 |
| 243 | }; |
| 244 | |
| 245 | static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = { |
| 246 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 |
| 247 | }; |
| 248 | |
| 249 | static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; |
| 250 | |
Sean Wang | 3966be3c0 | 2018-02-17 16:49:02 +0800 | [diff] [blame] | 251 | /* MT7622 thermal sensor data */ |
| 252 | static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, }; |
| 253 | static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; |
| 254 | static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; |
| 255 | static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; |
| 256 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 257 | /** |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 258 | * The MT8173 thermal controller has four banks. Each bank can read up to |
| 259 | * four temperature sensors simultaneously. The MT8173 has a total of 5 |
| 260 | * temperature sensors. We use each bank to measure a certain area of the |
| 261 | * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple |
| 262 | * areas, hence is used in different banks. |
| 263 | * |
| 264 | * The thermal core only gets the maximum temperature of all banks, so |
| 265 | * the bank concept wouldn't be necessary here. However, the SVS (Smart |
| 266 | * Voltage Scaling) unit makes its decisions based on the same bank |
| 267 | * data, and this indeed needs the temperatures of the individual banks |
| 268 | * for making better decisions. |
| 269 | */ |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 270 | static const struct mtk_thermal_data mt8173_thermal_data = { |
| 271 | .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, |
| 272 | .num_banks = MT8173_NUM_ZONES, |
| 273 | .num_sensors = MT8173_NUM_SENSORS, |
| 274 | .bank_data = { |
| 275 | { |
| 276 | .num_sensors = 2, |
| 277 | .sensors = mt8173_bank_data[0], |
| 278 | }, { |
| 279 | .num_sensors = 2, |
| 280 | .sensors = mt8173_bank_data[1], |
| 281 | }, { |
| 282 | .num_sensors = 3, |
| 283 | .sensors = mt8173_bank_data[2], |
| 284 | }, { |
| 285 | .num_sensors = 1, |
| 286 | .sensors = mt8173_bank_data[3], |
| 287 | }, |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 288 | }, |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 289 | .msr = mt8173_msr, |
| 290 | .adcpnp = mt8173_adcpnp, |
| 291 | .sensor_mux_values = mt8173_mux_values, |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 292 | }; |
| 293 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 294 | /** |
| 295 | * The MT2701 thermal controller has one bank, which can read up to |
| 296 | * three temperature sensors simultaneously. The MT2701 has a total of 3 |
| 297 | * temperature sensors. |
| 298 | * |
| 299 | * The thermal core only gets the maximum temperature of this one bank, |
| 300 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart |
| 301 | * Voltage Scaling) unit makes its decisions based on the same bank |
| 302 | * data. |
| 303 | */ |
| 304 | static const struct mtk_thermal_data mt2701_thermal_data = { |
| 305 | .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, |
| 306 | .num_banks = 1, |
| 307 | .num_sensors = MT2701_NUM_SENSORS, |
| 308 | .bank_data = { |
| 309 | { |
| 310 | .num_sensors = 3, |
| 311 | .sensors = mt2701_bank_data, |
| 312 | }, |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 313 | }, |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 314 | .msr = mt2701_msr, |
| 315 | .adcpnp = mt2701_adcpnp, |
| 316 | .sensor_mux_values = mt2701_mux_values, |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 317 | }; |
| 318 | |
| 319 | /** |
Louis Yu | 6cf7f00 | 2017-08-01 15:28:31 +0800 | [diff] [blame] | 320 | * The MT2712 thermal controller has one bank, which can read up to |
| 321 | * four temperature sensors simultaneously. The MT2712 has a total of 4 |
| 322 | * temperature sensors. |
| 323 | * |
| 324 | * The thermal core only gets the maximum temperature of this one bank, |
| 325 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart |
| 326 | * Voltage Scaling) unit makes its decisions based on the same bank |
| 327 | * data. |
| 328 | */ |
| 329 | static const struct mtk_thermal_data mt2712_thermal_data = { |
| 330 | .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL, |
| 331 | .num_banks = 1, |
| 332 | .num_sensors = MT2712_NUM_SENSORS, |
| 333 | .bank_data = { |
| 334 | { |
| 335 | .num_sensors = 4, |
| 336 | .sensors = mt2712_bank_data, |
| 337 | }, |
| 338 | }, |
| 339 | .msr = mt2712_msr, |
| 340 | .adcpnp = mt2712_adcpnp, |
| 341 | .sensor_mux_values = mt2712_mux_values, |
| 342 | }; |
| 343 | |
Sean Wang | 3966be3c0 | 2018-02-17 16:49:02 +0800 | [diff] [blame] | 344 | /* |
| 345 | * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data |
| 346 | * access. |
| 347 | */ |
| 348 | static const struct mtk_thermal_data mt7622_thermal_data = { |
| 349 | .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL, |
| 350 | .num_banks = MT7622_NUM_ZONES, |
| 351 | .num_sensors = MT7622_NUM_SENSORS, |
| 352 | .bank_data = { |
| 353 | { |
| 354 | .num_sensors = 1, |
| 355 | .sensors = mt7622_bank_data, |
| 356 | }, |
| 357 | }, |
| 358 | .msr = mt7622_msr, |
| 359 | .adcpnp = mt7622_adcpnp, |
| 360 | .sensor_mux_values = mt7622_mux_values, |
| 361 | }; |
| 362 | |
Louis Yu | 6cf7f00 | 2017-08-01 15:28:31 +0800 | [diff] [blame] | 363 | /** |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 364 | * raw_to_mcelsius - convert a raw ADC value to mcelsius |
| 365 | * @mt: The thermal controller |
| 366 | * @raw: raw ADC value |
| 367 | * |
| 368 | * This converts the raw ADC value to mcelsius using the SoC specific |
| 369 | * calibration constants |
| 370 | */ |
| 371 | static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) |
| 372 | { |
| 373 | s32 tmp; |
| 374 | |
| 375 | raw &= 0xfff; |
| 376 | |
| 377 | tmp = 203450520 << 3; |
| 378 | tmp /= 165 + mt->o_slope; |
| 379 | tmp /= 10000 + mt->adc_ge; |
| 380 | tmp *= raw - mt->vts[sensno] - 3350; |
| 381 | tmp >>= 3; |
| 382 | |
| 383 | return mt->degc_cali * 500 - tmp; |
| 384 | } |
| 385 | |
| 386 | /** |
| 387 | * mtk_thermal_get_bank - get bank |
| 388 | * @bank: The bank |
| 389 | * |
| 390 | * The bank registers are banked, we have to select a bank in the |
| 391 | * PTPCORESEL register to access it. |
| 392 | */ |
| 393 | static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) |
| 394 | { |
| 395 | struct mtk_thermal *mt = bank->mt; |
| 396 | u32 val; |
| 397 | |
| 398 | mutex_lock(&mt->lock); |
| 399 | |
| 400 | val = readl(mt->thermal_base + PTPCORESEL); |
| 401 | val &= ~0xf; |
| 402 | val |= bank->id; |
| 403 | writel(val, mt->thermal_base + PTPCORESEL); |
| 404 | } |
| 405 | |
| 406 | /** |
| 407 | * mtk_thermal_put_bank - release bank |
| 408 | * @bank: The bank |
| 409 | * |
| 410 | * release a bank previously taken with mtk_thermal_get_bank, |
| 411 | */ |
| 412 | static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) |
| 413 | { |
| 414 | struct mtk_thermal *mt = bank->mt; |
| 415 | |
| 416 | mutex_unlock(&mt->lock); |
| 417 | } |
| 418 | |
| 419 | /** |
| 420 | * mtk_thermal_bank_temperature - get the temperature of a bank |
| 421 | * @bank: The bank |
| 422 | * |
| 423 | * The temperature of a bank is considered the maximum temperature of |
| 424 | * the sensors associated to the bank. |
| 425 | */ |
| 426 | static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) |
| 427 | { |
| 428 | struct mtk_thermal *mt = bank->mt; |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 429 | const struct mtk_thermal_data *conf = mt->conf; |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 430 | int i, temp = INT_MIN, max = INT_MIN; |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 431 | u32 raw; |
| 432 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 433 | for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { |
Michael Kao | 82871fb | 2019-02-01 15:38:07 +0800 | [diff] [blame] | 434 | raw = readl(mt->thermal_base + |
| 435 | conf->msr[conf->bank_data[bank->id].sensors[i]]); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 436 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 437 | temp = raw_to_mcelsius(mt, |
| 438 | conf->bank_data[bank->id].sensors[i], |
| 439 | raw); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 440 | |
| 441 | /* |
| 442 | * The first read of a sensor often contains very high bogus |
| 443 | * temperature value. Filter these out so that the system does |
| 444 | * not immediately shut down. |
| 445 | */ |
| 446 | if (temp > 200000) |
| 447 | temp = 0; |
| 448 | |
| 449 | if (temp > max) |
| 450 | max = temp; |
| 451 | } |
| 452 | |
| 453 | return max; |
| 454 | } |
| 455 | |
| 456 | static int mtk_read_temp(void *data, int *temperature) |
| 457 | { |
| 458 | struct mtk_thermal *mt = data; |
| 459 | int i; |
| 460 | int tempmax = INT_MIN; |
| 461 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 462 | for (i = 0; i < mt->conf->num_banks; i++) { |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 463 | struct mtk_thermal_bank *bank = &mt->banks[i]; |
| 464 | |
| 465 | mtk_thermal_get_bank(bank); |
| 466 | |
| 467 | tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); |
| 468 | |
| 469 | mtk_thermal_put_bank(bank); |
| 470 | } |
| 471 | |
| 472 | *temperature = tempmax; |
| 473 | |
| 474 | return 0; |
| 475 | } |
| 476 | |
| 477 | static const struct thermal_zone_of_device_ops mtk_thermal_ops = { |
| 478 | .get_temp = mtk_read_temp, |
| 479 | }; |
| 480 | |
| 481 | static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 482 | u32 apmixed_phys_base, u32 auxadc_phys_base) |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 483 | { |
| 484 | struct mtk_thermal_bank *bank = &mt->banks[num]; |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 485 | const struct mtk_thermal_data *conf = mt->conf; |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 486 | int i; |
| 487 | |
| 488 | bank->id = num; |
| 489 | bank->mt = mt; |
| 490 | |
| 491 | mtk_thermal_get_bank(bank); |
| 492 | |
| 493 | /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ |
| 494 | writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); |
| 495 | |
| 496 | /* |
| 497 | * filt interval is 1 * 46.540us = 46.54us, |
| 498 | * sen interval is 429 * 46.540us = 19.96ms |
| 499 | */ |
| 500 | writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | |
| 501 | TEMP_MONCTL2_SENSOR_INTERVAL(429), |
| 502 | mt->thermal_base + TEMP_MONCTL2); |
| 503 | |
| 504 | /* poll is set to 10u */ |
| 505 | writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 506 | mt->thermal_base + TEMP_AHBPOLL); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 507 | |
| 508 | /* temperature sampling control, 1 sample */ |
| 509 | writel(0x0, mt->thermal_base + TEMP_MSRCTL0); |
| 510 | |
| 511 | /* exceed this polling time, IRQ would be inserted */ |
| 512 | writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); |
| 513 | |
| 514 | /* number of interrupts per event, 1 is enough */ |
| 515 | writel(0x0, mt->thermal_base + TEMP_MONIDET0); |
| 516 | writel(0x0, mt->thermal_base + TEMP_MONIDET1); |
| 517 | |
| 518 | /* |
| 519 | * The MT8173 thermal controller does not have its own ADC. Instead it |
| 520 | * uses AHB bus accesses to control the AUXADC. To do this the thermal |
| 521 | * controller has to be programmed with the physical addresses of the |
| 522 | * AUXADC registers and with the various bit positions in the AUXADC. |
| 523 | * Also the thermal controller controls a mux in the APMIXEDSYS register |
| 524 | * space. |
| 525 | */ |
| 526 | |
| 527 | /* |
| 528 | * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) |
| 529 | * automatically by hw |
| 530 | */ |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 531 | writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCMUX); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 532 | |
| 533 | /* AHB address for auxadc mux selection */ |
| 534 | writel(auxadc_phys_base + AUXADC_CON1_CLR_V, |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 535 | mt->thermal_base + TEMP_ADCMUXADDR); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 536 | |
| 537 | /* AHB address for pnp sensor mux selection */ |
| 538 | writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 539 | mt->thermal_base + TEMP_PNPMUXADDR); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 540 | |
| 541 | /* AHB value for auxadc enable */ |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 542 | writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCEN); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 543 | |
| 544 | /* AHB address for auxadc enable (channel 0 immediate mode selected) */ |
| 545 | writel(auxadc_phys_base + AUXADC_CON1_SET_V, |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 546 | mt->thermal_base + TEMP_ADCENADDR); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 547 | |
| 548 | /* AHB address for auxadc valid bit */ |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 549 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 550 | mt->thermal_base + TEMP_ADCVALIDADDR); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 551 | |
| 552 | /* AHB address for auxadc voltage output */ |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 553 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 554 | mt->thermal_base + TEMP_ADCVOLTADDR); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 555 | |
| 556 | /* read valid & voltage are at the same register */ |
| 557 | writel(0x0, mt->thermal_base + TEMP_RDCTRL); |
| 558 | |
| 559 | /* indicate where the valid bit is */ |
| 560 | writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 561 | mt->thermal_base + TEMP_ADCVALIDMASK); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 562 | |
| 563 | /* no shift */ |
| 564 | writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); |
| 565 | |
| 566 | /* enable auxadc mux write transaction */ |
| 567 | writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 568 | mt->thermal_base + TEMP_ADCWRITECTRL); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 569 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 570 | for (i = 0; i < conf->bank_data[num].num_sensors; i++) |
| 571 | writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], |
Michael Kao | 82871fb | 2019-02-01 15:38:07 +0800 | [diff] [blame] | 572 | mt->thermal_base + |
| 573 | conf->adcpnp[conf->bank_data[num].sensors[i]]); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 574 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 575 | writel((1 << conf->bank_data[num].num_sensors) - 1, |
| 576 | mt->thermal_base + TEMP_MONCTL0); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 577 | |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 578 | writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | |
| 579 | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, |
| 580 | mt->thermal_base + TEMP_ADCWRITECTRL); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 581 | |
| 582 | mtk_thermal_put_bank(bank); |
| 583 | } |
| 584 | |
| 585 | static u64 of_get_phys_base(struct device_node *np) |
| 586 | { |
| 587 | u64 size64; |
| 588 | const __be32 *regaddr_p; |
| 589 | |
| 590 | regaddr_p = of_get_address(np, 0, &size64, NULL); |
| 591 | if (!regaddr_p) |
| 592 | return OF_BAD_ADDR; |
| 593 | |
| 594 | return of_translate_address(np, regaddr_p); |
| 595 | } |
| 596 | |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 597 | static int mtk_thermal_get_calibration_data(struct device *dev, |
| 598 | struct mtk_thermal *mt) |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 599 | { |
| 600 | struct nvmem_cell *cell; |
| 601 | u32 *buf; |
| 602 | size_t len; |
| 603 | int i, ret = 0; |
| 604 | |
| 605 | /* Start with default values */ |
| 606 | mt->adc_ge = 512; |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 607 | for (i = 0; i < mt->conf->num_sensors; i++) |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 608 | mt->vts[i] = 260; |
| 609 | mt->degc_cali = 40; |
| 610 | mt->o_slope = 0; |
| 611 | |
| 612 | cell = nvmem_cell_get(dev, "calibration-data"); |
| 613 | if (IS_ERR(cell)) { |
| 614 | if (PTR_ERR(cell) == -EPROBE_DEFER) |
| 615 | return PTR_ERR(cell); |
| 616 | return 0; |
| 617 | } |
| 618 | |
| 619 | buf = (u32 *)nvmem_cell_read(cell, &len); |
| 620 | |
| 621 | nvmem_cell_put(cell); |
| 622 | |
| 623 | if (IS_ERR(buf)) |
| 624 | return PTR_ERR(buf); |
| 625 | |
| 626 | if (len < 3 * sizeof(u32)) { |
| 627 | dev_warn(dev, "invalid calibration data\n"); |
| 628 | ret = -EINVAL; |
| 629 | goto out; |
| 630 | } |
| 631 | |
| 632 | if (buf[0] & MT8173_CALIB_BUF0_VALID) { |
| 633 | mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); |
| 634 | mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); |
| 635 | mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); |
| 636 | mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); |
| 637 | mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); |
| 638 | mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); |
| 639 | mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); |
Louis Yu | 0a06899 | 2017-08-01 15:28:32 +0800 | [diff] [blame] | 640 | if (MT8173_CALIB_BUF1_ID(buf[1]) & |
| 641 | MT8173_CALIB_BUF0_O_SLOPE_SIGN(buf[0])) |
| 642 | mt->o_slope = -MT8173_CALIB_BUF0_O_SLOPE(buf[0]); |
| 643 | else |
| 644 | mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 645 | } else { |
| 646 | dev_info(dev, "Device not calibrated, using default calibration values\n"); |
| 647 | } |
| 648 | |
| 649 | out: |
| 650 | kfree(buf); |
| 651 | |
| 652 | return ret; |
| 653 | } |
| 654 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 655 | static const struct of_device_id mtk_thermal_of_match[] = { |
| 656 | { |
| 657 | .compatible = "mediatek,mt8173-thermal", |
| 658 | .data = (void *)&mt8173_thermal_data, |
| 659 | }, |
| 660 | { |
| 661 | .compatible = "mediatek,mt2701-thermal", |
| 662 | .data = (void *)&mt2701_thermal_data, |
Louis Yu | 6cf7f00 | 2017-08-01 15:28:31 +0800 | [diff] [blame] | 663 | }, |
| 664 | { |
| 665 | .compatible = "mediatek,mt2712-thermal", |
| 666 | .data = (void *)&mt2712_thermal_data, |
Sean Wang | 3966be3c0 | 2018-02-17 16:49:02 +0800 | [diff] [blame] | 667 | }, |
| 668 | { |
| 669 | .compatible = "mediatek,mt7622-thermal", |
| 670 | .data = (void *)&mt7622_thermal_data, |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 671 | }, { |
| 672 | }, |
| 673 | }; |
| 674 | MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); |
| 675 | |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 676 | static int mtk_thermal_probe(struct platform_device *pdev) |
| 677 | { |
| 678 | int ret, i; |
| 679 | struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; |
| 680 | struct mtk_thermal *mt; |
| 681 | struct resource *res; |
| 682 | u64 auxadc_phys_base, apmixed_phys_base; |
Axel Lin | 1f6b088 | 2016-09-07 17:24:52 +0800 | [diff] [blame] | 683 | struct thermal_zone_device *tzdev; |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 684 | |
| 685 | mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); |
| 686 | if (!mt) |
| 687 | return -ENOMEM; |
| 688 | |
Ryder Lee | 9efc58d | 2018-04-16 10:34:16 +0800 | [diff] [blame] | 689 | mt->conf = of_device_get_match_data(&pdev->dev); |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 690 | |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 691 | mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); |
| 692 | if (IS_ERR(mt->clk_peri_therm)) |
| 693 | return PTR_ERR(mt->clk_peri_therm); |
| 694 | |
| 695 | mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); |
| 696 | if (IS_ERR(mt->clk_auxadc)) |
| 697 | return PTR_ERR(mt->clk_auxadc); |
| 698 | |
| 699 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 700 | mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); |
| 701 | if (IS_ERR(mt->thermal_base)) |
| 702 | return PTR_ERR(mt->thermal_base); |
| 703 | |
| 704 | ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); |
| 705 | if (ret) |
| 706 | return ret; |
| 707 | |
| 708 | mutex_init(&mt->lock); |
| 709 | |
| 710 | mt->dev = &pdev->dev; |
| 711 | |
| 712 | auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); |
| 713 | if (!auxadc) { |
| 714 | dev_err(&pdev->dev, "missing auxadc node\n"); |
| 715 | return -ENODEV; |
| 716 | } |
| 717 | |
| 718 | auxadc_phys_base = of_get_phys_base(auxadc); |
| 719 | |
| 720 | of_node_put(auxadc); |
| 721 | |
| 722 | if (auxadc_phys_base == OF_BAD_ADDR) { |
| 723 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); |
| 724 | return -EINVAL; |
| 725 | } |
| 726 | |
| 727 | apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); |
| 728 | if (!apmixedsys) { |
| 729 | dev_err(&pdev->dev, "missing apmixedsys node\n"); |
| 730 | return -ENODEV; |
| 731 | } |
| 732 | |
| 733 | apmixed_phys_base = of_get_phys_base(apmixedsys); |
| 734 | |
| 735 | of_node_put(apmixedsys); |
| 736 | |
| 737 | if (apmixed_phys_base == OF_BAD_ADDR) { |
| 738 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); |
| 739 | return -EINVAL; |
| 740 | } |
| 741 | |
Louis Yu | 6760f3f | 2017-08-01 15:28:33 +0800 | [diff] [blame] | 742 | ret = device_reset(&pdev->dev); |
| 743 | if (ret) |
| 744 | return ret; |
| 745 | |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 746 | ret = clk_prepare_enable(mt->clk_auxadc); |
| 747 | if (ret) { |
| 748 | dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); |
| 749 | return ret; |
| 750 | } |
| 751 | |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 752 | ret = clk_prepare_enable(mt->clk_peri_therm); |
| 753 | if (ret) { |
| 754 | dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); |
| 755 | goto err_disable_clk_auxadc; |
| 756 | } |
| 757 | |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 758 | for (i = 0; i < mt->conf->num_banks; i++) |
Eduardo Valentin | eb4fc33 | 2016-02-18 07:43:57 -0800 | [diff] [blame] | 759 | mtk_thermal_init_bank(mt, i, apmixed_phys_base, |
| 760 | auxadc_phys_base); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 761 | |
| 762 | platform_set_drvdata(pdev, mt); |
| 763 | |
Axel Lin | 1f6b088 | 2016-09-07 17:24:52 +0800 | [diff] [blame] | 764 | tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt, |
| 765 | &mtk_thermal_ops); |
| 766 | if (IS_ERR(tzdev)) { |
| 767 | ret = PTR_ERR(tzdev); |
| 768 | goto err_disable_clk_peri_therm; |
| 769 | } |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 770 | |
| 771 | return 0; |
| 772 | |
Axel Lin | 1f6b088 | 2016-09-07 17:24:52 +0800 | [diff] [blame] | 773 | err_disable_clk_peri_therm: |
| 774 | clk_disable_unprepare(mt->clk_peri_therm); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 775 | err_disable_clk_auxadc: |
| 776 | clk_disable_unprepare(mt->clk_auxadc); |
| 777 | |
| 778 | return ret; |
| 779 | } |
| 780 | |
| 781 | static int mtk_thermal_remove(struct platform_device *pdev) |
| 782 | { |
| 783 | struct mtk_thermal *mt = platform_get_drvdata(pdev); |
| 784 | |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 785 | clk_disable_unprepare(mt->clk_peri_therm); |
| 786 | clk_disable_unprepare(mt->clk_auxadc); |
| 787 | |
| 788 | return 0; |
| 789 | } |
| 790 | |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 791 | static struct platform_driver mtk_thermal_driver = { |
| 792 | .probe = mtk_thermal_probe, |
| 793 | .remove = mtk_thermal_remove, |
| 794 | .driver = { |
Matthias Brugger | f45ce7e | 2017-12-01 11:43:21 +0100 | [diff] [blame] | 795 | .name = "mtk-thermal", |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 796 | .of_match_table = mtk_thermal_of_match, |
| 797 | }, |
| 798 | }; |
| 799 | |
| 800 | module_platform_driver(mtk_thermal_driver); |
| 801 | |
Louis Yu | 6cf7f00 | 2017-08-01 15:28:31 +0800 | [diff] [blame] | 802 | MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>"); |
dawei.chien@mediatek.com | b7cf005 | 2016-08-18 11:50:52 +0800 | [diff] [blame] | 803 | MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>"); |
Randy Dunlap | 9ebfb4e | 2016-04-19 16:45:01 -0700 | [diff] [blame] | 804 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
Sascha Hauer | a92db1c | 2015-11-30 12:42:32 +0100 | [diff] [blame] | 805 | MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); |
| 806 | MODULE_DESCRIPTION("Mediatek thermal driver"); |
| 807 | MODULE_LICENSE("GPL v2"); |