blob: 91a71774472eca02976018c63ebccc4ab2372709 [file] [log] [blame]
Nicolas Ferre467f1cf2012-01-26 11:59:20 +01001/*
2 * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +080010#include "at91sam9g25.dtsi"
11#include "at91sam9x5ek.dtsi"
Nicolas Ferre467f1cf2012-01-26 11:59:20 +010012
13/ {
14 model = "Atmel AT91SAM9G25-EK";
15 compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
Nicolas Ferre509ea1b2013-03-22 14:47:54 +010016
17 ahb {
18 apb {
Josh Wu3978d6b2015-02-12 16:06:25 +080019 spi0: spi@f0000000 {
20 status = "disabled";
21 };
22
23 mmc1: mmc@f000c000 {
24 status = "disabled";
25 };
26
27 i2c0: i2c@f8010000 {
28 ov2640: camera@0x30 {
Alexandre Belloniefedc482016-07-14 16:50:17 +020029 compatible = "ovti,ov2640";
30 reg = <0x30>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
33 resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
34 pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
35 clocks = <&pck0>;
36 clock-names = "xvclk";
37 assigned-clocks = <&pck0>;
38 assigned-clock-rates = <25000000>;
Josh Wu3978d6b2015-02-12 16:06:25 +080039 status = "okay";
Alexandre Belloniefedc482016-07-14 16:50:17 +020040
41 port {
42 ov2640_0: endpoint {
43 remote-endpoint = <&isi_0>;
44 bus-width = <8>;
45 };
46 };
Josh Wu3978d6b2015-02-12 16:06:25 +080047 };
48 };
49
Nicolas Ferre509ea1b2013-03-22 14:47:54 +010050 macb0: ethernet@f802c000 {
51 phy-mode = "rmii";
52 status = "okay";
53 };
Josh Wu3978d6b2015-02-12 16:06:25 +080054
55 isi: isi@f8048000 {
56 status = "okay";
Alexandre Belloniefedc482016-07-14 16:50:17 +020057 port {
58 isi_0: endpoint@0 {
Alexandre Belloni81c940d2016-07-14 17:04:50 +020059 reg = <0>;
Alexandre Belloniefedc482016-07-14 16:50:17 +020060 remote-endpoint = <&ov2640_0>;
61 bus-width = <8>;
62 vsync-active = <1>;
63 hsync-active = <1>;
64 };
65 };
Josh Wu3978d6b2015-02-12 16:06:25 +080066 };
Nicolas Ferre509ea1b2013-03-22 14:47:54 +010067 };
68 };
Nicolas Ferre467f1cf2012-01-26 11:59:20 +010069};