Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 1 | /* |
Nicolas Ferre | 8dafaa1 | 2015-03-04 17:56:03 +0100 | [diff] [blame] | 2 | * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 3 | * 2 TC blocks. |
| 4 | * |
| 5 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> |
| 6 | * |
| 7 | * Licensed under GPLv2. |
| 8 | */ |
| 9 | |
| 10 | #include <dt-bindings/pinctrl/at91.h> |
| 11 | #include <dt-bindings/interrupt-controller/irq.h> |
Tushar Behera | 35d35aa | 2014-03-06 11:34:43 +0530 | [diff] [blame] | 12 | #include <dt-bindings/clock/at91.h> |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 13 | |
| 14 | / { |
| 15 | aliases { |
| 16 | tcb1 = &tcb1; |
| 17 | }; |
| 18 | |
| 19 | ahb { |
| 20 | apb { |
Boris BREZILLON | d2e8190 | 2013-10-18 23:48:27 +0200 | [diff] [blame] | 21 | pmc: pmc@fffffc00 { |
| 22 | periphck { |
| 23 | tcb1_clk: tcb1_clk { |
| 24 | #clock-cells = <0>; |
| 25 | reg = <27>; |
| 26 | }; |
| 27 | }; |
| 28 | }; |
| 29 | |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 30 | tcb1: timer@f8014000 { |
| 31 | compatible = "atmel,at91sam9x5-tcb"; |
| 32 | reg = <0xf8014000 0x100>; |
| 33 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; |
Alexandre Belloni | 288fb7f | 2015-07-29 14:10:06 +0200 | [diff] [blame] | 34 | clocks = <&tcb1_clk>, <&clk32k>; |
| 35 | clock-names = "t0_clk", "slow_clk"; |
Boris BREZILLON | d7d1d45 | 2013-08-07 10:49:01 +0200 | [diff] [blame] | 36 | }; |
| 37 | }; |
| 38 | }; |
| 39 | }; |