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Paul Walmsley73591542010-02-22 22:09:32 -07001/*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2010 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
13 *
14 * XXX these should be marked initdata for multi-OMAP kernels
15 */
16#include <plat/omap_hwmod.h>
17#include <mach/irqs.h>
18#include <plat/cpu.h>
19#include <plat/dma.h>
Kevin Hilman046465b2010-09-27 20:19:30 +053020#include <plat/serial.h>
Senthilvadivu Guruswamye04d9e12011-01-24 06:21:51 +000021#include <plat/l3_3xxx.h>
Rajendra Nayak4fe20e92010-09-21 19:37:13 +053022#include <plat/l4_3xxx.h>
23#include <plat/i2c.h>
Varadarajan, Charulatha70034d32010-12-07 16:26:57 -080024#include <plat/gpio.h>
Thara Gopinathd3442722010-05-29 22:02:24 +053025#include <plat/smartreflex.h>
Charulatha V0f616a42011-02-17 09:53:10 -080026#include <plat/mcspi.h>
Thara Gopinathce722d22011-02-23 00:14:05 -070027#include <plat/dmtimer.h>
Paul Walmsley73591542010-02-22 22:09:32 -070028
Paul Walmsley43b40992010-02-22 22:09:34 -070029#include "omap_hwmod_common_data.h"
30
Paul Walmsley73591542010-02-22 22:09:32 -070031#include "prm-regbits-34xx.h"
Varadarajan, Charulatha6b667f82010-09-23 20:02:38 +053032#include "cm-regbits-34xx.h"
Paul Walmsleyff2516f2010-12-21 15:39:15 -070033#include "wd_timer.h"
Hema HK273ff8c2011-02-17 12:07:19 +053034#include <mach/am35xx.h>
Paul Walmsley73591542010-02-22 22:09:32 -070035
36/*
37 * OMAP3xxx hardware module integration data
38 *
39 * ALl of the data in this section should be autogeneratable from the
40 * TI hardware database or other technical documentation. Data that
41 * is driver-specific or driver-kernel integration-specific belongs
42 * elsewhere.
43 */
44
45static struct omap_hwmod omap3xxx_mpu_hwmod;
Kevin Hilman540064b2010-07-26 16:34:32 -060046static struct omap_hwmod omap3xxx_iva_hwmod;
Kevin Hilman4a7cf902010-07-26 16:34:32 -060047static struct omap_hwmod omap3xxx_l3_main_hwmod;
Paul Walmsley73591542010-02-22 22:09:32 -070048static struct omap_hwmod omap3xxx_l4_core_hwmod;
49static struct omap_hwmod omap3xxx_l4_per_hwmod;
Varadarajan, Charulatha6b667f82010-09-23 20:02:38 +053050static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
Senthilvadivu Guruswamye04d9e12011-01-24 06:21:51 +000051static struct omap_hwmod omap3430es1_dss_core_hwmod;
52static struct omap_hwmod omap3xxx_dss_core_hwmod;
53static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
54static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
55static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
56static struct omap_hwmod omap3xxx_dss_venc_hwmod;
Rajendra Nayak4fe20e92010-09-21 19:37:13 +053057static struct omap_hwmod omap3xxx_i2c1_hwmod;
58static struct omap_hwmod omap3xxx_i2c2_hwmod;
59static struct omap_hwmod omap3xxx_i2c3_hwmod;
Varadarajan, Charulatha70034d32010-12-07 16:26:57 -080060static struct omap_hwmod omap3xxx_gpio1_hwmod;
61static struct omap_hwmod omap3xxx_gpio2_hwmod;
62static struct omap_hwmod omap3xxx_gpio3_hwmod;
63static struct omap_hwmod omap3xxx_gpio4_hwmod;
64static struct omap_hwmod omap3xxx_gpio5_hwmod;
65static struct omap_hwmod omap3xxx_gpio6_hwmod;
Thara Gopinathd3442722010-05-29 22:02:24 +053066static struct omap_hwmod omap34xx_sr1_hwmod;
67static struct omap_hwmod omap34xx_sr2_hwmod;
Charulatha V0f616a42011-02-17 09:53:10 -080068static struct omap_hwmod omap34xx_mcspi1;
69static struct omap_hwmod omap34xx_mcspi2;
70static struct omap_hwmod omap34xx_mcspi3;
71static struct omap_hwmod omap34xx_mcspi4;
Hema HK273ff8c2011-02-17 12:07:19 +053072static struct omap_hwmod am35xx_usbhsotg_hwmod;
Paul Walmsley73591542010-02-22 22:09:32 -070073
G, Manjunath Kondaiah01438ab2010-12-20 18:27:19 -080074static struct omap_hwmod omap3xxx_dma_system_hwmod;
75
Paul Walmsley73591542010-02-22 22:09:32 -070076/* L3 -> L4_CORE interface */
Kevin Hilman4a7cf902010-07-26 16:34:32 -060077static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
78 .master = &omap3xxx_l3_main_hwmod,
Paul Walmsley73591542010-02-22 22:09:32 -070079 .slave = &omap3xxx_l4_core_hwmod,
80 .user = OCP_USER_MPU | OCP_USER_SDMA,
81};
82
83/* L3 -> L4_PER interface */
Kevin Hilman4a7cf902010-07-26 16:34:32 -060084static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
85 .master = &omap3xxx_l3_main_hwmod,
Paul Walmsley73591542010-02-22 22:09:32 -070086 .slave = &omap3xxx_l4_per_hwmod,
87 .user = OCP_USER_MPU | OCP_USER_SDMA,
88};
89
90/* MPU -> L3 interface */
Kevin Hilman4a7cf902010-07-26 16:34:32 -060091static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
Paul Walmsley73591542010-02-22 22:09:32 -070092 .master = &omap3xxx_mpu_hwmod,
Kevin Hilman4a7cf902010-07-26 16:34:32 -060093 .slave = &omap3xxx_l3_main_hwmod,
Paul Walmsley73591542010-02-22 22:09:32 -070094 .user = OCP_USER_MPU,
95};
96
97/* Slave interfaces on the L3 interconnect */
Kevin Hilman4a7cf902010-07-26 16:34:32 -060098static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
99 &omap3xxx_mpu__l3_main,
Paul Walmsley73591542010-02-22 22:09:32 -0700100};
101
Senthilvadivu Guruswamye04d9e12011-01-24 06:21:51 +0000102/* DSS -> l3 */
103static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
104 .master = &omap3xxx_dss_core_hwmod,
105 .slave = &omap3xxx_l3_main_hwmod,
106 .fw = {
107 .omap2 = {
108 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
109 .flags = OMAP_FIREWALL_L3,
110 }
111 },
112 .user = OCP_USER_MPU | OCP_USER_SDMA,
113};
114
Paul Walmsley73591542010-02-22 22:09:32 -0700115/* Master interfaces on the L3 interconnect */
Kevin Hilman4a7cf902010-07-26 16:34:32 -0600116static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
117 &omap3xxx_l3_main__l4_core,
118 &omap3xxx_l3_main__l4_per,
Paul Walmsley73591542010-02-22 22:09:32 -0700119};
120
121/* L3 */
Kevin Hilman4a7cf902010-07-26 16:34:32 -0600122static struct omap_hwmod omap3xxx_l3_main_hwmod = {
Benoit Coussonfa983472010-07-26 16:34:29 -0600123 .name = "l3_main",
Paul Walmsley43b40992010-02-22 22:09:34 -0700124 .class = &l3_hwmod_class,
Kevin Hilman4a7cf902010-07-26 16:34:32 -0600125 .masters = omap3xxx_l3_main_masters,
126 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
127 .slaves = omap3xxx_l3_main_slaves,
128 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
Kevin Hilman2eb18752010-07-26 16:34:28 -0600129 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
130 .flags = HWMOD_NO_IDLEST,
Paul Walmsley73591542010-02-22 22:09:32 -0700131};
132
133static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
Kevin Hilman046465b2010-09-27 20:19:30 +0530134static struct omap_hwmod omap3xxx_uart1_hwmod;
135static struct omap_hwmod omap3xxx_uart2_hwmod;
136static struct omap_hwmod omap3xxx_uart3_hwmod;
137static struct omap_hwmod omap3xxx_uart4_hwmod;
Hema HK870ea2b2011-02-17 12:07:18 +0530138static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
Paul Walmsley73591542010-02-22 22:09:32 -0700139
Hema HK870ea2b2011-02-17 12:07:18 +0530140/* l3_core -> usbhsotg interface */
141static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
142 .master = &omap3xxx_usbhsotg_hwmod,
143 .slave = &omap3xxx_l3_main_hwmod,
144 .clk = "core_l3_ick",
145 .user = OCP_USER_MPU,
146};
Paul Walmsley73591542010-02-22 22:09:32 -0700147
Hema HK273ff8c2011-02-17 12:07:19 +0530148/* l3_core -> am35xx_usbhsotg interface */
149static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
150 .master = &am35xx_usbhsotg_hwmod,
151 .slave = &omap3xxx_l3_main_hwmod,
152 .clk = "core_l3_ick",
153 .user = OCP_USER_MPU,
154};
Paul Walmsley73591542010-02-22 22:09:32 -0700155/* L4_CORE -> L4_WKUP interface */
156static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
157 .master = &omap3xxx_l4_core_hwmod,
158 .slave = &omap3xxx_l4_wkup_hwmod,
159 .user = OCP_USER_MPU | OCP_USER_SDMA,
160};
161
Kevin Hilman046465b2010-09-27 20:19:30 +0530162/* L4 CORE -> UART1 interface */
163static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
164 {
165 .pa_start = OMAP3_UART1_BASE,
166 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
167 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
168 },
169};
170
171static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
172 .master = &omap3xxx_l4_core_hwmod,
173 .slave = &omap3xxx_uart1_hwmod,
174 .clk = "uart1_ick",
175 .addr = omap3xxx_uart1_addr_space,
176 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
177 .user = OCP_USER_MPU | OCP_USER_SDMA,
178};
179
180/* L4 CORE -> UART2 interface */
181static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
182 {
183 .pa_start = OMAP3_UART2_BASE,
184 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
185 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
186 },
187};
188
189static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
190 .master = &omap3xxx_l4_core_hwmod,
191 .slave = &omap3xxx_uart2_hwmod,
192 .clk = "uart2_ick",
193 .addr = omap3xxx_uart2_addr_space,
194 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
195 .user = OCP_USER_MPU | OCP_USER_SDMA,
196};
197
198/* L4 PER -> UART3 interface */
199static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
200 {
201 .pa_start = OMAP3_UART3_BASE,
202 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
203 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
204 },
205};
206
207static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
208 .master = &omap3xxx_l4_per_hwmod,
209 .slave = &omap3xxx_uart3_hwmod,
210 .clk = "uart3_ick",
211 .addr = omap3xxx_uart3_addr_space,
212 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
213 .user = OCP_USER_MPU | OCP_USER_SDMA,
214};
215
216/* L4 PER -> UART4 interface */
217static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
218 {
219 .pa_start = OMAP3_UART4_BASE,
220 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
221 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
222 },
223};
224
225static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
226 .master = &omap3xxx_l4_per_hwmod,
227 .slave = &omap3xxx_uart4_hwmod,
228 .clk = "uart4_ick",
229 .addr = omap3xxx_uart4_addr_space,
230 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
231 .user = OCP_USER_MPU | OCP_USER_SDMA,
232};
233
Rajendra Nayak4fe20e92010-09-21 19:37:13 +0530234/* I2C IP block address space length (in bytes) */
235#define OMAP2_I2C_AS_LEN 128
236
237/* L4 CORE -> I2C1 interface */
238static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
239 {
240 .pa_start = 0x48070000,
241 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
242 .flags = ADDR_TYPE_RT,
243 },
244};
245
246static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
247 .master = &omap3xxx_l4_core_hwmod,
248 .slave = &omap3xxx_i2c1_hwmod,
249 .clk = "i2c1_ick",
250 .addr = omap3xxx_i2c1_addr_space,
251 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
252 .fw = {
253 .omap2 = {
254 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
255 .l4_prot_group = 7,
256 .flags = OMAP_FIREWALL_L4,
257 }
258 },
259 .user = OCP_USER_MPU | OCP_USER_SDMA,
260};
261
262/* L4 CORE -> I2C2 interface */
263static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
264 {
265 .pa_start = 0x48072000,
266 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
267 .flags = ADDR_TYPE_RT,
268 },
269};
270
271static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
272 .master = &omap3xxx_l4_core_hwmod,
273 .slave = &omap3xxx_i2c2_hwmod,
274 .clk = "i2c2_ick",
275 .addr = omap3xxx_i2c2_addr_space,
276 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
277 .fw = {
278 .omap2 = {
279 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
280 .l4_prot_group = 7,
281 .flags = OMAP_FIREWALL_L4,
282 }
283 },
284 .user = OCP_USER_MPU | OCP_USER_SDMA,
285};
286
287/* L4 CORE -> I2C3 interface */
288static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
289 {
290 .pa_start = 0x48060000,
291 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
292 .flags = ADDR_TYPE_RT,
293 },
294};
295
296static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
297 .master = &omap3xxx_l4_core_hwmod,
298 .slave = &omap3xxx_i2c3_hwmod,
299 .clk = "i2c3_ick",
300 .addr = omap3xxx_i2c3_addr_space,
301 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
302 .fw = {
303 .omap2 = {
304 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
305 .l4_prot_group = 7,
306 .flags = OMAP_FIREWALL_L4,
307 }
308 },
309 .user = OCP_USER_MPU | OCP_USER_SDMA,
310};
311
Thara Gopinathd3442722010-05-29 22:02:24 +0530312/* L4 CORE -> SR1 interface */
313static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
314 {
315 .pa_start = OMAP34XX_SR1_BASE,
316 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
317 .flags = ADDR_TYPE_RT,
318 },
319};
320
321static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
322 .master = &omap3xxx_l4_core_hwmod,
323 .slave = &omap34xx_sr1_hwmod,
324 .clk = "sr_l4_ick",
325 .addr = omap3_sr1_addr_space,
326 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
327 .user = OCP_USER_MPU,
328};
329
330/* L4 CORE -> SR1 interface */
331static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
332 {
333 .pa_start = OMAP34XX_SR2_BASE,
334 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
335 .flags = ADDR_TYPE_RT,
336 },
337};
338
339static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
340 .master = &omap3xxx_l4_core_hwmod,
341 .slave = &omap34xx_sr2_hwmod,
342 .clk = "sr_l4_ick",
343 .addr = omap3_sr2_addr_space,
344 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
345 .user = OCP_USER_MPU,
346};
347
Hema HK870ea2b2011-02-17 12:07:18 +0530348/*
349* usbhsotg interface data
350*/
351
352static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
353 {
354 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
355 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
356 .flags = ADDR_TYPE_RT
357 },
358};
359
360/* l4_core -> usbhsotg */
361static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
362 .master = &omap3xxx_l4_core_hwmod,
363 .slave = &omap3xxx_usbhsotg_hwmod,
364 .clk = "l4_ick",
365 .addr = omap3xxx_usbhsotg_addrs,
366 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
367 .user = OCP_USER_MPU,
368};
369
370static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
371 &omap3xxx_usbhsotg__l3,
372};
373
374static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
375 &omap3xxx_l4_core__usbhsotg,
376};
377
Hema HK273ff8c2011-02-17 12:07:19 +0530378static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
379 {
380 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
381 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
382 .flags = ADDR_TYPE_RT
383 },
384};
385
386/* l4_core -> usbhsotg */
387static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
388 .master = &omap3xxx_l4_core_hwmod,
389 .slave = &am35xx_usbhsotg_hwmod,
390 .clk = "l4_ick",
391 .addr = am35xx_usbhsotg_addrs,
392 .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
393 .user = OCP_USER_MPU,
394};
395
396static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
397 &am35xx_usbhsotg__l3,
398};
399
400static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
401 &am35xx_l4_core__usbhsotg,
402};
Paul Walmsley73591542010-02-22 22:09:32 -0700403/* Slave interfaces on the L4_CORE interconnect */
404static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
Kevin Hilman4a7cf902010-07-26 16:34:32 -0600405 &omap3xxx_l3_main__l4_core,
Thara Gopinathd3442722010-05-29 22:02:24 +0530406 &omap3_l4_core__sr1,
407 &omap3_l4_core__sr2,
Paul Walmsley73591542010-02-22 22:09:32 -0700408};
409
410/* Master interfaces on the L4_CORE interconnect */
411static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
412 &omap3xxx_l4_core__l4_wkup,
Kevin Hilman046465b2010-09-27 20:19:30 +0530413 &omap3_l4_core__uart1,
414 &omap3_l4_core__uart2,
Rajendra Nayak4fe20e92010-09-21 19:37:13 +0530415 &omap3_l4_core__i2c1,
416 &omap3_l4_core__i2c2,
417 &omap3_l4_core__i2c3,
Paul Walmsley73591542010-02-22 22:09:32 -0700418};
419
420/* L4 CORE */
421static struct omap_hwmod omap3xxx_l4_core_hwmod = {
Benoit Coussonfa983472010-07-26 16:34:29 -0600422 .name = "l4_core",
Paul Walmsley43b40992010-02-22 22:09:34 -0700423 .class = &l4_hwmod_class,
Paul Walmsley73591542010-02-22 22:09:32 -0700424 .masters = omap3xxx_l4_core_masters,
425 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
426 .slaves = omap3xxx_l4_core_slaves,
427 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
Kevin Hilman2eb18752010-07-26 16:34:28 -0600428 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
429 .flags = HWMOD_NO_IDLEST,
Paul Walmsley73591542010-02-22 22:09:32 -0700430};
431
432/* Slave interfaces on the L4_PER interconnect */
433static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
Kevin Hilman4a7cf902010-07-26 16:34:32 -0600434 &omap3xxx_l3_main__l4_per,
Paul Walmsley73591542010-02-22 22:09:32 -0700435};
436
437/* Master interfaces on the L4_PER interconnect */
438static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
Kevin Hilman046465b2010-09-27 20:19:30 +0530439 &omap3_l4_per__uart3,
440 &omap3_l4_per__uart4,
Paul Walmsley73591542010-02-22 22:09:32 -0700441};
442
443/* L4 PER */
444static struct omap_hwmod omap3xxx_l4_per_hwmod = {
Benoit Coussonfa983472010-07-26 16:34:29 -0600445 .name = "l4_per",
Paul Walmsley43b40992010-02-22 22:09:34 -0700446 .class = &l4_hwmod_class,
Paul Walmsley73591542010-02-22 22:09:32 -0700447 .masters = omap3xxx_l4_per_masters,
448 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
449 .slaves = omap3xxx_l4_per_slaves,
450 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
Kevin Hilman2eb18752010-07-26 16:34:28 -0600451 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
452 .flags = HWMOD_NO_IDLEST,
Paul Walmsley73591542010-02-22 22:09:32 -0700453};
454
455/* Slave interfaces on the L4_WKUP interconnect */
456static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
457 &omap3xxx_l4_core__l4_wkup,
458};
459
460/* Master interfaces on the L4_WKUP interconnect */
461static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
462};
463
464/* L4 WKUP */
465static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
Benoit Coussonfa983472010-07-26 16:34:29 -0600466 .name = "l4_wkup",
Paul Walmsley43b40992010-02-22 22:09:34 -0700467 .class = &l4_hwmod_class,
Paul Walmsley73591542010-02-22 22:09:32 -0700468 .masters = omap3xxx_l4_wkup_masters,
469 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
470 .slaves = omap3xxx_l4_wkup_slaves,
471 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
Kevin Hilman2eb18752010-07-26 16:34:28 -0600472 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
473 .flags = HWMOD_NO_IDLEST,
Paul Walmsley73591542010-02-22 22:09:32 -0700474};
475
476/* Master interfaces on the MPU device */
477static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
Kevin Hilman4a7cf902010-07-26 16:34:32 -0600478 &omap3xxx_mpu__l3_main,
Paul Walmsley73591542010-02-22 22:09:32 -0700479};
480
481/* MPU */
482static struct omap_hwmod omap3xxx_mpu_hwmod = {
Benoit Cousson5c2c0292010-05-20 12:31:10 -0600483 .name = "mpu",
Paul Walmsley43b40992010-02-22 22:09:34 -0700484 .class = &mpu_hwmod_class,
Paul Walmsley73591542010-02-22 22:09:32 -0700485 .main_clk = "arm_fck",
486 .masters = omap3xxx_mpu_masters,
487 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
488 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
489};
490
Kevin Hilman540064b2010-07-26 16:34:32 -0600491/*
492 * IVA2_2 interface data
493 */
494
495/* IVA2 <- L3 interface */
496static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
497 .master = &omap3xxx_l3_main_hwmod,
498 .slave = &omap3xxx_iva_hwmod,
499 .clk = "iva2_ck",
500 .user = OCP_USER_MPU | OCP_USER_SDMA,
501};
502
503static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
504 &omap3xxx_l3__iva,
505};
506
507/*
508 * IVA2 (IVA2)
509 */
510
511static struct omap_hwmod omap3xxx_iva_hwmod = {
512 .name = "iva",
513 .class = &iva_hwmod_class,
514 .masters = omap3xxx_iva_masters,
515 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
516 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
517};
518
Thara Gopinathce722d22011-02-23 00:14:05 -0700519/* timer class */
520static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
521 .rev_offs = 0x0000,
522 .sysc_offs = 0x0010,
523 .syss_offs = 0x0014,
524 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
525 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
526 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
527 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
528 .sysc_fields = &omap_hwmod_sysc_type1,
529};
530
531static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
532 .name = "timer",
533 .sysc = &omap3xxx_timer_1ms_sysc,
534 .rev = OMAP_TIMER_IP_VERSION_1,
535};
536
537static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
538 .rev_offs = 0x0000,
539 .sysc_offs = 0x0010,
540 .syss_offs = 0x0014,
541 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
542 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
543 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
544 .sysc_fields = &omap_hwmod_sysc_type1,
545};
546
547static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
548 .name = "timer",
549 .sysc = &omap3xxx_timer_sysc,
550 .rev = OMAP_TIMER_IP_VERSION_1,
551};
552
553/* timer1 */
554static struct omap_hwmod omap3xxx_timer1_hwmod;
555static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
556 { .irq = 37, },
557};
558
559static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
560 {
561 .pa_start = 0x48318000,
562 .pa_end = 0x48318000 + SZ_1K - 1,
563 .flags = ADDR_TYPE_RT
564 },
565};
566
567/* l4_wkup -> timer1 */
568static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
569 .master = &omap3xxx_l4_wkup_hwmod,
570 .slave = &omap3xxx_timer1_hwmod,
571 .clk = "gpt1_ick",
572 .addr = omap3xxx_timer1_addrs,
573 .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
574 .user = OCP_USER_MPU | OCP_USER_SDMA,
575};
576
577/* timer1 slave port */
578static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
579 &omap3xxx_l4_wkup__timer1,
580};
581
582/* timer1 hwmod */
583static struct omap_hwmod omap3xxx_timer1_hwmod = {
584 .name = "timer1",
585 .mpu_irqs = omap3xxx_timer1_mpu_irqs,
586 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
587 .main_clk = "gpt1_fck",
588 .prcm = {
589 .omap2 = {
590 .prcm_reg_id = 1,
591 .module_bit = OMAP3430_EN_GPT1_SHIFT,
592 .module_offs = WKUP_MOD,
593 .idlest_reg_id = 1,
594 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
595 },
596 },
597 .slaves = omap3xxx_timer1_slaves,
598 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
599 .class = &omap3xxx_timer_1ms_hwmod_class,
600 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
601};
602
603/* timer2 */
604static struct omap_hwmod omap3xxx_timer2_hwmod;
605static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
606 { .irq = 38, },
607};
608
609static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
610 {
611 .pa_start = 0x49032000,
612 .pa_end = 0x49032000 + SZ_1K - 1,
613 .flags = ADDR_TYPE_RT
614 },
615};
616
617/* l4_per -> timer2 */
618static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
619 .master = &omap3xxx_l4_per_hwmod,
620 .slave = &omap3xxx_timer2_hwmod,
621 .clk = "gpt2_ick",
622 .addr = omap3xxx_timer2_addrs,
623 .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
624 .user = OCP_USER_MPU | OCP_USER_SDMA,
625};
626
627/* timer2 slave port */
628static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
629 &omap3xxx_l4_per__timer2,
630};
631
632/* timer2 hwmod */
633static struct omap_hwmod omap3xxx_timer2_hwmod = {
634 .name = "timer2",
635 .mpu_irqs = omap3xxx_timer2_mpu_irqs,
636 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
637 .main_clk = "gpt2_fck",
638 .prcm = {
639 .omap2 = {
640 .prcm_reg_id = 1,
641 .module_bit = OMAP3430_EN_GPT2_SHIFT,
642 .module_offs = OMAP3430_PER_MOD,
643 .idlest_reg_id = 1,
644 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
645 },
646 },
647 .slaves = omap3xxx_timer2_slaves,
648 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
649 .class = &omap3xxx_timer_1ms_hwmod_class,
650 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
651};
652
653/* timer3 */
654static struct omap_hwmod omap3xxx_timer3_hwmod;
655static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
656 { .irq = 39, },
657};
658
659static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
660 {
661 .pa_start = 0x49034000,
662 .pa_end = 0x49034000 + SZ_1K - 1,
663 .flags = ADDR_TYPE_RT
664 },
665};
666
667/* l4_per -> timer3 */
668static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
669 .master = &omap3xxx_l4_per_hwmod,
670 .slave = &omap3xxx_timer3_hwmod,
671 .clk = "gpt3_ick",
672 .addr = omap3xxx_timer3_addrs,
673 .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
674 .user = OCP_USER_MPU | OCP_USER_SDMA,
675};
676
677/* timer3 slave port */
678static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
679 &omap3xxx_l4_per__timer3,
680};
681
682/* timer3 hwmod */
683static struct omap_hwmod omap3xxx_timer3_hwmod = {
684 .name = "timer3",
685 .mpu_irqs = omap3xxx_timer3_mpu_irqs,
686 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
687 .main_clk = "gpt3_fck",
688 .prcm = {
689 .omap2 = {
690 .prcm_reg_id = 1,
691 .module_bit = OMAP3430_EN_GPT3_SHIFT,
692 .module_offs = OMAP3430_PER_MOD,
693 .idlest_reg_id = 1,
694 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
695 },
696 },
697 .slaves = omap3xxx_timer3_slaves,
698 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
699 .class = &omap3xxx_timer_hwmod_class,
700 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
701};
702
703/* timer4 */
704static struct omap_hwmod omap3xxx_timer4_hwmod;
705static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
706 { .irq = 40, },
707};
708
709static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
710 {
711 .pa_start = 0x49036000,
712 .pa_end = 0x49036000 + SZ_1K - 1,
713 .flags = ADDR_TYPE_RT
714 },
715};
716
717/* l4_per -> timer4 */
718static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
719 .master = &omap3xxx_l4_per_hwmod,
720 .slave = &omap3xxx_timer4_hwmod,
721 .clk = "gpt4_ick",
722 .addr = omap3xxx_timer4_addrs,
723 .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
724 .user = OCP_USER_MPU | OCP_USER_SDMA,
725};
726
727/* timer4 slave port */
728static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
729 &omap3xxx_l4_per__timer4,
730};
731
732/* timer4 hwmod */
733static struct omap_hwmod omap3xxx_timer4_hwmod = {
734 .name = "timer4",
735 .mpu_irqs = omap3xxx_timer4_mpu_irqs,
736 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
737 .main_clk = "gpt4_fck",
738 .prcm = {
739 .omap2 = {
740 .prcm_reg_id = 1,
741 .module_bit = OMAP3430_EN_GPT4_SHIFT,
742 .module_offs = OMAP3430_PER_MOD,
743 .idlest_reg_id = 1,
744 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
745 },
746 },
747 .slaves = omap3xxx_timer4_slaves,
748 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
749 .class = &omap3xxx_timer_hwmod_class,
750 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
751};
752
753/* timer5 */
754static struct omap_hwmod omap3xxx_timer5_hwmod;
755static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
756 { .irq = 41, },
757};
758
759static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
760 {
761 .pa_start = 0x49038000,
762 .pa_end = 0x49038000 + SZ_1K - 1,
763 .flags = ADDR_TYPE_RT
764 },
765};
766
767/* l4_per -> timer5 */
768static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
769 .master = &omap3xxx_l4_per_hwmod,
770 .slave = &omap3xxx_timer5_hwmod,
771 .clk = "gpt5_ick",
772 .addr = omap3xxx_timer5_addrs,
773 .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
774 .user = OCP_USER_MPU | OCP_USER_SDMA,
775};
776
777/* timer5 slave port */
778static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
779 &omap3xxx_l4_per__timer5,
780};
781
782/* timer5 hwmod */
783static struct omap_hwmod omap3xxx_timer5_hwmod = {
784 .name = "timer5",
785 .mpu_irqs = omap3xxx_timer5_mpu_irqs,
786 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
787 .main_clk = "gpt5_fck",
788 .prcm = {
789 .omap2 = {
790 .prcm_reg_id = 1,
791 .module_bit = OMAP3430_EN_GPT5_SHIFT,
792 .module_offs = OMAP3430_PER_MOD,
793 .idlest_reg_id = 1,
794 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
795 },
796 },
797 .slaves = omap3xxx_timer5_slaves,
798 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
799 .class = &omap3xxx_timer_hwmod_class,
800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
801};
802
803/* timer6 */
804static struct omap_hwmod omap3xxx_timer6_hwmod;
805static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
806 { .irq = 42, },
807};
808
809static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
810 {
811 .pa_start = 0x4903A000,
812 .pa_end = 0x4903A000 + SZ_1K - 1,
813 .flags = ADDR_TYPE_RT
814 },
815};
816
817/* l4_per -> timer6 */
818static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
819 .master = &omap3xxx_l4_per_hwmod,
820 .slave = &omap3xxx_timer6_hwmod,
821 .clk = "gpt6_ick",
822 .addr = omap3xxx_timer6_addrs,
823 .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
824 .user = OCP_USER_MPU | OCP_USER_SDMA,
825};
826
827/* timer6 slave port */
828static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
829 &omap3xxx_l4_per__timer6,
830};
831
832/* timer6 hwmod */
833static struct omap_hwmod omap3xxx_timer6_hwmod = {
834 .name = "timer6",
835 .mpu_irqs = omap3xxx_timer6_mpu_irqs,
836 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
837 .main_clk = "gpt6_fck",
838 .prcm = {
839 .omap2 = {
840 .prcm_reg_id = 1,
841 .module_bit = OMAP3430_EN_GPT6_SHIFT,
842 .module_offs = OMAP3430_PER_MOD,
843 .idlest_reg_id = 1,
844 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
845 },
846 },
847 .slaves = omap3xxx_timer6_slaves,
848 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
849 .class = &omap3xxx_timer_hwmod_class,
850 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
851};
852
853/* timer7 */
854static struct omap_hwmod omap3xxx_timer7_hwmod;
855static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
856 { .irq = 43, },
857};
858
859static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
860 {
861 .pa_start = 0x4903C000,
862 .pa_end = 0x4903C000 + SZ_1K - 1,
863 .flags = ADDR_TYPE_RT
864 },
865};
866
867/* l4_per -> timer7 */
868static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
869 .master = &omap3xxx_l4_per_hwmod,
870 .slave = &omap3xxx_timer7_hwmod,
871 .clk = "gpt7_ick",
872 .addr = omap3xxx_timer7_addrs,
873 .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
874 .user = OCP_USER_MPU | OCP_USER_SDMA,
875};
876
877/* timer7 slave port */
878static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
879 &omap3xxx_l4_per__timer7,
880};
881
882/* timer7 hwmod */
883static struct omap_hwmod omap3xxx_timer7_hwmod = {
884 .name = "timer7",
885 .mpu_irqs = omap3xxx_timer7_mpu_irqs,
886 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
887 .main_clk = "gpt7_fck",
888 .prcm = {
889 .omap2 = {
890 .prcm_reg_id = 1,
891 .module_bit = OMAP3430_EN_GPT7_SHIFT,
892 .module_offs = OMAP3430_PER_MOD,
893 .idlest_reg_id = 1,
894 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
895 },
896 },
897 .slaves = omap3xxx_timer7_slaves,
898 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
899 .class = &omap3xxx_timer_hwmod_class,
900 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
901};
902
903/* timer8 */
904static struct omap_hwmod omap3xxx_timer8_hwmod;
905static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
906 { .irq = 44, },
907};
908
909static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
910 {
911 .pa_start = 0x4903E000,
912 .pa_end = 0x4903E000 + SZ_1K - 1,
913 .flags = ADDR_TYPE_RT
914 },
915};
916
917/* l4_per -> timer8 */
918static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
919 .master = &omap3xxx_l4_per_hwmod,
920 .slave = &omap3xxx_timer8_hwmod,
921 .clk = "gpt8_ick",
922 .addr = omap3xxx_timer8_addrs,
923 .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
924 .user = OCP_USER_MPU | OCP_USER_SDMA,
925};
926
927/* timer8 slave port */
928static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
929 &omap3xxx_l4_per__timer8,
930};
931
932/* timer8 hwmod */
933static struct omap_hwmod omap3xxx_timer8_hwmod = {
934 .name = "timer8",
935 .mpu_irqs = omap3xxx_timer8_mpu_irqs,
936 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
937 .main_clk = "gpt8_fck",
938 .prcm = {
939 .omap2 = {
940 .prcm_reg_id = 1,
941 .module_bit = OMAP3430_EN_GPT8_SHIFT,
942 .module_offs = OMAP3430_PER_MOD,
943 .idlest_reg_id = 1,
944 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
945 },
946 },
947 .slaves = omap3xxx_timer8_slaves,
948 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
949 .class = &omap3xxx_timer_hwmod_class,
950 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
951};
952
953/* timer9 */
954static struct omap_hwmod omap3xxx_timer9_hwmod;
955static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
956 { .irq = 45, },
957};
958
959static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
960 {
961 .pa_start = 0x49040000,
962 .pa_end = 0x49040000 + SZ_1K - 1,
963 .flags = ADDR_TYPE_RT
964 },
965};
966
967/* l4_per -> timer9 */
968static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
969 .master = &omap3xxx_l4_per_hwmod,
970 .slave = &omap3xxx_timer9_hwmod,
971 .clk = "gpt9_ick",
972 .addr = omap3xxx_timer9_addrs,
973 .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
974 .user = OCP_USER_MPU | OCP_USER_SDMA,
975};
976
977/* timer9 slave port */
978static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
979 &omap3xxx_l4_per__timer9,
980};
981
982/* timer9 hwmod */
983static struct omap_hwmod omap3xxx_timer9_hwmod = {
984 .name = "timer9",
985 .mpu_irqs = omap3xxx_timer9_mpu_irqs,
986 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
987 .main_clk = "gpt9_fck",
988 .prcm = {
989 .omap2 = {
990 .prcm_reg_id = 1,
991 .module_bit = OMAP3430_EN_GPT9_SHIFT,
992 .module_offs = OMAP3430_PER_MOD,
993 .idlest_reg_id = 1,
994 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
995 },
996 },
997 .slaves = omap3xxx_timer9_slaves,
998 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
999 .class = &omap3xxx_timer_hwmod_class,
1000 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1001};
1002
1003/* timer10 */
1004static struct omap_hwmod omap3xxx_timer10_hwmod;
1005static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1006 { .irq = 46, },
1007};
1008
1009static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1010 {
1011 .pa_start = 0x48086000,
1012 .pa_end = 0x48086000 + SZ_1K - 1,
1013 .flags = ADDR_TYPE_RT
1014 },
1015};
1016
1017/* l4_core -> timer10 */
1018static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1019 .master = &omap3xxx_l4_core_hwmod,
1020 .slave = &omap3xxx_timer10_hwmod,
1021 .clk = "gpt10_ick",
1022 .addr = omap3xxx_timer10_addrs,
1023 .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
1024 .user = OCP_USER_MPU | OCP_USER_SDMA,
1025};
1026
1027/* timer10 slave port */
1028static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1029 &omap3xxx_l4_core__timer10,
1030};
1031
1032/* timer10 hwmod */
1033static struct omap_hwmod omap3xxx_timer10_hwmod = {
1034 .name = "timer10",
1035 .mpu_irqs = omap3xxx_timer10_mpu_irqs,
1036 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1037 .main_clk = "gpt10_fck",
1038 .prcm = {
1039 .omap2 = {
1040 .prcm_reg_id = 1,
1041 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1042 .module_offs = CORE_MOD,
1043 .idlest_reg_id = 1,
1044 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1045 },
1046 },
1047 .slaves = omap3xxx_timer10_slaves,
1048 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1049 .class = &omap3xxx_timer_1ms_hwmod_class,
1050 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1051};
1052
1053/* timer11 */
1054static struct omap_hwmod omap3xxx_timer11_hwmod;
1055static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1056 { .irq = 47, },
1057};
1058
1059static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1060 {
1061 .pa_start = 0x48088000,
1062 .pa_end = 0x48088000 + SZ_1K - 1,
1063 .flags = ADDR_TYPE_RT
1064 },
1065};
1066
1067/* l4_core -> timer11 */
1068static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1069 .master = &omap3xxx_l4_core_hwmod,
1070 .slave = &omap3xxx_timer11_hwmod,
1071 .clk = "gpt11_ick",
1072 .addr = omap3xxx_timer11_addrs,
1073 .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
1074 .user = OCP_USER_MPU | OCP_USER_SDMA,
1075};
1076
1077/* timer11 slave port */
1078static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1079 &omap3xxx_l4_core__timer11,
1080};
1081
1082/* timer11 hwmod */
1083static struct omap_hwmod omap3xxx_timer11_hwmod = {
1084 .name = "timer11",
1085 .mpu_irqs = omap3xxx_timer11_mpu_irqs,
1086 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1087 .main_clk = "gpt11_fck",
1088 .prcm = {
1089 .omap2 = {
1090 .prcm_reg_id = 1,
1091 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1092 .module_offs = CORE_MOD,
1093 .idlest_reg_id = 1,
1094 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1095 },
1096 },
1097 .slaves = omap3xxx_timer11_slaves,
1098 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1099 .class = &omap3xxx_timer_hwmod_class,
1100 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1101};
1102
1103/* timer12*/
1104static struct omap_hwmod omap3xxx_timer12_hwmod;
1105static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1106 { .irq = 95, },
1107};
1108
1109static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1110 {
1111 .pa_start = 0x48304000,
1112 .pa_end = 0x48304000 + SZ_1K - 1,
1113 .flags = ADDR_TYPE_RT
1114 },
1115};
1116
1117/* l4_core -> timer12 */
1118static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1119 .master = &omap3xxx_l4_core_hwmod,
1120 .slave = &omap3xxx_timer12_hwmod,
1121 .clk = "gpt12_ick",
1122 .addr = omap3xxx_timer12_addrs,
1123 .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
1124 .user = OCP_USER_MPU | OCP_USER_SDMA,
1125};
1126
1127/* timer12 slave port */
1128static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1129 &omap3xxx_l4_core__timer12,
1130};
1131
1132/* timer12 hwmod */
1133static struct omap_hwmod omap3xxx_timer12_hwmod = {
1134 .name = "timer12",
1135 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1136 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1137 .main_clk = "gpt12_fck",
1138 .prcm = {
1139 .omap2 = {
1140 .prcm_reg_id = 1,
1141 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1142 .module_offs = WKUP_MOD,
1143 .idlest_reg_id = 1,
1144 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1145 },
1146 },
1147 .slaves = omap3xxx_timer12_slaves,
1148 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1149 .class = &omap3xxx_timer_hwmod_class,
1150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1151};
1152
Varadarajan, Charulatha6b667f82010-09-23 20:02:38 +05301153/* l4_wkup -> wd_timer2 */
1154static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1155 {
1156 .pa_start = 0x48314000,
1157 .pa_end = 0x4831407f,
1158 .flags = ADDR_TYPE_RT
1159 },
1160};
1161
1162static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1163 .master = &omap3xxx_l4_wkup_hwmod,
1164 .slave = &omap3xxx_wd_timer2_hwmod,
1165 .clk = "wdt2_ick",
1166 .addr = omap3xxx_wd_timer2_addrs,
1167 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
1168 .user = OCP_USER_MPU | OCP_USER_SDMA,
1169};
1170
1171/*
1172 * 'wd_timer' class
1173 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1174 * overflow condition
1175 */
1176
1177static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1178 .rev_offs = 0x0000,
1179 .sysc_offs = 0x0010,
1180 .syss_offs = 0x0014,
1181 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1182 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1183 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
1184 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1185 .sysc_fields = &omap_hwmod_sysc_type1,
1186};
1187
Rajendra Nayak4fe20e92010-09-21 19:37:13 +05301188/* I2C common */
1189static struct omap_hwmod_class_sysconfig i2c_sysc = {
1190 .rev_offs = 0x00,
1191 .sysc_offs = 0x20,
1192 .syss_offs = 0x10,
1193 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1194 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1195 SYSC_HAS_AUTOIDLE),
1196 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1197 .sysc_fields = &omap_hwmod_sysc_type1,
1198};
1199
Varadarajan, Charulatha6b667f82010-09-23 20:02:38 +05301200static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
Paul Walmsleyff2516f2010-12-21 15:39:15 -07001201 .name = "wd_timer",
1202 .sysc = &omap3xxx_wd_timer_sysc,
1203 .pre_shutdown = &omap2_wd_timer_disable
Varadarajan, Charulatha6b667f82010-09-23 20:02:38 +05301204};
1205
1206/* wd_timer2 */
1207static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1208 &omap3xxx_l4_wkup__wd_timer2,
1209};
1210
1211static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1212 .name = "wd_timer2",
1213 .class = &omap3xxx_wd_timer_hwmod_class,
1214 .main_clk = "wdt2_fck",
1215 .prcm = {
1216 .omap2 = {
1217 .prcm_reg_id = 1,
1218 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1219 .module_offs = WKUP_MOD,
1220 .idlest_reg_id = 1,
1221 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1222 },
1223 },
1224 .slaves = omap3xxx_wd_timer2_slaves,
1225 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1227};
1228
Kevin Hilman046465b2010-09-27 20:19:30 +05301229/* UART common */
1230
1231static struct omap_hwmod_class_sysconfig uart_sysc = {
1232 .rev_offs = 0x50,
1233 .sysc_offs = 0x54,
1234 .syss_offs = 0x58,
1235 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1236 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1237 SYSC_HAS_AUTOIDLE),
1238 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1239 .sysc_fields = &omap_hwmod_sysc_type1,
1240};
1241
1242static struct omap_hwmod_class uart_class = {
1243 .name = "uart",
1244 .sysc = &uart_sysc,
1245};
1246
1247/* UART1 */
1248
1249static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1250 { .irq = INT_24XX_UART1_IRQ, },
1251};
1252
1253static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1254 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1255 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1256};
1257
1258static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1259 &omap3_l4_core__uart1,
1260};
1261
1262static struct omap_hwmod omap3xxx_uart1_hwmod = {
1263 .name = "uart1",
1264 .mpu_irqs = uart1_mpu_irqs,
1265 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
1266 .sdma_reqs = uart1_sdma_reqs,
1267 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1268 .main_clk = "uart1_fck",
1269 .prcm = {
1270 .omap2 = {
1271 .module_offs = CORE_MOD,
1272 .prcm_reg_id = 1,
1273 .module_bit = OMAP3430_EN_UART1_SHIFT,
1274 .idlest_reg_id = 1,
1275 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1276 },
1277 },
1278 .slaves = omap3xxx_uart1_slaves,
1279 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1280 .class = &uart_class,
1281 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1282};
1283
1284/* UART2 */
1285
1286static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1287 { .irq = INT_24XX_UART2_IRQ, },
1288};
1289
1290static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1291 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1292 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1293};
1294
1295static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1296 &omap3_l4_core__uart2,
1297};
1298
1299static struct omap_hwmod omap3xxx_uart2_hwmod = {
1300 .name = "uart2",
1301 .mpu_irqs = uart2_mpu_irqs,
1302 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
1303 .sdma_reqs = uart2_sdma_reqs,
1304 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1305 .main_clk = "uart2_fck",
1306 .prcm = {
1307 .omap2 = {
1308 .module_offs = CORE_MOD,
1309 .prcm_reg_id = 1,
1310 .module_bit = OMAP3430_EN_UART2_SHIFT,
1311 .idlest_reg_id = 1,
1312 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1313 },
1314 },
1315 .slaves = omap3xxx_uart2_slaves,
1316 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1317 .class = &uart_class,
1318 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1319};
1320
1321/* UART3 */
1322
1323static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1324 { .irq = INT_24XX_UART3_IRQ, },
1325};
1326
1327static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1328 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1329 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1330};
1331
1332static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1333 &omap3_l4_per__uart3,
1334};
1335
1336static struct omap_hwmod omap3xxx_uart3_hwmod = {
1337 .name = "uart3",
1338 .mpu_irqs = uart3_mpu_irqs,
1339 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
1340 .sdma_reqs = uart3_sdma_reqs,
1341 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1342 .main_clk = "uart3_fck",
1343 .prcm = {
1344 .omap2 = {
1345 .module_offs = OMAP3430_PER_MOD,
1346 .prcm_reg_id = 1,
1347 .module_bit = OMAP3430_EN_UART3_SHIFT,
1348 .idlest_reg_id = 1,
1349 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1350 },
1351 },
1352 .slaves = omap3xxx_uart3_slaves,
1353 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1354 .class = &uart_class,
1355 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1356};
1357
1358/* UART4 */
1359
1360static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1361 { .irq = INT_36XX_UART4_IRQ, },
1362};
1363
1364static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1365 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1366 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1367};
1368
1369static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1370 &omap3_l4_per__uart4,
1371};
1372
1373static struct omap_hwmod omap3xxx_uart4_hwmod = {
1374 .name = "uart4",
1375 .mpu_irqs = uart4_mpu_irqs,
1376 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
1377 .sdma_reqs = uart4_sdma_reqs,
1378 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
1379 .main_clk = "uart4_fck",
1380 .prcm = {
1381 .omap2 = {
1382 .module_offs = OMAP3430_PER_MOD,
1383 .prcm_reg_id = 1,
1384 .module_bit = OMAP3630_EN_UART4_SHIFT,
1385 .idlest_reg_id = 1,
1386 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1387 },
1388 },
1389 .slaves = omap3xxx_uart4_slaves,
1390 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1391 .class = &uart_class,
1392 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1393};
1394
Rajendra Nayak4fe20e92010-09-21 19:37:13 +05301395static struct omap_hwmod_class i2c_class = {
1396 .name = "i2c",
1397 .sysc = &i2c_sysc,
1398};
1399
Senthilvadivu Guruswamye04d9e12011-01-24 06:21:51 +00001400/*
1401 * 'dss' class
1402 * display sub-system
1403 */
1404
1405static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1406 .rev_offs = 0x0000,
1407 .sysc_offs = 0x0010,
1408 .syss_offs = 0x0014,
1409 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1410 .sysc_fields = &omap_hwmod_sysc_type1,
1411};
1412
1413static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1414 .name = "dss",
1415 .sysc = &omap3xxx_dss_sysc,
1416};
1417
1418/* dss */
1419static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
1420 { .irq = 25 },
1421};
1422
1423static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1424 { .name = "dispc", .dma_req = 5 },
1425 { .name = "dsi1", .dma_req = 74 },
1426};
1427
1428/* dss */
1429/* dss master ports */
1430static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1431 &omap3xxx_dss__l3,
1432};
1433
1434static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
1435 {
1436 .pa_start = 0x48050000,
1437 .pa_end = 0x480503FF,
1438 .flags = ADDR_TYPE_RT
1439 },
1440};
1441
1442/* l4_core -> dss */
1443static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1444 .master = &omap3xxx_l4_core_hwmod,
1445 .slave = &omap3430es1_dss_core_hwmod,
1446 .clk = "dss_ick",
1447 .addr = omap3xxx_dss_addrs,
1448 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1449 .fw = {
1450 .omap2 = {
1451 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1452 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1453 .flags = OMAP_FIREWALL_L4,
1454 }
1455 },
1456 .user = OCP_USER_MPU | OCP_USER_SDMA,
1457};
1458
1459static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1460 .master = &omap3xxx_l4_core_hwmod,
1461 .slave = &omap3xxx_dss_core_hwmod,
1462 .clk = "dss_ick",
1463 .addr = omap3xxx_dss_addrs,
1464 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1465 .fw = {
1466 .omap2 = {
1467 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1468 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1469 .flags = OMAP_FIREWALL_L4,
1470 }
1471 },
1472 .user = OCP_USER_MPU | OCP_USER_SDMA,
1473};
1474
1475/* dss slave ports */
1476static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1477 &omap3430es1_l4_core__dss,
1478};
1479
1480static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1481 &omap3xxx_l4_core__dss,
1482};
1483
1484static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1485 { .role = "tv_clk", .clk = "dss_tv_fck" },
1486 { .role = "dssclk", .clk = "dss_96m_fck" },
1487 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1488};
1489
1490static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1491 .name = "dss_core",
1492 .class = &omap3xxx_dss_hwmod_class,
1493 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1494 .mpu_irqs = omap3xxx_dss_irqs,
1495 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
1496 .sdma_reqs = omap3xxx_dss_sdma_chs,
1497 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1498
1499 .prcm = {
1500 .omap2 = {
1501 .prcm_reg_id = 1,
1502 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1503 .module_offs = OMAP3430_DSS_MOD,
1504 .idlest_reg_id = 1,
1505 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1506 },
1507 },
1508 .opt_clks = dss_opt_clks,
1509 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1510 .slaves = omap3430es1_dss_slaves,
1511 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1512 .masters = omap3xxx_dss_masters,
1513 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1514 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1515 .flags = HWMOD_NO_IDLEST,
1516};
1517
1518static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1519 .name = "dss_core",
1520 .class = &omap3xxx_dss_hwmod_class,
1521 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1522 .mpu_irqs = omap3xxx_dss_irqs,
1523 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
1524 .sdma_reqs = omap3xxx_dss_sdma_chs,
1525 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1526
1527 .prcm = {
1528 .omap2 = {
1529 .prcm_reg_id = 1,
1530 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1531 .module_offs = OMAP3430_DSS_MOD,
1532 .idlest_reg_id = 1,
1533 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1534 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1535 },
1536 },
1537 .opt_clks = dss_opt_clks,
1538 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1539 .slaves = omap3xxx_dss_slaves,
1540 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1541 .masters = omap3xxx_dss_masters,
1542 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1543 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1544 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1545};
1546
1547/*
1548 * 'dispc' class
1549 * display controller
1550 */
1551
1552static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1553 .rev_offs = 0x0000,
1554 .sysc_offs = 0x0010,
1555 .syss_offs = 0x0014,
1556 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1557 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1558 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1559 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1560 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1561 .sysc_fields = &omap_hwmod_sysc_type1,
1562};
1563
1564static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1565 .name = "dispc",
1566 .sysc = &omap3xxx_dispc_sysc,
1567};
1568
1569static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
1570 {
1571 .pa_start = 0x48050400,
1572 .pa_end = 0x480507FF,
1573 .flags = ADDR_TYPE_RT
1574 },
1575};
1576
1577/* l4_core -> dss_dispc */
1578static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1579 .master = &omap3xxx_l4_core_hwmod,
1580 .slave = &omap3xxx_dss_dispc_hwmod,
1581 .clk = "dss_ick",
1582 .addr = omap3xxx_dss_dispc_addrs,
1583 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
1584 .fw = {
1585 .omap2 = {
1586 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1587 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1588 .flags = OMAP_FIREWALL_L4,
1589 }
1590 },
1591 .user = OCP_USER_MPU | OCP_USER_SDMA,
1592};
1593
1594/* dss_dispc slave ports */
1595static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1596 &omap3xxx_l4_core__dss_dispc,
1597};
1598
1599static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1600 .name = "dss_dispc",
1601 .class = &omap3xxx_dispc_hwmod_class,
1602 .main_clk = "dss1_alwon_fck",
1603 .prcm = {
1604 .omap2 = {
1605 .prcm_reg_id = 1,
1606 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1607 .module_offs = OMAP3430_DSS_MOD,
1608 },
1609 },
1610 .slaves = omap3xxx_dss_dispc_slaves,
1611 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1612 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1613 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1614 CHIP_GE_OMAP3630ES1_1),
1615 .flags = HWMOD_NO_IDLEST,
1616};
1617
1618/*
1619 * 'dsi' class
1620 * display serial interface controller
1621 */
1622
1623static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1624 .name = "dsi",
1625};
1626
1627/* dss_dsi1 */
1628static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1629 {
1630 .pa_start = 0x4804FC00,
1631 .pa_end = 0x4804FFFF,
1632 .flags = ADDR_TYPE_RT
1633 },
1634};
1635
1636/* l4_core -> dss_dsi1 */
1637static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1638 .master = &omap3xxx_l4_core_hwmod,
1639 .slave = &omap3xxx_dss_dsi1_hwmod,
1640 .addr = omap3xxx_dss_dsi1_addrs,
1641 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1642 .fw = {
1643 .omap2 = {
1644 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1645 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1646 .flags = OMAP_FIREWALL_L4,
1647 }
1648 },
1649 .user = OCP_USER_MPU | OCP_USER_SDMA,
1650};
1651
1652/* dss_dsi1 slave ports */
1653static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1654 &omap3xxx_l4_core__dss_dsi1,
1655};
1656
1657static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1658 .name = "dss_dsi1",
1659 .class = &omap3xxx_dsi_hwmod_class,
1660 .main_clk = "dss1_alwon_fck",
1661 .prcm = {
1662 .omap2 = {
1663 .prcm_reg_id = 1,
1664 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1665 .module_offs = OMAP3430_DSS_MOD,
1666 },
1667 },
1668 .slaves = omap3xxx_dss_dsi1_slaves,
1669 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1670 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1671 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1672 CHIP_GE_OMAP3630ES1_1),
1673 .flags = HWMOD_NO_IDLEST,
1674};
1675
1676/*
1677 * 'rfbi' class
1678 * remote frame buffer interface
1679 */
1680
1681static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1682 .rev_offs = 0x0000,
1683 .sysc_offs = 0x0010,
1684 .syss_offs = 0x0014,
1685 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1686 SYSC_HAS_AUTOIDLE),
1687 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1688 .sysc_fields = &omap_hwmod_sysc_type1,
1689};
1690
1691static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1692 .name = "rfbi",
1693 .sysc = &omap3xxx_rfbi_sysc,
1694};
1695
1696static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1697 {
1698 .pa_start = 0x48050800,
1699 .pa_end = 0x48050BFF,
1700 .flags = ADDR_TYPE_RT
1701 },
1702};
1703
1704/* l4_core -> dss_rfbi */
1705static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1706 .master = &omap3xxx_l4_core_hwmod,
1707 .slave = &omap3xxx_dss_rfbi_hwmod,
1708 .clk = "dss_ick",
1709 .addr = omap3xxx_dss_rfbi_addrs,
1710 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1711 .fw = {
1712 .omap2 = {
1713 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1714 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1715 .flags = OMAP_FIREWALL_L4,
1716 }
1717 },
1718 .user = OCP_USER_MPU | OCP_USER_SDMA,
1719};
1720
1721/* dss_rfbi slave ports */
1722static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1723 &omap3xxx_l4_core__dss_rfbi,
1724};
1725
1726static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1727 .name = "dss_rfbi",
1728 .class = &omap3xxx_rfbi_hwmod_class,
1729 .main_clk = "dss1_alwon_fck",
1730 .prcm = {
1731 .omap2 = {
1732 .prcm_reg_id = 1,
1733 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1734 .module_offs = OMAP3430_DSS_MOD,
1735 },
1736 },
1737 .slaves = omap3xxx_dss_rfbi_slaves,
1738 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1739 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1740 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1741 CHIP_GE_OMAP3630ES1_1),
1742 .flags = HWMOD_NO_IDLEST,
1743};
1744
1745/*
1746 * 'venc' class
1747 * video encoder
1748 */
1749
1750static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1751 .name = "venc",
1752};
1753
1754/* dss_venc */
1755static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1756 {
1757 .pa_start = 0x48050C00,
1758 .pa_end = 0x48050FFF,
1759 .flags = ADDR_TYPE_RT
1760 },
1761};
1762
1763/* l4_core -> dss_venc */
1764static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1765 .master = &omap3xxx_l4_core_hwmod,
1766 .slave = &omap3xxx_dss_venc_hwmod,
1767 .clk = "dss_tv_fck",
1768 .addr = omap3xxx_dss_venc_addrs,
1769 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1770 .fw = {
1771 .omap2 = {
1772 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1773 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1774 .flags = OMAP_FIREWALL_L4,
1775 }
1776 },
1777 .user = OCP_USER_MPU | OCP_USER_SDMA,
1778};
1779
1780/* dss_venc slave ports */
1781static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1782 &omap3xxx_l4_core__dss_venc,
1783};
1784
1785static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1786 .name = "dss_venc",
1787 .class = &omap3xxx_venc_hwmod_class,
1788 .main_clk = "dss1_alwon_fck",
1789 .prcm = {
1790 .omap2 = {
1791 .prcm_reg_id = 1,
1792 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1793 .module_offs = OMAP3430_DSS_MOD,
1794 },
1795 },
1796 .slaves = omap3xxx_dss_venc_slaves,
1797 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1798 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1799 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1800 CHIP_GE_OMAP3630ES1_1),
1801 .flags = HWMOD_NO_IDLEST,
1802};
1803
Rajendra Nayak4fe20e92010-09-21 19:37:13 +05301804/* I2C1 */
1805
1806static struct omap_i2c_dev_attr i2c1_dev_attr = {
1807 .fifo_depth = 8, /* bytes */
1808};
1809
1810static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1811 { .irq = INT_24XX_I2C1_IRQ, },
1812};
1813
1814static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1815 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1816 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1817};
1818
1819static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1820 &omap3_l4_core__i2c1,
1821};
1822
1823static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1824 .name = "i2c1",
1825 .mpu_irqs = i2c1_mpu_irqs,
1826 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
1827 .sdma_reqs = i2c1_sdma_reqs,
1828 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1829 .main_clk = "i2c1_fck",
1830 .prcm = {
1831 .omap2 = {
1832 .module_offs = CORE_MOD,
1833 .prcm_reg_id = 1,
1834 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1835 .idlest_reg_id = 1,
1836 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1837 },
1838 },
1839 .slaves = omap3xxx_i2c1_slaves,
1840 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1841 .class = &i2c_class,
1842 .dev_attr = &i2c1_dev_attr,
1843 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1844};
1845
1846/* I2C2 */
1847
1848static struct omap_i2c_dev_attr i2c2_dev_attr = {
1849 .fifo_depth = 8, /* bytes */
1850};
1851
1852static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1853 { .irq = INT_24XX_I2C2_IRQ, },
1854};
1855
1856static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1857 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1858 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1859};
1860
1861static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1862 &omap3_l4_core__i2c2,
1863};
1864
1865static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1866 .name = "i2c2",
1867 .mpu_irqs = i2c2_mpu_irqs,
1868 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
1869 .sdma_reqs = i2c2_sdma_reqs,
1870 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1871 .main_clk = "i2c2_fck",
1872 .prcm = {
1873 .omap2 = {
1874 .module_offs = CORE_MOD,
1875 .prcm_reg_id = 1,
1876 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1877 .idlest_reg_id = 1,
1878 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1879 },
1880 },
1881 .slaves = omap3xxx_i2c2_slaves,
1882 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1883 .class = &i2c_class,
1884 .dev_attr = &i2c2_dev_attr,
1885 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1886};
1887
1888/* I2C3 */
1889
1890static struct omap_i2c_dev_attr i2c3_dev_attr = {
1891 .fifo_depth = 64, /* bytes */
1892};
1893
1894static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1895 { .irq = INT_34XX_I2C3_IRQ, },
1896};
1897
1898static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1899 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1900 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1901};
1902
1903static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1904 &omap3_l4_core__i2c3,
1905};
1906
1907static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1908 .name = "i2c3",
1909 .mpu_irqs = i2c3_mpu_irqs,
1910 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
1911 .sdma_reqs = i2c3_sdma_reqs,
1912 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
1913 .main_clk = "i2c3_fck",
1914 .prcm = {
1915 .omap2 = {
1916 .module_offs = CORE_MOD,
1917 .prcm_reg_id = 1,
1918 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1919 .idlest_reg_id = 1,
1920 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1921 },
1922 },
1923 .slaves = omap3xxx_i2c3_slaves,
1924 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1925 .class = &i2c_class,
1926 .dev_attr = &i2c3_dev_attr,
1927 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1928};
1929
Varadarajan, Charulatha70034d32010-12-07 16:26:57 -08001930/* l4_wkup -> gpio1 */
1931static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1932 {
1933 .pa_start = 0x48310000,
1934 .pa_end = 0x483101ff,
1935 .flags = ADDR_TYPE_RT
1936 },
1937};
1938
1939static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1940 .master = &omap3xxx_l4_wkup_hwmod,
1941 .slave = &omap3xxx_gpio1_hwmod,
1942 .addr = omap3xxx_gpio1_addrs,
1943 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
1944 .user = OCP_USER_MPU | OCP_USER_SDMA,
1945};
1946
1947/* l4_per -> gpio2 */
1948static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1949 {
1950 .pa_start = 0x49050000,
1951 .pa_end = 0x490501ff,
1952 .flags = ADDR_TYPE_RT
1953 },
1954};
1955
1956static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1957 .master = &omap3xxx_l4_per_hwmod,
1958 .slave = &omap3xxx_gpio2_hwmod,
1959 .addr = omap3xxx_gpio2_addrs,
1960 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
1961 .user = OCP_USER_MPU | OCP_USER_SDMA,
1962};
1963
1964/* l4_per -> gpio3 */
1965static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1966 {
1967 .pa_start = 0x49052000,
1968 .pa_end = 0x490521ff,
1969 .flags = ADDR_TYPE_RT
1970 },
1971};
1972
1973static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1974 .master = &omap3xxx_l4_per_hwmod,
1975 .slave = &omap3xxx_gpio3_hwmod,
1976 .addr = omap3xxx_gpio3_addrs,
1977 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
1978 .user = OCP_USER_MPU | OCP_USER_SDMA,
1979};
1980
1981/* l4_per -> gpio4 */
1982static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1983 {
1984 .pa_start = 0x49054000,
1985 .pa_end = 0x490541ff,
1986 .flags = ADDR_TYPE_RT
1987 },
1988};
1989
1990static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1991 .master = &omap3xxx_l4_per_hwmod,
1992 .slave = &omap3xxx_gpio4_hwmod,
1993 .addr = omap3xxx_gpio4_addrs,
1994 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
1995 .user = OCP_USER_MPU | OCP_USER_SDMA,
1996};
1997
1998/* l4_per -> gpio5 */
1999static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2000 {
2001 .pa_start = 0x49056000,
2002 .pa_end = 0x490561ff,
2003 .flags = ADDR_TYPE_RT
2004 },
2005};
2006
2007static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2008 .master = &omap3xxx_l4_per_hwmod,
2009 .slave = &omap3xxx_gpio5_hwmod,
2010 .addr = omap3xxx_gpio5_addrs,
2011 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
2012 .user = OCP_USER_MPU | OCP_USER_SDMA,
2013};
2014
2015/* l4_per -> gpio6 */
2016static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2017 {
2018 .pa_start = 0x49058000,
2019 .pa_end = 0x490581ff,
2020 .flags = ADDR_TYPE_RT
2021 },
2022};
2023
2024static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2025 .master = &omap3xxx_l4_per_hwmod,
2026 .slave = &omap3xxx_gpio6_hwmod,
2027 .addr = omap3xxx_gpio6_addrs,
2028 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
2029 .user = OCP_USER_MPU | OCP_USER_SDMA,
2030};
2031
2032/*
2033 * 'gpio' class
2034 * general purpose io module
2035 */
2036
2037static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
2038 .rev_offs = 0x0000,
2039 .sysc_offs = 0x0010,
2040 .syss_offs = 0x0014,
2041 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2042 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2043 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2044 .sysc_fields = &omap_hwmod_sysc_type1,
2045};
2046
2047static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
2048 .name = "gpio",
2049 .sysc = &omap3xxx_gpio_sysc,
2050 .rev = 1,
2051};
2052
2053/* gpio_dev_attr*/
2054static struct omap_gpio_dev_attr gpio_dev_attr = {
2055 .bank_width = 32,
2056 .dbck_flag = true,
2057};
2058
2059/* gpio1 */
2060static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2061 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2062};
2063
2064static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2065 { .role = "dbclk", .clk = "gpio1_dbck", },
2066};
2067
2068static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2069 &omap3xxx_l4_wkup__gpio1,
2070};
2071
2072static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2073 .name = "gpio1",
2074 .mpu_irqs = omap3xxx_gpio1_irqs,
2075 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2076 .main_clk = "gpio1_ick",
2077 .opt_clks = gpio1_opt_clks,
2078 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
2079 .prcm = {
2080 .omap2 = {
2081 .prcm_reg_id = 1,
2082 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
2083 .module_offs = WKUP_MOD,
2084 .idlest_reg_id = 1,
2085 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
2086 },
2087 },
2088 .slaves = omap3xxx_gpio1_slaves,
2089 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
2090 .class = &omap3xxx_gpio_hwmod_class,
2091 .dev_attr = &gpio_dev_attr,
2092 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2093};
2094
2095/* gpio2 */
2096static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2097 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2098};
2099
2100static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2101 { .role = "dbclk", .clk = "gpio2_dbck", },
2102};
2103
2104static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2105 &omap3xxx_l4_per__gpio2,
2106};
2107
2108static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2109 .name = "gpio2",
2110 .mpu_irqs = omap3xxx_gpio2_irqs,
2111 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2112 .main_clk = "gpio2_ick",
2113 .opt_clks = gpio2_opt_clks,
2114 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
2115 .prcm = {
2116 .omap2 = {
2117 .prcm_reg_id = 1,
2118 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2119 .module_offs = OMAP3430_PER_MOD,
2120 .idlest_reg_id = 1,
2121 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2122 },
2123 },
2124 .slaves = omap3xxx_gpio2_slaves,
2125 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2126 .class = &omap3xxx_gpio_hwmod_class,
2127 .dev_attr = &gpio_dev_attr,
2128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2129};
2130
2131/* gpio3 */
2132static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2133 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2134};
2135
2136static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2137 { .role = "dbclk", .clk = "gpio3_dbck", },
2138};
2139
2140static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2141 &omap3xxx_l4_per__gpio3,
2142};
2143
2144static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2145 .name = "gpio3",
2146 .mpu_irqs = omap3xxx_gpio3_irqs,
2147 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2148 .main_clk = "gpio3_ick",
2149 .opt_clks = gpio3_opt_clks,
2150 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
2151 .prcm = {
2152 .omap2 = {
2153 .prcm_reg_id = 1,
2154 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2155 .module_offs = OMAP3430_PER_MOD,
2156 .idlest_reg_id = 1,
2157 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2158 },
2159 },
2160 .slaves = omap3xxx_gpio3_slaves,
2161 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2162 .class = &omap3xxx_gpio_hwmod_class,
2163 .dev_attr = &gpio_dev_attr,
2164 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2165};
2166
2167/* gpio4 */
2168static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2169 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2170};
2171
2172static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2173 { .role = "dbclk", .clk = "gpio4_dbck", },
2174};
2175
2176static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2177 &omap3xxx_l4_per__gpio4,
2178};
2179
2180static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2181 .name = "gpio4",
2182 .mpu_irqs = omap3xxx_gpio4_irqs,
2183 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2184 .main_clk = "gpio4_ick",
2185 .opt_clks = gpio4_opt_clks,
2186 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2187 .prcm = {
2188 .omap2 = {
2189 .prcm_reg_id = 1,
2190 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2191 .module_offs = OMAP3430_PER_MOD,
2192 .idlest_reg_id = 1,
2193 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2194 },
2195 },
2196 .slaves = omap3xxx_gpio4_slaves,
2197 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2198 .class = &omap3xxx_gpio_hwmod_class,
2199 .dev_attr = &gpio_dev_attr,
2200 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2201};
2202
2203/* gpio5 */
2204static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2205 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2206};
2207
2208static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2209 { .role = "dbclk", .clk = "gpio5_dbck", },
2210};
2211
2212static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2213 &omap3xxx_l4_per__gpio5,
2214};
2215
2216static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2217 .name = "gpio5",
2218 .mpu_irqs = omap3xxx_gpio5_irqs,
2219 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2220 .main_clk = "gpio5_ick",
2221 .opt_clks = gpio5_opt_clks,
2222 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2223 .prcm = {
2224 .omap2 = {
2225 .prcm_reg_id = 1,
2226 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2227 .module_offs = OMAP3430_PER_MOD,
2228 .idlest_reg_id = 1,
2229 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2230 },
2231 },
2232 .slaves = omap3xxx_gpio5_slaves,
2233 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2234 .class = &omap3xxx_gpio_hwmod_class,
2235 .dev_attr = &gpio_dev_attr,
2236 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2237};
2238
2239/* gpio6 */
2240static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2241 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2242};
2243
2244static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2245 { .role = "dbclk", .clk = "gpio6_dbck", },
2246};
2247
2248static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2249 &omap3xxx_l4_per__gpio6,
2250};
2251
2252static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2253 .name = "gpio6",
2254 .mpu_irqs = omap3xxx_gpio6_irqs,
2255 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2256 .main_clk = "gpio6_ick",
2257 .opt_clks = gpio6_opt_clks,
2258 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2259 .prcm = {
2260 .omap2 = {
2261 .prcm_reg_id = 1,
2262 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2263 .module_offs = OMAP3430_PER_MOD,
2264 .idlest_reg_id = 1,
2265 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2266 },
2267 },
2268 .slaves = omap3xxx_gpio6_slaves,
2269 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2270 .class = &omap3xxx_gpio_hwmod_class,
2271 .dev_attr = &gpio_dev_attr,
2272 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2273};
2274
G, Manjunath Kondaiah01438ab2010-12-20 18:27:19 -08002275/* dma_system -> L3 */
2276static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2277 .master = &omap3xxx_dma_system_hwmod,
2278 .slave = &omap3xxx_l3_main_hwmod,
2279 .clk = "core_l3_ick",
2280 .user = OCP_USER_MPU | OCP_USER_SDMA,
2281};
2282
2283/* dma attributes */
2284static struct omap_dma_dev_attr dma_dev_attr = {
2285 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2286 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2287 .lch_count = 32,
2288};
2289
2290static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2291 .rev_offs = 0x0000,
2292 .sysc_offs = 0x002c,
2293 .syss_offs = 0x0028,
2294 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2295 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2296 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
2297 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2298 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2299 .sysc_fields = &omap_hwmod_sysc_type1,
2300};
2301
2302static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2303 .name = "dma",
2304 .sysc = &omap3xxx_dma_sysc,
2305};
2306
2307/* dma_system */
2308static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2309 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2310 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2311 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2312 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2313};
2314
2315static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2316 {
2317 .pa_start = 0x48056000,
2318 .pa_end = 0x4a0560ff,
2319 .flags = ADDR_TYPE_RT
2320 },
2321};
2322
2323/* dma_system master ports */
2324static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2325 &omap3xxx_dma_system__l3,
2326};
2327
2328/* l4_cfg -> dma_system */
2329static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2330 .master = &omap3xxx_l4_core_hwmod,
2331 .slave = &omap3xxx_dma_system_hwmod,
2332 .clk = "core_l4_ick",
2333 .addr = omap3xxx_dma_system_addrs,
2334 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
2335 .user = OCP_USER_MPU | OCP_USER_SDMA,
2336};
2337
2338/* dma_system slave ports */
2339static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2340 &omap3xxx_l4_core__dma_system,
2341};
2342
2343static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2344 .name = "dma",
2345 .class = &omap3xxx_dma_hwmod_class,
2346 .mpu_irqs = omap3xxx_dma_system_irqs,
2347 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2348 .main_clk = "core_l3_ick",
2349 .prcm = {
2350 .omap2 = {
2351 .module_offs = CORE_MOD,
2352 .prcm_reg_id = 1,
2353 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2354 .idlest_reg_id = 1,
2355 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2356 },
2357 },
2358 .slaves = omap3xxx_dma_system_slaves,
2359 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2360 .masters = omap3xxx_dma_system_masters,
2361 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2362 .dev_attr = &dma_dev_attr,
2363 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2364 .flags = HWMOD_NO_IDLEST,
2365};
2366
Thara Gopinathd3442722010-05-29 22:02:24 +05302367/* SR common */
2368static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2369 .clkact_shift = 20,
2370};
2371
2372static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2373 .sysc_offs = 0x24,
2374 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2375 .clockact = CLOCKACT_TEST_ICLK,
2376 .sysc_fields = &omap34xx_sr_sysc_fields,
2377};
2378
2379static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2380 .name = "smartreflex",
2381 .sysc = &omap34xx_sr_sysc,
2382 .rev = 1,
2383};
2384
2385static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2386 .sidle_shift = 24,
2387 .enwkup_shift = 26
2388};
2389
2390static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2391 .sysc_offs = 0x38,
2392 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2393 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2394 SYSC_NO_CACHE),
2395 .sysc_fields = &omap36xx_sr_sysc_fields,
2396};
2397
2398static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2399 .name = "smartreflex",
2400 .sysc = &omap36xx_sr_sysc,
2401 .rev = 2,
2402};
2403
2404/* SR1 */
2405static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2406 &omap3_l4_core__sr1,
2407};
2408
2409static struct omap_hwmod omap34xx_sr1_hwmod = {
2410 .name = "sr1_hwmod",
2411 .class = &omap34xx_smartreflex_hwmod_class,
2412 .main_clk = "sr1_fck",
2413 .vdd_name = "mpu",
2414 .prcm = {
2415 .omap2 = {
2416 .prcm_reg_id = 1,
2417 .module_bit = OMAP3430_EN_SR1_SHIFT,
2418 .module_offs = WKUP_MOD,
2419 .idlest_reg_id = 1,
2420 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2421 },
2422 },
2423 .slaves = omap3_sr1_slaves,
2424 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2425 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2426 CHIP_IS_OMAP3430ES3_0 |
2427 CHIP_IS_OMAP3430ES3_1),
2428 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2429};
2430
2431static struct omap_hwmod omap36xx_sr1_hwmod = {
2432 .name = "sr1_hwmod",
2433 .class = &omap36xx_smartreflex_hwmod_class,
2434 .main_clk = "sr1_fck",
2435 .vdd_name = "mpu",
2436 .prcm = {
2437 .omap2 = {
2438 .prcm_reg_id = 1,
2439 .module_bit = OMAP3430_EN_SR1_SHIFT,
2440 .module_offs = WKUP_MOD,
2441 .idlest_reg_id = 1,
2442 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2443 },
2444 },
2445 .slaves = omap3_sr1_slaves,
2446 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2447 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2448};
2449
2450/* SR2 */
2451static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2452 &omap3_l4_core__sr2,
2453};
2454
2455static struct omap_hwmod omap34xx_sr2_hwmod = {
2456 .name = "sr2_hwmod",
2457 .class = &omap34xx_smartreflex_hwmod_class,
2458 .main_clk = "sr2_fck",
2459 .vdd_name = "core",
2460 .prcm = {
2461 .omap2 = {
2462 .prcm_reg_id = 1,
2463 .module_bit = OMAP3430_EN_SR2_SHIFT,
2464 .module_offs = WKUP_MOD,
2465 .idlest_reg_id = 1,
2466 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2467 },
2468 },
2469 .slaves = omap3_sr2_slaves,
2470 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2471 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2472 CHIP_IS_OMAP3430ES3_0 |
2473 CHIP_IS_OMAP3430ES3_1),
2474 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2475};
2476
2477static struct omap_hwmod omap36xx_sr2_hwmod = {
2478 .name = "sr2_hwmod",
2479 .class = &omap36xx_smartreflex_hwmod_class,
2480 .main_clk = "sr2_fck",
2481 .vdd_name = "core",
2482 .prcm = {
2483 .omap2 = {
2484 .prcm_reg_id = 1,
2485 .module_bit = OMAP3430_EN_SR2_SHIFT,
2486 .module_offs = WKUP_MOD,
2487 .idlest_reg_id = 1,
2488 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2489 },
2490 },
2491 .slaves = omap3_sr2_slaves,
2492 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2493 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2494};
2495
Charulatha V0f616a42011-02-17 09:53:10 -08002496/* l4 core -> mcspi1 interface */
2497static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
2498 {
2499 .pa_start = 0x48098000,
2500 .pa_end = 0x480980ff,
2501 .flags = ADDR_TYPE_RT,
2502 },
2503};
2504
2505static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2506 .master = &omap3xxx_l4_core_hwmod,
2507 .slave = &omap34xx_mcspi1,
2508 .clk = "mcspi1_ick",
2509 .addr = omap34xx_mcspi1_addr_space,
2510 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
2511 .user = OCP_USER_MPU | OCP_USER_SDMA,
2512};
2513
2514/* l4 core -> mcspi2 interface */
2515static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
2516 {
2517 .pa_start = 0x4809a000,
2518 .pa_end = 0x4809a0ff,
2519 .flags = ADDR_TYPE_RT,
2520 },
2521};
2522
2523static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2524 .master = &omap3xxx_l4_core_hwmod,
2525 .slave = &omap34xx_mcspi2,
2526 .clk = "mcspi2_ick",
2527 .addr = omap34xx_mcspi2_addr_space,
2528 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
2529 .user = OCP_USER_MPU | OCP_USER_SDMA,
2530};
2531
2532/* l4 core -> mcspi3 interface */
2533static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
2534 {
2535 .pa_start = 0x480b8000,
2536 .pa_end = 0x480b80ff,
2537 .flags = ADDR_TYPE_RT,
2538 },
2539};
2540
2541static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2542 .master = &omap3xxx_l4_core_hwmod,
2543 .slave = &omap34xx_mcspi3,
2544 .clk = "mcspi3_ick",
2545 .addr = omap34xx_mcspi3_addr_space,
2546 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
2547 .user = OCP_USER_MPU | OCP_USER_SDMA,
2548};
2549
2550/* l4 core -> mcspi4 interface */
2551static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2552 {
2553 .pa_start = 0x480ba000,
2554 .pa_end = 0x480ba0ff,
2555 .flags = ADDR_TYPE_RT,
2556 },
2557};
2558
2559static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2560 .master = &omap3xxx_l4_core_hwmod,
2561 .slave = &omap34xx_mcspi4,
2562 .clk = "mcspi4_ick",
2563 .addr = omap34xx_mcspi4_addr_space,
2564 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
2565 .user = OCP_USER_MPU | OCP_USER_SDMA,
2566};
2567
2568/*
2569 * 'mcspi' class
2570 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2571 * bus
2572 */
2573
2574static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2575 .rev_offs = 0x0000,
2576 .sysc_offs = 0x0010,
2577 .syss_offs = 0x0014,
2578 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2579 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2580 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2581 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2582 .sysc_fields = &omap_hwmod_sysc_type1,
2583};
2584
2585static struct omap_hwmod_class omap34xx_mcspi_class = {
2586 .name = "mcspi",
2587 .sysc = &omap34xx_mcspi_sysc,
2588 .rev = OMAP3_MCSPI_REV,
2589};
2590
2591/* mcspi1 */
2592static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
2593 { .name = "irq", .irq = 65 },
2594};
2595
2596static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
2597 { .name = "tx0", .dma_req = 35 },
2598 { .name = "rx0", .dma_req = 36 },
2599 { .name = "tx1", .dma_req = 37 },
2600 { .name = "rx1", .dma_req = 38 },
2601 { .name = "tx2", .dma_req = 39 },
2602 { .name = "rx2", .dma_req = 40 },
2603 { .name = "tx3", .dma_req = 41 },
2604 { .name = "rx3", .dma_req = 42 },
2605};
2606
2607static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2608 &omap34xx_l4_core__mcspi1,
2609};
2610
2611static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2612 .num_chipselect = 4,
2613};
2614
2615static struct omap_hwmod omap34xx_mcspi1 = {
2616 .name = "mcspi1",
2617 .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
2618 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
2619 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
2620 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
2621 .main_clk = "mcspi1_fck",
2622 .prcm = {
2623 .omap2 = {
2624 .module_offs = CORE_MOD,
2625 .prcm_reg_id = 1,
2626 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2627 .idlest_reg_id = 1,
2628 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2629 },
2630 },
2631 .slaves = omap34xx_mcspi1_slaves,
2632 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2633 .class = &omap34xx_mcspi_class,
2634 .dev_attr = &omap_mcspi1_dev_attr,
2635 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2636};
2637
2638/* mcspi2 */
2639static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
2640 { .name = "irq", .irq = 66 },
2641};
2642
2643static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
2644 { .name = "tx0", .dma_req = 43 },
2645 { .name = "rx0", .dma_req = 44 },
2646 { .name = "tx1", .dma_req = 45 },
2647 { .name = "rx1", .dma_req = 46 },
2648};
2649
2650static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2651 &omap34xx_l4_core__mcspi2,
2652};
2653
2654static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2655 .num_chipselect = 2,
2656};
2657
2658static struct omap_hwmod omap34xx_mcspi2 = {
2659 .name = "mcspi2",
2660 .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
2661 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
2662 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
2663 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
2664 .main_clk = "mcspi2_fck",
2665 .prcm = {
2666 .omap2 = {
2667 .module_offs = CORE_MOD,
2668 .prcm_reg_id = 1,
2669 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2670 .idlest_reg_id = 1,
2671 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2672 },
2673 },
2674 .slaves = omap34xx_mcspi2_slaves,
2675 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2676 .class = &omap34xx_mcspi_class,
2677 .dev_attr = &omap_mcspi2_dev_attr,
2678 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2679};
2680
2681/* mcspi3 */
2682static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2683 { .name = "irq", .irq = 91 }, /* 91 */
2684};
2685
2686static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2687 { .name = "tx0", .dma_req = 15 },
2688 { .name = "rx0", .dma_req = 16 },
2689 { .name = "tx1", .dma_req = 23 },
2690 { .name = "rx1", .dma_req = 24 },
2691};
2692
2693static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2694 &omap34xx_l4_core__mcspi3,
2695};
2696
2697static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2698 .num_chipselect = 2,
2699};
2700
2701static struct omap_hwmod omap34xx_mcspi3 = {
2702 .name = "mcspi3",
2703 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
2704 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
2705 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
2706 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
2707 .main_clk = "mcspi3_fck",
2708 .prcm = {
2709 .omap2 = {
2710 .module_offs = CORE_MOD,
2711 .prcm_reg_id = 1,
2712 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2713 .idlest_reg_id = 1,
2714 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2715 },
2716 },
2717 .slaves = omap34xx_mcspi3_slaves,
2718 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2719 .class = &omap34xx_mcspi_class,
2720 .dev_attr = &omap_mcspi3_dev_attr,
2721 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2722};
2723
2724/* SPI4 */
2725static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2726 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2727};
2728
2729static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2730 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2731 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2732};
2733
2734static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2735 &omap34xx_l4_core__mcspi4,
2736};
2737
2738static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2739 .num_chipselect = 1,
2740};
2741
2742static struct omap_hwmod omap34xx_mcspi4 = {
2743 .name = "mcspi4",
2744 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
2745 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
2746 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
2747 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
2748 .main_clk = "mcspi4_fck",
2749 .prcm = {
2750 .omap2 = {
2751 .module_offs = CORE_MOD,
2752 .prcm_reg_id = 1,
2753 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2754 .idlest_reg_id = 1,
2755 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2756 },
2757 },
2758 .slaves = omap34xx_mcspi4_slaves,
2759 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2760 .class = &omap34xx_mcspi_class,
2761 .dev_attr = &omap_mcspi4_dev_attr,
2762 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2763};
2764
Hema HK870ea2b2011-02-17 12:07:18 +05302765/*
2766 * usbhsotg
2767 */
2768static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2769 .rev_offs = 0x0400,
2770 .sysc_offs = 0x0404,
2771 .syss_offs = 0x0408,
2772 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2773 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2774 SYSC_HAS_AUTOIDLE),
2775 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2776 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2777 .sysc_fields = &omap_hwmod_sysc_type1,
2778};
2779
2780static struct omap_hwmod_class usbotg_class = {
2781 .name = "usbotg",
2782 .sysc = &omap3xxx_usbhsotg_sysc,
2783};
Hema HK870ea2b2011-02-17 12:07:18 +05302784/* usb_otg_hs */
2785static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2786
2787 { .name = "mc", .irq = 92 },
2788 { .name = "dma", .irq = 93 },
2789};
2790
2791static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2792 .name = "usb_otg_hs",
2793 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
2794 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
2795 .main_clk = "hsotgusb_ick",
2796 .prcm = {
2797 .omap2 = {
2798 .prcm_reg_id = 1,
2799 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2800 .module_offs = CORE_MOD,
2801 .idlest_reg_id = 1,
2802 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
2803 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
2804 },
2805 },
2806 .masters = omap3xxx_usbhsotg_masters,
2807 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
2808 .slaves = omap3xxx_usbhsotg_slaves,
2809 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
2810 .class = &usbotg_class,
2811
2812 /*
2813 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
2814 * broken when autoidle is enabled
2815 * workaround is to disable the autoidle bit at module level.
2816 */
2817 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2818 | HWMOD_SWSUP_MSTANDBY,
2819 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
2820};
Tony Lindgren04aa67d2011-02-22 10:54:12 -08002821
Hema HK273ff8c2011-02-17 12:07:19 +05302822/* usb_otg_hs */
2823static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
2824
2825 { .name = "mc", .irq = 71 },
2826};
2827
2828static struct omap_hwmod_class am35xx_usbotg_class = {
2829 .name = "am35xx_usbotg",
2830 .sysc = NULL,
2831};
2832
2833static struct omap_hwmod am35xx_usbhsotg_hwmod = {
2834 .name = "am35x_otg_hs",
2835 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
2836 .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
2837 .main_clk = NULL,
2838 .prcm = {
2839 .omap2 = {
2840 },
2841 },
2842 .masters = am35xx_usbhsotg_masters,
2843 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
2844 .slaves = am35xx_usbhsotg_slaves,
2845 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
2846 .class = &am35xx_usbotg_class,
2847 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
2848};
Hema HK870ea2b2011-02-17 12:07:18 +05302849
Paul Walmsley73591542010-02-22 22:09:32 -07002850static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
Kevin Hilman4a7cf902010-07-26 16:34:32 -06002851 &omap3xxx_l3_main_hwmod,
Paul Walmsley73591542010-02-22 22:09:32 -07002852 &omap3xxx_l4_core_hwmod,
2853 &omap3xxx_l4_per_hwmod,
2854 &omap3xxx_l4_wkup_hwmod,
2855 &omap3xxx_mpu_hwmod,
Kevin Hilman540064b2010-07-26 16:34:32 -06002856 &omap3xxx_iva_hwmod,
Thara Gopinathce722d22011-02-23 00:14:05 -07002857
2858 &omap3xxx_timer1_hwmod,
2859 &omap3xxx_timer2_hwmod,
2860 &omap3xxx_timer3_hwmod,
2861 &omap3xxx_timer4_hwmod,
2862 &omap3xxx_timer5_hwmod,
2863 &omap3xxx_timer6_hwmod,
2864 &omap3xxx_timer7_hwmod,
2865 &omap3xxx_timer8_hwmod,
2866 &omap3xxx_timer9_hwmod,
2867 &omap3xxx_timer10_hwmod,
2868 &omap3xxx_timer11_hwmod,
2869 &omap3xxx_timer12_hwmod,
2870
Varadarajan, Charulatha6b667f82010-09-23 20:02:38 +05302871 &omap3xxx_wd_timer2_hwmod,
Kevin Hilman046465b2010-09-27 20:19:30 +05302872 &omap3xxx_uart1_hwmod,
2873 &omap3xxx_uart2_hwmod,
2874 &omap3xxx_uart3_hwmod,
2875 &omap3xxx_uart4_hwmod,
Senthilvadivu Guruswamye04d9e12011-01-24 06:21:51 +00002876 /* dss class */
2877 &omap3430es1_dss_core_hwmod,
2878 &omap3xxx_dss_core_hwmod,
2879 &omap3xxx_dss_dispc_hwmod,
2880 &omap3xxx_dss_dsi1_hwmod,
2881 &omap3xxx_dss_rfbi_hwmod,
2882 &omap3xxx_dss_venc_hwmod,
2883
2884 /* i2c class */
Rajendra Nayak4fe20e92010-09-21 19:37:13 +05302885 &omap3xxx_i2c1_hwmod,
2886 &omap3xxx_i2c2_hwmod,
2887 &omap3xxx_i2c3_hwmod,
Thara Gopinathd3442722010-05-29 22:02:24 +05302888 &omap34xx_sr1_hwmod,
2889 &omap34xx_sr2_hwmod,
2890 &omap36xx_sr1_hwmod,
2891 &omap36xx_sr2_hwmod,
2892
Varadarajan, Charulatha70034d32010-12-07 16:26:57 -08002893
2894 /* gpio class */
2895 &omap3xxx_gpio1_hwmod,
2896 &omap3xxx_gpio2_hwmod,
2897 &omap3xxx_gpio3_hwmod,
2898 &omap3xxx_gpio4_hwmod,
2899 &omap3xxx_gpio5_hwmod,
2900 &omap3xxx_gpio6_hwmod,
G, Manjunath Kondaiah01438ab2010-12-20 18:27:19 -08002901
2902 /* dma_system class*/
2903 &omap3xxx_dma_system_hwmod,
Charulatha V0f616a42011-02-17 09:53:10 -08002904
2905 /* mcspi class */
2906 &omap34xx_mcspi1,
2907 &omap34xx_mcspi2,
2908 &omap34xx_mcspi3,
2909 &omap34xx_mcspi4,
Tony Lindgren04aa67d2011-02-22 10:54:12 -08002910
Hema HK870ea2b2011-02-17 12:07:18 +05302911 /* usbotg class */
2912 &omap3xxx_usbhsotg_hwmod,
2913
Hema HK273ff8c2011-02-17 12:07:19 +05302914 /* usbotg for am35x */
2915 &am35xx_usbhsotg_hwmod,
2916
Paul Walmsley73591542010-02-22 22:09:32 -07002917 NULL,
2918};
2919
2920int __init omap3xxx_hwmod_init(void)
2921{
2922 return omap_hwmod_init(omap3xxx_hwmods);
2923}