blob: 04681359a6f51d051103f184969440a48b18d3a1 [file] [log] [blame]
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
Dave Airlieab2c0672009-12-04 10:55:24 +100023#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
Keith Packarda4fc5ed2009-04-07 16:16:42 -070025
Jesse Barnes9f0e7ff2010-10-07 16:01:14 -070026#include <linux/types.h>
27#include <linux/i2c.h>
Daniel Vetter1a644cd2012-10-18 15:32:40 +020028#include <linux/delay.h>
Jesse Barnes9f0e7ff2010-10-07 16:01:14 -070029
Adam Jacksona477f4f2012-09-20 16:42:44 -040030/*
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
34 *
35 * Abbreviations, in chronological order:
36 *
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
Dave Airlie3c8a0922014-05-02 11:05:21 +100040 * MST: Multistream Transport - part of DP 1.2a
Adam Jacksona477f4f2012-09-20 16:42:44 -040041 *
42 * 1.2 formally includes both eDP and DPI definitions.
43 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -070044
Simon Farnsworth1d002fa2015-02-10 18:38:08 +000045#define DP_AUX_MAX_PAYLOAD_BYTES 16
46
Thierry Reding6b27f7f2013-12-16 17:01:29 +010047#define DP_AUX_I2C_WRITE 0x0
48#define DP_AUX_I2C_READ 0x1
Ville Syrjälä2b712be2015-08-27 17:23:26 +030049#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
Thierry Reding6b27f7f2013-12-16 17:01:29 +010050#define DP_AUX_I2C_MOT 0x4
51#define DP_AUX_NATIVE_WRITE 0x8
52#define DP_AUX_NATIVE_READ 0x9
Keith Packarda4fc5ed2009-04-07 16:16:42 -070053
Thierry Reding6b27f7f2013-12-16 17:01:29 +010054#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
55#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
56#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
57#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
Keith Packarda4fc5ed2009-04-07 16:16:42 -070058
Thierry Reding6b27f7f2013-12-16 17:01:29 +010059#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
60#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
61#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
62#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
Keith Packarda4fc5ed2009-04-07 16:16:42 -070063
64/* AUX CH addresses */
Alex Deucher5801ead2009-11-24 13:32:59 -050065/* DPCD */
66#define DP_DPCD_REV 0x000
Dave Airlie746c1aa2009-12-08 07:07:28 +100067
Alex Deucher5801ead2009-11-24 13:32:59 -050068#define DP_MAX_LINK_RATE 0x001
69
70#define DP_MAX_LANE_COUNT 0x002
71# define DP_MAX_LANE_COUNT_MASK 0x1f
Adam Jacksona477f4f2012-09-20 16:42:44 -040072# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
Alex Deucher5801ead2009-11-24 13:32:59 -050073# define DP_ENHANCED_FRAME_CAP (1 << 7)
74
75#define DP_MAX_DOWNSPREAD 0x003
Enric Balletbo i Serra56c5da02016-05-02 09:54:23 +020076# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
Alex Deucher5801ead2009-11-24 13:32:59 -050077# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
78
79#define DP_NORP 0x004
80
81#define DP_DOWNSTREAMPORT_PRESENT 0x005
82# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
83# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
Jani Nikula3d2e4232013-09-27 14:48:41 +030084# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
85# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
86# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
87# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
Alex Deucher5801ead2009-11-24 13:32:59 -050088# define DP_FORMAT_CONVERSION (1 << 3)
Adam Jacksona477f4f2012-09-20 16:42:44 -040089# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
Alex Deucher5801ead2009-11-24 13:32:59 -050090
91#define DP_MAIN_LINK_CHANNEL_CODING 0x006
92
Adam Jacksonde44d972012-05-14 16:05:46 -040093#define DP_DOWN_STREAM_PORT_COUNT 0x007
Adam Jacksone89861d2012-09-18 10:58:48 -040094# define DP_PORT_COUNT_MASK 0x0f
Adam Jacksona477f4f2012-09-20 16:42:44 -040095# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
Adam Jacksone89861d2012-09-18 10:58:48 -040096# define DP_OUI_SUPPORT (1 << 7)
97
Jani Nikula94746752015-02-27 13:10:38 +020098#define DP_RECEIVE_PORT_0_CAP_0 0x008
99# define DP_LOCAL_EDID_PRESENT (1 << 1)
100# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
101
102#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
103
104#define DP_RECEIVE_PORT_1_CAP_0 0x00a
105#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
106
Adam Jacksona477f4f2012-09-20 16:42:44 -0400107#define DP_I2C_SPEED_CAP 0x00c /* DPI */
Adam Jacksone89861d2012-09-18 10:58:48 -0400108# define DP_I2C_SPEED_1K 0x01
109# define DP_I2C_SPEED_5K 0x02
110# define DP_I2C_SPEED_10K 0x04
111# define DP_I2C_SPEED_100K 0x08
112# define DP_I2C_SPEED_400K 0x10
113# define DP_I2C_SPEED_1M 0x20
Adam Jacksonde44d972012-05-14 16:05:46 -0400114
Adam Jacksona477f4f2012-09-20 16:42:44 -0400115#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
Jani Nikula94746752015-02-27 13:10:38 +0200116# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
117# define DP_FRAMING_CHANGE_CAP (1 << 1)
Sonika Jindale045d202015-02-19 13:16:44 +0530118# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
Jani Nikulabd5da992015-02-25 14:46:51 +0200119
Adam Jacksona477f4f2012-09-20 16:42:44 -0400120#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
Alex Deucher428c4b52011-05-20 04:34:25 -0400121
Jani Nikula94746752015-02-27 13:10:38 +0200122#define DP_ADAPTER_CAP 0x00f /* 1.2 */
123# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
124# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
125
Jani Nikulabd5da992015-02-25 14:46:51 +0200126#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
127# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
128
Adam Jacksone89861d2012-09-18 10:58:48 -0400129/* Multiple stream transport */
Dave Airlie3c8a0922014-05-02 11:05:21 +1000130#define DP_FAUX_CAP 0x020 /* 1.2 */
131# define DP_FAUX_CAP_1 (1 << 0)
132
Adam Jacksona477f4f2012-09-20 16:42:44 -0400133#define DP_MSTM_CAP 0x021 /* 1.2 */
Adam Jacksone89861d2012-09-18 10:58:48 -0400134# define DP_MST_CAP (1 << 0)
135
Jani Nikula94746752015-02-27 13:10:38 +0200136#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
137
138/* AV_SYNC_DATA_BLOCK 1.2 */
139#define DP_AV_GRANULARITY 0x023
140# define DP_AG_FACTOR_MASK (0xf << 0)
141# define DP_AG_FACTOR_3MS (0 << 0)
142# define DP_AG_FACTOR_2MS (1 << 0)
143# define DP_AG_FACTOR_1MS (2 << 0)
144# define DP_AG_FACTOR_500US (3 << 0)
145# define DP_AG_FACTOR_200US (4 << 0)
146# define DP_AG_FACTOR_100US (5 << 0)
147# define DP_AG_FACTOR_10US (6 << 0)
148# define DP_AG_FACTOR_1US (7 << 0)
149# define DP_VG_FACTOR_MASK (0xf << 4)
150# define DP_VG_FACTOR_3MS (0 << 4)
151# define DP_VG_FACTOR_2MS (1 << 4)
152# define DP_VG_FACTOR_1MS (2 << 4)
153# define DP_VG_FACTOR_500US (3 << 4)
154# define DP_VG_FACTOR_200US (4 << 4)
155# define DP_VG_FACTOR_100US (5 << 4)
156
157#define DP_AUD_DEC_LAT0 0x024
158#define DP_AUD_DEC_LAT1 0x025
159
160#define DP_AUD_PP_LAT0 0x026
161#define DP_AUD_PP_LAT1 0x027
162
163#define DP_VID_INTER_LAT 0x028
164
165#define DP_VID_PROG_LAT 0x029
166
167#define DP_REP_LAT 0x02a
168
169#define DP_AUD_DEL_INS0 0x02b
170#define DP_AUD_DEL_INS1 0x02c
171#define DP_AUD_DEL_INS2 0x02d
172/* End of AV_SYNC_DATA_BLOCK */
173
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200174#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
175# define DP_ALPM_CAP (1 << 0)
176
177#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
178# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
179
Dave Airlie3c8a0922014-05-02 11:05:21 +1000180#define DP_GUID 0x030 /* 1.2 */
181
Adam Jacksona477f4f2012-09-20 16:42:44 -0400182#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700183# define DP_PSR_IS_SUPPORTED 1
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200184# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
185
Adam Jacksona477f4f2012-09-20 16:42:44 -0400186#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700187# define DP_PSR_NO_TRAIN_ON_EXIT 1
188# define DP_PSR_SETUP_TIME_330 (0 << 1)
189# define DP_PSR_SETUP_TIME_275 (1 << 1)
190# define DP_PSR_SETUP_TIME_220 (2 << 1)
191# define DP_PSR_SETUP_TIME_165 (3 << 1)
192# define DP_PSR_SETUP_TIME_110 (4 << 1)
193# define DP_PSR_SETUP_TIME_55 (5 << 1)
194# define DP_PSR_SETUP_TIME_0 (6 << 1)
195# define DP_PSR_SETUP_TIME_MASK (7 << 1)
196# define DP_PSR_SETUP_TIME_SHIFT 1
Nagaraju, Vathsalad0ce9062017-01-02 17:00:54 +0530197# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
198# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
Adam Jacksone89861d2012-09-18 10:58:48 -0400199/*
200 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
201 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
202 * each port's descriptor is one byte wide. If it was set, each port's is
203 * four bytes wide, starting with the one byte from the base info. As of
204 * DP interop v1.1a only VGA defines additional detail.
205 */
206
207/* offset 0 */
208#define DP_DOWNSTREAM_PORT_0 0x80
209# define DP_DS_PORT_TYPE_MASK (7 << 0)
210# define DP_DS_PORT_TYPE_DP 0
211# define DP_DS_PORT_TYPE_VGA 1
212# define DP_DS_PORT_TYPE_DVI 2
213# define DP_DS_PORT_TYPE_HDMI 3
214# define DP_DS_PORT_TYPE_NON_EDID 4
Mika Kahola69b1e002016-09-09 14:10:47 +0300215# define DP_DS_PORT_TYPE_DP_DUALMODE 5
216# define DP_DS_PORT_TYPE_WIRELESS 6
Adam Jacksone89861d2012-09-18 10:58:48 -0400217# define DP_DS_PORT_HPD (1 << 3)
218/* offset 1 for VGA is maximum megapixels per second / 8 */
219/* offset 2 */
Mika Kahola8fedf082016-09-09 14:10:48 +0300220# define DP_DS_MAX_BPC_MASK (3 << 0)
221# define DP_DS_8BPC 0
222# define DP_DS_10BPC 1
223# define DP_DS_12BPC 2
224# define DP_DS_16BPC 3
Adam Jacksone89861d2012-09-18 10:58:48 -0400225
Alex Deucher5801ead2009-11-24 13:32:59 -0500226/* link configuration */
227#define DP_LINK_BW_SET 0x100
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200228# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700229# define DP_LINK_BW_1_62 0x06
230# define DP_LINK_BW_2_7 0x0a
Adam Jacksona477f4f2012-09-20 16:42:44 -0400231# define DP_LINK_BW_5_4 0x14 /* 1.2 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700232
Alex Deucher5801ead2009-11-24 13:32:59 -0500233#define DP_LANE_COUNT_SET 0x101
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700234# define DP_LANE_COUNT_MASK 0x0f
235# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
236
Alex Deucher5801ead2009-11-24 13:32:59 -0500237#define DP_TRAINING_PATTERN_SET 0x102
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700238# define DP_TRAINING_PATTERN_DISABLE 0
239# define DP_TRAINING_PATTERN_1 1
240# define DP_TRAINING_PATTERN_2 2
Adam Jacksona477f4f2012-09-20 16:42:44 -0400241# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700242# define DP_TRAINING_PATTERN_MASK 0x3
243
Jani Nikula94746752015-02-27 13:10:38 +0200244/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
245# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
246# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
247# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
248# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
249# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700250
251# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
252# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
253
254# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
255# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
256# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
257# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
258
259#define DP_TRAINING_LANE0_SET 0x103
260#define DP_TRAINING_LANE1_SET 0x104
261#define DP_TRAINING_LANE2_SET 0x105
262#define DP_TRAINING_LANE3_SET 0x106
263
264# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
265# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
266# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530267# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530268# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530269# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530270# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700271
272# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530273# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530274# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530275# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
Sonika Jindal0504cd12014-08-08 16:23:40 +0530276# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700277
278# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
279# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
280
281#define DP_DOWNSPREAD_CTRL 0x107
282# define DP_SPREAD_AMP_0_5 (1 << 4)
Adam Jacksona477f4f2012-09-20 16:42:44 -0400283# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700284
285#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
286# define DP_SET_ANSI_8B10B (1 << 0)
287
Adam Jacksona477f4f2012-09-20 16:42:44 -0400288#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
Adam Jacksone89861d2012-09-18 10:58:48 -0400289/* bitmask as for DP_I2C_SPEED_CAP */
290
Adam Jacksona477f4f2012-09-20 16:42:44 -0400291#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
Jani Nikula94746752015-02-27 13:10:38 +0200292# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
293# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
294# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
295
296#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
297#define DP_LINK_QUAL_LANE1_SET 0x10c
298#define DP_LINK_QUAL_LANE2_SET 0x10d
299#define DP_LINK_QUAL_LANE3_SET 0x10e
300# define DP_LINK_QUAL_PATTERN_DISABLE 0
301# define DP_LINK_QUAL_PATTERN_D10_2 1
302# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
303# define DP_LINK_QUAL_PATTERN_PRBS7 3
304# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
305# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
306# define DP_LINK_QUAL_PATTERN_MASK 7
307
308#define DP_TRAINING_LANE0_1_SET2 0x10f
309#define DP_TRAINING_LANE2_3_SET2 0x110
310# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
311# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
312# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
313# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
Adam Jacksone89861d2012-09-18 10:58:48 -0400314
Adam Jacksona477f4f2012-09-20 16:42:44 -0400315#define DP_MSTM_CTRL 0x111 /* 1.2 */
Adam Jacksone89861d2012-09-18 10:58:48 -0400316# define DP_MST_EN (1 << 0)
317# define DP_UP_REQ_EN (1 << 1)
318# define DP_UPSTREAM_IS_SRC (1 << 2)
319
Jani Nikula94746752015-02-27 13:10:38 +0200320#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
321#define DP_AUDIO_DELAY1 0x113
322#define DP_AUDIO_DELAY2 0x114
323
Jani Nikulabd5da992015-02-25 14:46:51 +0200324#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200325# define DP_LINK_RATE_SET_SHIFT 0
326# define DP_LINK_RATE_SET_MASK (7 << 0)
327
328#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
329# define DP_ALPM_ENABLE (1 << 0)
330# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
331
332#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
333# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
334# define DP_IRQ_HPD_ENABLE (1 << 1)
Sonika Jindale045d202015-02-19 13:16:44 +0530335
Jani Nikula94746752015-02-27 13:10:38 +0200336#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
337# define DP_PWR_NOT_NEEDED (1 << 0)
338
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200339#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
340# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
341
Adam Jacksona477f4f2012-09-20 16:42:44 -0400342#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700343# define DP_PSR_ENABLE (1 << 0)
344# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
345# define DP_PSR_CRC_VERIFICATION (1 << 2)
346# define DP_PSR_FRAME_CAPTURE (1 << 3)
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200347# define DP_PSR_SELECTIVE_UPDATE (1 << 4)
348# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
Ben Widawskyb73fe582011-10-04 15:16:48 -0700349
Dave Airlie3c8a0922014-05-02 11:05:21 +1000350#define DP_ADAPTER_CTRL 0x1a0
351# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
352
353#define DP_BRANCH_DEVICE_CTRL 0x1a1
354# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
355
356#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
357#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
358#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
359
Adam Jacksone89861d2012-09-18 10:58:48 -0400360#define DP_SINK_COUNT 0x200
Adam Jacksonda131a42012-09-20 16:42:45 -0400361/* prior to 1.2 bit 7 was reserved mbz */
362# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
Adam Jacksone89861d2012-09-18 10:58:48 -0400363# define DP_SINK_CP_READY (1 << 6)
364
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700365#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
366# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
367# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
368# define DP_CP_IRQ (1 << 2)
Dave Airlie3c8a0922014-05-02 11:05:21 +1000369# define DP_MCCS_IRQ (1 << 3)
370# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
371# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700372# define DP_SINK_SPECIFIC_IRQ (1 << 6)
373
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700374#define DP_LANE0_1_STATUS 0x202
375#define DP_LANE2_3_STATUS 0x203
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700376# define DP_LANE_CR_DONE (1 << 0)
377# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
378# define DP_LANE_SYMBOL_LOCKED (1 << 2)
379
Alex Deucher5801ead2009-11-24 13:32:59 -0500380#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
381 DP_LANE_CHANNEL_EQ_DONE | \
382 DP_LANE_SYMBOL_LOCKED)
383
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700384#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
385
386#define DP_INTERLANE_ALIGN_DONE (1 << 0)
387#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
388#define DP_LINK_STATUS_UPDATED (1 << 7)
389
390#define DP_SINK_STATUS 0x205
391
392#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
393#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
394
395#define DP_ADJUST_REQUEST_LANE0_1 0x206
396#define DP_ADJUST_REQUEST_LANE2_3 0x207
Alex Deucher5801ead2009-11-24 13:32:59 -0500397# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
398# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
399# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
400# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
401# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
402# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
403# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
404# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700405
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700406#define DP_TEST_REQUEST 0x218
407# define DP_TEST_LINK_TRAINING (1 << 0)
Todd Previtefe3c7032013-10-04 12:59:03 -0700408# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700409# define DP_TEST_LINK_EDID_READ (1 << 2)
410# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
Todd Previtefe3c7032013-10-04 12:59:03 -0700411# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700412
413#define DP_TEST_LINK_RATE 0x219
414# define DP_LINK_RATE_162 (0x6)
415# define DP_LINK_RATE_27 (0xa)
416
417#define DP_TEST_LANE_COUNT 0x220
418
419#define DP_TEST_PATTERN 0x221
420
Rodrigo Vivia25eebb2014-01-14 16:21:49 -0200421#define DP_TEST_CRC_R_CR 0x240
422#define DP_TEST_CRC_G_Y 0x242
423#define DP_TEST_CRC_B_CB 0x244
424
425#define DP_TEST_SINK_MISC 0x246
Rodrigo Viviad9dc912014-09-16 19:18:12 -0400426# define DP_TEST_CRC_SUPPORTED (1 << 5)
Rodrigo Vivi90a21702015-07-23 16:34:58 -0700427# define DP_TEST_COUNT_MASK 0xf
Rodrigo Vivia25eebb2014-01-14 16:21:49 -0200428
Jesse Barnesa60f0e32011-10-20 15:09:17 -0700429#define DP_TEST_RESPONSE 0x260
430# define DP_TEST_ACK (1 << 0)
431# define DP_TEST_NAK (1 << 1)
432# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
433
Jingoo Han073ea2a2014-05-07 20:44:51 +0900434#define DP_TEST_EDID_CHECKSUM 0x261
435
Rodrigo Vivia25eebb2014-01-14 16:21:49 -0200436#define DP_TEST_SINK 0x270
Rodrigo Viviad9dc912014-09-16 19:18:12 -0400437# define DP_TEST_SINK_START (1 << 0)
Rodrigo Vivia25eebb2014-01-14 16:21:49 -0200438
Dave Airlie3c8a0922014-05-02 11:05:21 +1000439#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
440# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
441# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
442
443#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
444/* up to ID_SLOT_63 at 0x2ff */
445
Adam Jackson86c3c3b2012-05-14 16:05:45 -0400446#define DP_SOURCE_OUI 0x300
447#define DP_SINK_OUI 0x400
448#define DP_BRANCH_OUI 0x500
Mika Kahola266d7832016-09-09 14:10:51 +0300449#define DP_BRANCH_ID 0x503
Mika Kahola0e390a32016-09-09 14:10:53 +0300450#define DP_BRANCH_HW_REV 0x509
Mika Kahola1a2724f2016-09-09 14:10:54 +0300451#define DP_BRANCH_SW_REV 0x50A
Adam Jackson86c3c3b2012-05-14 16:05:45 -0400452
Alex Deucher1a66c952009-11-20 19:40:13 -0500453#define DP_SET_POWER 0x600
Alex Deucher5801ead2009-11-24 13:32:59 -0500454# define DP_SET_POWER_D0 0x1
455# define DP_SET_POWER_D3 0x2
Thierry Reding516c0f72013-12-09 11:47:55 +0100456# define DP_SET_POWER_MASK 0x3
Alex Deucher1a66c952009-11-20 19:40:13 -0500457
Jani Nikulabd5da992015-02-25 14:46:51 +0200458#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200459# define DP_EDP_11 0x00
460# define DP_EDP_12 0x01
461# define DP_EDP_13 0x02
462# define DP_EDP_14 0x03
Sonika Jindale045d202015-02-19 13:16:44 +0530463
Jani Nikula0e712442015-02-25 14:46:53 +0200464#define DP_EDP_GENERAL_CAP_1 0x701
Jani Nikula36af4ca2015-10-29 11:03:08 +0200465# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
466# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
467# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
468# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
469# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
470# define DP_EDP_FRC_ENABLE_CAP (1 << 5)
471# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
472# define DP_EDP_SET_POWER_CAP (1 << 7)
Jani Nikula0e712442015-02-25 14:46:53 +0200473
474#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
Jani Nikula36af4ca2015-10-29 11:03:08 +0200475# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
476# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
477# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
478# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
479# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
480# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
481# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
482# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
Jani Nikula0e712442015-02-25 14:46:53 +0200483
484#define DP_EDP_GENERAL_CAP_2 0x703
Jani Nikula36af4ca2015-10-29 11:03:08 +0200485# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
Jani Nikula0e712442015-02-25 14:46:53 +0200486
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200487#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
Jani Nikula36af4ca2015-10-29 11:03:08 +0200488# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
489# define DP_EDP_X_REGION_CAP_SHIFT 0
490# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
491# define DP_EDP_Y_REGION_CAP_SHIFT 4
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200492
Jani Nikula0e712442015-02-25 14:46:53 +0200493#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
Jani Nikula36af4ca2015-10-29 11:03:08 +0200494# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
495# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
496# define DP_EDP_FRC_ENABLE (1 << 2)
497# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
498# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
Jani Nikula0e712442015-02-25 14:46:53 +0200499
500#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
Jani Nikula36af4ca2015-10-29 11:03:08 +0200501# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
502# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
503# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
504# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
505# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
506# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
507# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
508# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
509# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
510# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
Jani Nikula0e712442015-02-25 14:46:53 +0200511
512#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
513#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
514
515#define DP_EDP_PWMGEN_BIT_COUNT 0x724
516#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
517#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
518
519#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
520
521#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
522
523#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
524#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
525#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
526
527#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
528#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
529#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
530
531#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
532#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
533
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200534#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
535#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
536
Dave Airlie3c8a0922014-05-02 11:05:21 +1000537#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
538#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
539#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
540#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
541
542#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
543/* 0-5 sink count */
544# define DP_SINK_COUNT_CP_READY (1 << 6)
545
546#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
547
548#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
549
550#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
551
Adam Jacksona477f4f2012-09-20 16:42:44 -0400552#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700553# define DP_PSR_LINK_CRC_ERROR (1 << 0)
554# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200555# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700556
Adam Jacksona477f4f2012-09-20 16:42:44 -0400557#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700558# define DP_PSR_CAPS_CHANGE (1 << 0)
559
Adam Jacksona477f4f2012-09-20 16:42:44 -0400560#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
Ben Widawskyb73fe582011-10-04 15:16:48 -0700561# define DP_PSR_SINK_INACTIVE 0
562# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
563# define DP_PSR_SINK_ACTIVE_RFB 2
564# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
565# define DP_PSR_SINK_ACTIVE_RESYNC 4
566# define DP_PSR_SINK_INTERNAL_ERROR 7
567# define DP_PSR_SINK_STATE_MASK 0x07
568
Jani Nikula6b1e3f62015-02-27 13:11:14 +0200569#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
570# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
571
Nagaraju, Vathsalad0ce9062017-01-02 17:00:54 +0530572#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
573# define DP_GTC_CAP (1 << 0) /* DP 1.3 */
574# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
575# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
576# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
577# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
578# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
579# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
580# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
581
Dave Airlie3c8a0922014-05-02 11:05:21 +1000582/* DP 1.2 Sideband message defines */
583/* peer device type - DP 1.2a Table 2-92 */
584#define DP_PEER_DEVICE_NONE 0x0
585#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
586#define DP_PEER_DEVICE_MST_BRANCHING 0x2
587#define DP_PEER_DEVICE_SST_SINK 0x3
588#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
589
590/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
591#define DP_LINK_ADDRESS 0x01
592#define DP_CONNECTION_STATUS_NOTIFY 0x02
593#define DP_ENUM_PATH_RESOURCES 0x10
594#define DP_ALLOCATE_PAYLOAD 0x11
595#define DP_QUERY_PAYLOAD 0x12
596#define DP_RESOURCE_STATUS_NOTIFY 0x13
597#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
598#define DP_REMOTE_DPCD_READ 0x20
599#define DP_REMOTE_DPCD_WRITE 0x21
600#define DP_REMOTE_I2C_READ 0x22
601#define DP_REMOTE_I2C_WRITE 0x23
602#define DP_POWER_UP_PHY 0x24
603#define DP_POWER_DOWN_PHY 0x25
604#define DP_SINK_EVENT_NOTIFY 0x30
605#define DP_QUERY_STREAM_ENC_STATUS 0x38
606
607/* DP 1.2 MST sideband nak reasons - table 2.84 */
608#define DP_NAK_WRITE_FAILURE 0x01
609#define DP_NAK_INVALID_READ 0x02
610#define DP_NAK_CRC_FAILURE 0x03
611#define DP_NAK_BAD_PARAM 0x04
612#define DP_NAK_DEFER 0x05
613#define DP_NAK_LINK_FAILURE 0x06
614#define DP_NAK_NO_RESOURCES 0x07
615#define DP_NAK_DPCD_FAIL 0x08
616#define DP_NAK_I2C_NAK 0x09
617#define DP_NAK_ALLOCATE_FAIL 0x0a
618
Dave Airlieab2c0672009-12-04 10:55:24 +1000619#define MODE_I2C_START 1
620#define MODE_I2C_WRITE 2
621#define MODE_I2C_READ 4
622#define MODE_I2C_STOP 8
623
Dave Airlieccf03d62015-10-01 16:28:25 +1000624/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
625#define DP_MST_PHYSICAL_PORT_0 0
626#define DP_MST_LOGICAL_PORT_0 8
627
Daniel Vetter1ffdff12012-10-18 10:15:24 +0200628#define DP_LINK_STATUS_SIZE 6
Jani Nikula0aec2882013-09-27 19:01:01 +0300629bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
Daniel Vetter1ffdff12012-10-18 10:15:24 +0200630 int lane_count);
Jani Nikula0aec2882013-09-27 19:01:01 +0300631bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
Daniel Vetter01916272012-10-18 10:15:25 +0200632 int lane_count);
Jani Nikula0aec2882013-09-27 19:01:01 +0300633u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
Daniel Vetter0f037bd2012-10-18 10:15:27 +0200634 int lane);
Jani Nikula0aec2882013-09-27 19:01:01 +0300635u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
Daniel Vetter0f037bd2012-10-18 10:15:27 +0200636 int lane);
Daniel Vetter1ffdff12012-10-18 10:15:24 +0200637
Dave Airlie44790462015-07-14 11:33:31 +1000638#define DP_BRANCH_OUI_HEADER_SIZE 0xc
Shobhit Kumar52604b12013-07-11 18:44:55 -0300639#define DP_RECEIVER_CAP_SIZE 0xf
640#define EDP_PSR_RECEIVER_CAP_SIZE 2
Yetunde Adebisi4e382db2016-04-05 15:10:50 +0100641#define EDP_DISPLAY_CTL_CAP_SIZE 3
Shobhit Kumar52604b12013-07-11 18:44:55 -0300642
Jani Nikula0aec2882013-09-27 19:01:01 +0300643void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
644void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
Daniel Vetter1a644cd2012-10-18 15:32:40 +0200645
Daniel Vetter3b5c6622012-10-18 10:15:31 +0200646u8 drm_dp_link_rate_to_bw_code(int link_rate);
647int drm_dp_bw_code_to_link_rate(u8 link_bw);
648
Shobhit Kumar52604b12013-07-11 18:44:55 -0300649struct edp_sdp_header {
650 u8 HB0; /* Secondary Data Packet ID */
651 u8 HB1; /* Secondary Data Packet Type */
652 u8 HB2; /* 7:5 reserved, 4:0 revision number */
653 u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
654} __packed;
655
656#define EDP_SDP_HEADER_REVISION_MASK 0x1F
657#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
658
659struct edp_vsc_psr {
660 struct edp_sdp_header sdp_header;
661 u8 DB0; /* Stereo Interface */
662 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
663 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
664 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
665 u8 DB4; /* CRC value bits 7:0 of the G or Y component */
666 u8 DB5; /* CRC value bits 15:8 of the G or Y component */
667 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
668 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
669 u8 DB8_31[24]; /* Reserved */
670} __packed;
671
672#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
673#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
674#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
675
Ville Syrjälä66088042016-05-18 11:57:29 +0300676int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
677
Daniel Vetter3b5c6622012-10-18 10:15:31 +0200678static inline int
Jani Nikula0aec2882013-09-27 19:01:01 +0300679drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
Daniel Vetter3b5c6622012-10-18 10:15:31 +0200680{
681 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
682}
Daniel Vetter397fe152012-10-22 22:56:43 +0200683
684static inline u8
Jani Nikula0aec2882013-09-27 19:01:01 +0300685drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
Daniel Vetter397fe152012-10-22 22:56:43 +0200686{
687 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
688}
689
Jani Nikula58704e62013-10-04 15:08:08 +0300690static inline bool
691drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
692{
693 return dpcd[DP_DPCD_REV] >= 0x11 &&
694 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
695}
696
Jani Nikula7cc53cf2015-08-26 14:33:31 +0300697static inline bool
698drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
699{
700 return dpcd[DP_DPCD_REV] >= 0x12 &&
701 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
702}
703
Imre Deakc726ad02016-10-24 19:33:24 +0300704static inline bool
705drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
706{
707 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
708}
709
Thierry Redingc197db72013-11-28 11:31:00 +0100710/*
711 * DisplayPort AUX channel
712 */
713
714/**
715 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
716 * @address: address of the (first) register to access
717 * @request: contains the type of transaction (see DP_AUX_* macros)
718 * @reply: upon completion, contains the reply type of the transaction
719 * @buffer: pointer to a transmission or reception buffer
720 * @size: size of @buffer
721 */
722struct drm_dp_aux_msg {
723 unsigned int address;
724 u8 request;
725 u8 reply;
726 void *buffer;
727 size_t size;
728};
729
730/**
731 * struct drm_dp_aux - DisplayPort AUX channel
Thierry Redingb8380582014-04-23 15:49:04 +0200732 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
Thierry Reding88759682013-12-12 09:57:53 +0100733 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
Thierry Redingc197db72013-11-28 11:31:00 +0100734 * @dev: pointer to struct device that is the parent for this AUX channel
Dave Airlie4f71d0c2014-06-04 16:02:28 +1000735 * @hw_mutex: internal mutex used for locking transfers
Thierry Redingc197db72013-11-28 11:31:00 +0100736 * @transfer: transfers a message representing a single AUX transaction
737 *
738 * The .dev field should be set to a pointer to the device that implements
739 * the AUX channel.
740 *
Jani Nikula9dc40562014-03-14 16:51:12 +0200741 * The .name field may be used to specify the name of the I2C adapter. If set to
742 * NULL, dev_name() of .dev will be used.
743 *
Thierry Redingc197db72013-11-28 11:31:00 +0100744 * Drivers provide a hardware-specific implementation of how transactions
745 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
746 * structure describing the transaction is passed into this function. Upon
747 * success, the implementation should return the number of payload bytes
748 * that were transferred, or a negative error-code on failure. Helpers
749 * propagate errors from the .transfer() function, with the exception of
750 * the -EBUSY error, which causes a transaction to be retried. On a short,
751 * helpers will return -EPROTO to make it simpler to check for failure.
Thierry Reding88759682013-12-12 09:57:53 +0100752 *
753 * An AUX channel can also be used to transport I2C messages to a sink. A
754 * typical application of that is to access an EDID that's present in the
755 * sink device. The .transfer() function can also be used to execute such
Jon Hunter6921f882015-05-13 12:30:46 +0100756 * transactions. The drm_dp_aux_register() function registers an I2C
757 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
758 * should call drm_dp_aux_unregister() to remove the I2C adapter.
Simon Farnsworth1d002fa2015-02-10 18:38:08 +0000759 * The I2C adapter uses long transfers by default; if a partial response is
760 * received, the adapter will drop down to the size given by the partial
761 * response for this transaction only.
Alex Deucher732d50b2014-04-07 10:33:45 -0400762 *
763 * Note that the aux helper code assumes that the .transfer() function
764 * only modifies the reply field of the drm_dp_aux_msg structure. The
765 * retry logic and i2c helpers assume this is the case.
Thierry Redingc197db72013-11-28 11:31:00 +0100766 */
767struct drm_dp_aux {
Jani Nikula9dc40562014-03-14 16:51:12 +0200768 const char *name;
Thierry Reding88759682013-12-12 09:57:53 +0100769 struct i2c_adapter ddc;
Thierry Redingc197db72013-11-28 11:31:00 +0100770 struct device *dev;
Dave Airlie4f71d0c2014-06-04 16:02:28 +1000771 struct mutex hw_mutex;
Thierry Redingc197db72013-11-28 11:31:00 +0100772 ssize_t (*transfer)(struct drm_dp_aux *aux,
773 struct drm_dp_aux_msg *msg);
Daniel Vetter212ae892016-07-15 21:48:02 +0200774 /**
775 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
776 */
777 unsigned i2c_nack_count;
778 /**
779 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
780 */
781 unsigned i2c_defer_count;
Thierry Redingc197db72013-11-28 11:31:00 +0100782};
783
784ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
785 void *buffer, size_t size);
786ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
787 void *buffer, size_t size);
788
789/**
790 * drm_dp_dpcd_readb() - read a single byte from the DPCD
791 * @aux: DisplayPort AUX channel
792 * @offset: address of the register to read
793 * @valuep: location where the value of the register will be stored
794 *
795 * Returns the number of bytes transferred (1) on success, or a negative
796 * error code on failure.
797 */
798static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
799 unsigned int offset, u8 *valuep)
800{
801 return drm_dp_dpcd_read(aux, offset, valuep, 1);
802}
803
804/**
805 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
806 * @aux: DisplayPort AUX channel
807 * @offset: address of the register to write
808 * @value: value to write to the register
809 *
810 * Returns the number of bytes transferred (1) on success, or a negative
811 * error code on failure.
812 */
813static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
814 unsigned int offset, u8 value)
815{
816 return drm_dp_dpcd_write(aux, offset, &value, 1);
817}
818
Thierry Reding8d4adc62013-11-22 16:37:57 +0100819int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
820 u8 status[DP_LINK_STATUS_SIZE]);
821
Thierry Reding516c0f72013-12-09 11:47:55 +0100822/*
823 * DisplayPort link
824 */
825#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
826
827struct drm_dp_link {
828 unsigned char revision;
829 unsigned int rate;
830 unsigned int num_lanes;
831 unsigned long capabilities;
832};
833
834int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
835int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
Rob Clarkd816f072014-12-02 10:43:07 -0500836int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
Thierry Reding516c0f72013-12-09 11:47:55 +0100837int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
Mika Kahola1c29bd32016-09-09 14:10:49 +0300838int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
839 const u8 port_cap[4]);
Mika Kahola7529d6a2016-09-09 14:10:50 +0300840int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
841 const u8 port_cap[4]);
Mika Kahola266d7832016-09-09 14:10:51 +0300842int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
Mika Kahola80209e52016-09-09 14:10:57 +0300843void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
844 const u8 port_cap[4], struct drm_dp_aux *aux);
Thierry Reding516c0f72013-12-09 11:47:55 +0100845
Chris Wilsonacd8f412016-06-17 09:33:18 +0100846void drm_dp_aux_init(struct drm_dp_aux *aux);
Dave Airlie4f71d0c2014-06-04 16:02:28 +1000847int drm_dp_aux_register(struct drm_dp_aux *aux);
848void drm_dp_aux_unregister(struct drm_dp_aux *aux);
Thierry Reding88759682013-12-12 09:57:53 +0100849
Dave Airlieab2c0672009-12-04 10:55:24 +1000850#endif /* _DRM_DP_HELPER_H_ */