| Jeeja KP | a40e693 | 2015-07-09 15:20:08 +0530 | [diff] [blame] | 1 | /* |
| 2 | * skl.h - HD Audio skylake defintions. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp |
| 5 | * Author: Jeeja KP <jeeja.kp@intel.com> |
| 6 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but |
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | #ifndef __SOUND_SOC_SKL_H |
| 22 | #define __SOUND_SOC_SKL_H |
| 23 | |
| 24 | #include <sound/hda_register.h> |
| 25 | #include <sound/hdaudio_ext.h> |
| Jeeja KP | 473eb87 | 2015-07-21 23:53:55 +0530 | [diff] [blame] | 26 | #include "skl-nhlt.h" |
| Jeeja KP | a40e693 | 2015-07-09 15:20:08 +0530 | [diff] [blame] | 27 | |
| 28 | #define SKL_SUSPEND_DELAY 2000 |
| 29 | |
| 30 | /* Vendor Specific Registers */ |
| 31 | #define AZX_REG_VS_EM1 0x1000 |
| 32 | #define AZX_REG_VS_INRC 0x1004 |
| 33 | #define AZX_REG_VS_OUTRC 0x1008 |
| 34 | #define AZX_REG_VS_FIFOTRK 0x100C |
| 35 | #define AZX_REG_VS_FIFOTRK2 0x1010 |
| 36 | #define AZX_REG_VS_EM2 0x1030 |
| 37 | #define AZX_REG_VS_EM3L 0x1038 |
| 38 | #define AZX_REG_VS_EM3U 0x103C |
| 39 | #define AZX_REG_VS_EM4L 0x1040 |
| 40 | #define AZX_REG_VS_EM4U 0x1044 |
| 41 | #define AZX_REG_VS_LTRC 0x1048 |
| 42 | #define AZX_REG_VS_D0I3C 0x104A |
| 43 | #define AZX_REG_VS_PCE 0x104B |
| 44 | #define AZX_REG_VS_L2MAGC 0x1050 |
| 45 | #define AZX_REG_VS_L2LAHPT 0x1054 |
| 46 | #define AZX_REG_VS_SDXDPIB_XBASE 0x1084 |
| 47 | #define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20 |
| 48 | #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 |
| 49 | #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 |
| 50 | |
| 51 | struct skl { |
| 52 | struct hdac_ext_bus ebus; |
| 53 | struct pci_dev *pci; |
| 54 | |
| 55 | unsigned int init_failed:1; /* delayed init failed */ |
| 56 | struct platform_device *dmic_dev; |
| Jeeja KP | 473eb87 | 2015-07-21 23:53:55 +0530 | [diff] [blame] | 57 | |
| 58 | void __iomem *nhlt; /* nhlt ptr */ |
| Jeeja KP | d255b09 | 2015-07-21 23:53:56 +0530 | [diff] [blame^] | 59 | struct skl_sst *skl_sst; /* sst skl ctx */ |
| Jeeja KP | a40e693 | 2015-07-09 15:20:08 +0530 | [diff] [blame] | 60 | }; |
| 61 | |
| 62 | #define skl_to_ebus(s) (&(s)->ebus) |
| 63 | #define ebus_to_skl(sbus) \ |
| 64 | container_of(sbus, struct skl, sbus) |
| 65 | |
| 66 | /* to pass dai dma data */ |
| 67 | struct skl_dma_params { |
| 68 | u32 format; |
| 69 | u8 stream_tag; |
| 70 | }; |
| 71 | |
| 72 | int skl_platform_unregister(struct device *dev); |
| 73 | int skl_platform_register(struct device *dev); |
| 74 | |
| Jeeja KP | 473eb87 | 2015-07-21 23:53:55 +0530 | [diff] [blame] | 75 | void __iomem *skl_nhlt_init(struct device *dev); |
| 76 | void skl_nhlt_free(void __iomem *addr); |
| 77 | struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance, |
| 78 | u8 link_type, u8 s_fmt, u8 no_ch, u32 s_rate, u8 dirn); |
| Jeeja KP | d255b09 | 2015-07-21 23:53:56 +0530 | [diff] [blame^] | 79 | |
| 80 | int skl_init_dsp(struct skl *skl); |
| 81 | void skl_free_dsp(struct skl *skl); |
| 82 | int skl_suspend_dsp(struct skl *skl); |
| 83 | int skl_resume_dsp(struct skl *skl); |
| Jeeja KP | a40e693 | 2015-07-09 15:20:08 +0530 | [diff] [blame] | 84 | #endif /* __SOUND_SOC_SKL_H */ |