Maxime Ripard | d4da2eb | 2012-11-14 20:17:04 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Maxime Ripard |
| 3 | * |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 5 | * |
| 6 | * The code contained herein is licensed under the GNU General Public |
| 7 | * License. You may obtain a copy of the GNU General Public License |
| 8 | * Version 2 or later at the following locations: |
| 9 | * |
| 10 | * http://www.opensource.org/licenses/gpl-license.html |
| 11 | * http://www.gnu.org/copyleft/gpl.html |
| 12 | */ |
| 13 | |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 14 | /include/ "skeleton.dtsi" |
Maxime Ripard | d4da2eb | 2012-11-14 20:17:04 +0100 | [diff] [blame] | 15 | |
| 16 | / { |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 17 | interrupt-parent = <&intc>; |
| 18 | |
Maxime Ripard | 0cc774e | 2014-01-13 11:08:47 +0100 | [diff] [blame] | 19 | aliases { |
| 20 | serial0 = &uart1; |
| 21 | serial1 = &uart3; |
| 22 | }; |
| 23 | |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 24 | cpus { |
Arnd Bergmann | 8b2efa89 | 2013-06-10 16:48:36 +0200 | [diff] [blame] | 25 | #address-cells = <1>; |
| 26 | #size-cells = <0>; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 27 | cpu@0 { |
Lorenzo Pieralisi | 14c44aa | 2013-04-18 18:41:57 +0100 | [diff] [blame] | 28 | device_type = "cpu"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 29 | compatible = "arm,cortex-a8"; |
Lorenzo Pieralisi | 14c44aa | 2013-04-18 18:41:57 +0100 | [diff] [blame] | 30 | reg = <0x0>; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 31 | }; |
| 32 | }; |
| 33 | |
Maxime Ripard | d4da2eb | 2012-11-14 20:17:04 +0100 | [diff] [blame] | 34 | memory { |
| 35 | reg = <0x40000000 0x20000000>; |
| 36 | }; |
Maxime Ripard | 9e2dcb2 | 2013-01-18 22:30:36 +0100 | [diff] [blame] | 37 | |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 38 | clocks { |
| 39 | #address-cells = <1>; |
| 40 | #size-cells = <1>; |
| 41 | ranges; |
| 42 | |
| 43 | /* |
| 44 | * This is a dummy clock, to be used as placeholder on |
| 45 | * other mux clocks when a specific parent clock is not |
| 46 | * yet implemented. It should be dropped when the driver |
| 47 | * is complete. |
| 48 | */ |
| 49 | dummy: dummy { |
| 50 | #clock-cells = <0>; |
| 51 | compatible = "fixed-clock"; |
| 52 | clock-frequency = <0>; |
| 53 | }; |
| 54 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 55 | osc24M: clk@01c20050 { |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 56 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 57 | compatible = "allwinner,sun4i-a10-osc-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 58 | reg = <0x01c20050 0x4>; |
Emilio López | 92fd6e0 | 2013-04-09 10:48:04 -0300 | [diff] [blame] | 59 | clock-frequency = <24000000>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 60 | clock-output-names = "osc24M"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 61 | }; |
| 62 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 63 | osc32k: clk@0 { |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 64 | #clock-cells = <0>; |
| 65 | compatible = "fixed-clock"; |
| 66 | clock-frequency = <32768>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 67 | clock-output-names = "osc32k"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 68 | }; |
| 69 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 70 | pll1: clk@01c20000 { |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 71 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 72 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 73 | reg = <0x01c20000 0x4>; |
| 74 | clocks = <&osc24M>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 75 | clock-output-names = "pll1"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 76 | }; |
| 77 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 78 | pll4: clk@01c20018 { |
Emilio López | ec5589f | 2013-12-23 00:32:35 -0300 | [diff] [blame] | 79 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 80 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
Emilio López | ec5589f | 2013-12-23 00:32:35 -0300 | [diff] [blame] | 81 | reg = <0x01c20018 0x4>; |
| 82 | clocks = <&osc24M>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 83 | clock-output-names = "pll4"; |
Emilio López | ec5589f | 2013-12-23 00:32:35 -0300 | [diff] [blame] | 84 | }; |
| 85 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 86 | pll5: clk@01c20020 { |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 87 | #clock-cells = <1>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 88 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 89 | reg = <0x01c20020 0x4>; |
| 90 | clocks = <&osc24M>; |
| 91 | clock-output-names = "pll5_ddr", "pll5_other"; |
| 92 | }; |
| 93 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 94 | pll6: clk@01c20028 { |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 95 | #clock-cells = <1>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 96 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 97 | reg = <0x01c20028 0x4>; |
| 98 | clocks = <&osc24M>; |
| 99 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; |
| 100 | }; |
| 101 | |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 102 | /* dummy is 200M */ |
| 103 | cpu: cpu@01c20054 { |
| 104 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 105 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 106 | reg = <0x01c20054 0x4>; |
| 107 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 108 | clock-output-names = "cpu"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 109 | }; |
| 110 | |
| 111 | axi: axi@01c20054 { |
| 112 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 113 | compatible = "allwinner,sun4i-a10-axi-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 114 | reg = <0x01c20054 0x4>; |
| 115 | clocks = <&cpu>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 116 | clock-output-names = "axi"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 117 | }; |
| 118 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 119 | axi_gates: clk@01c2005c { |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 120 | #clock-cells = <1>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 121 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 122 | reg = <0x01c2005c 0x4>; |
| 123 | clocks = <&axi>; |
| 124 | clock-output-names = "axi_dram"; |
| 125 | }; |
| 126 | |
| 127 | ahb: ahb@01c20054 { |
| 128 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 129 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 130 | reg = <0x01c20054 0x4>; |
| 131 | clocks = <&axi>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 132 | clock-output-names = "ahb"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 133 | }; |
| 134 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 135 | ahb_gates: clk@01c20060 { |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 136 | #clock-cells = <1>; |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 137 | compatible = "allwinner,sun5i-a13-ahb-gates-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 138 | reg = <0x01c20060 0x8>; |
| 139 | clocks = <&ahb>; |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 140 | clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", |
| 141 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", |
| 142 | "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", |
| 143 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer", |
| 144 | "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be", |
| 145 | "ahb_de_fe", "ahb_iep", "ahb_mali400"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 146 | }; |
| 147 | |
| 148 | apb0: apb0@01c20054 { |
| 149 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 150 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 151 | reg = <0x01c20054 0x4>; |
| 152 | clocks = <&ahb>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 153 | clock-output-names = "apb0"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 154 | }; |
| 155 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 156 | apb0_gates: clk@01c20068 { |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 157 | #clock-cells = <1>; |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 158 | compatible = "allwinner,sun5i-a13-apb0-gates-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 159 | reg = <0x01c20068 0x4>; |
| 160 | clocks = <&apb0>; |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 161 | clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 162 | }; |
| 163 | |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 164 | apb1_mux: apb1_mux@01c20058 { |
| 165 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 166 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 167 | reg = <0x01c20058 0x4>; |
Emilio López | c3e5e66 | 2013-12-23 00:32:38 -0300 | [diff] [blame] | 168 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 169 | clock-output-names = "apb1_mux"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 170 | }; |
| 171 | |
| 172 | apb1: apb1@01c20058 { |
| 173 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 174 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 175 | reg = <0x01c20058 0x4>; |
| 176 | clocks = <&apb1_mux>; |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 177 | clock-output-names = "apb1"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 178 | }; |
| 179 | |
Chen-Yu Tsai | 3dce832 | 2014-02-03 09:51:42 +0800 | [diff] [blame] | 180 | apb1_gates: clk@01c2006c { |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 181 | #clock-cells = <1>; |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 182 | compatible = "allwinner,sun5i-a13-apb1-gates-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 183 | reg = <0x01c2006c 0x4>; |
| 184 | clocks = <&apb1>; |
| 185 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 186 | "apb1_i2c2", "apb1_uart1", "apb1_uart3"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 187 | }; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 188 | |
| 189 | nand_clk: clk@01c20080 { |
| 190 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 191 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 192 | reg = <0x01c20080 0x4>; |
| 193 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 194 | clock-output-names = "nand"; |
| 195 | }; |
| 196 | |
| 197 | ms_clk: clk@01c20084 { |
| 198 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 199 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 200 | reg = <0x01c20084 0x4>; |
| 201 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 202 | clock-output-names = "ms"; |
| 203 | }; |
| 204 | |
| 205 | mmc0_clk: clk@01c20088 { |
| 206 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 207 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 208 | reg = <0x01c20088 0x4>; |
| 209 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 210 | clock-output-names = "mmc0"; |
| 211 | }; |
| 212 | |
| 213 | mmc1_clk: clk@01c2008c { |
| 214 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 215 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 216 | reg = <0x01c2008c 0x4>; |
| 217 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 218 | clock-output-names = "mmc1"; |
| 219 | }; |
| 220 | |
| 221 | mmc2_clk: clk@01c20090 { |
| 222 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 223 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 224 | reg = <0x01c20090 0x4>; |
| 225 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 226 | clock-output-names = "mmc2"; |
| 227 | }; |
| 228 | |
| 229 | ts_clk: clk@01c20098 { |
| 230 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 231 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 232 | reg = <0x01c20098 0x4>; |
| 233 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 234 | clock-output-names = "ts"; |
| 235 | }; |
| 236 | |
| 237 | ss_clk: clk@01c2009c { |
| 238 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 239 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 240 | reg = <0x01c2009c 0x4>; |
| 241 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 242 | clock-output-names = "ss"; |
| 243 | }; |
| 244 | |
| 245 | spi0_clk: clk@01c200a0 { |
| 246 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 247 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 248 | reg = <0x01c200a0 0x4>; |
| 249 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 250 | clock-output-names = "spi0"; |
| 251 | }; |
| 252 | |
| 253 | spi1_clk: clk@01c200a4 { |
| 254 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 255 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 256 | reg = <0x01c200a4 0x4>; |
| 257 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 258 | clock-output-names = "spi1"; |
| 259 | }; |
| 260 | |
| 261 | spi2_clk: clk@01c200a8 { |
| 262 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 263 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 264 | reg = <0x01c200a8 0x4>; |
| 265 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 266 | clock-output-names = "spi2"; |
| 267 | }; |
| 268 | |
| 269 | ir0_clk: clk@01c200b0 { |
| 270 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 271 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 8dc36bf | 2013-12-23 00:32:42 -0300 | [diff] [blame] | 272 | reg = <0x01c200b0 0x4>; |
| 273 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 274 | clock-output-names = "ir0"; |
| 275 | }; |
Emilio López | 118c07a | 2013-12-23 00:32:44 -0300 | [diff] [blame] | 276 | |
Roman Byshko | 4c5d72f | 2014-02-07 16:21:52 +0100 | [diff] [blame] | 277 | usb_clk: clk@01c200cc { |
| 278 | #clock-cells = <1>; |
| 279 | #reset-cells = <1>; |
| 280 | compatible = "allwinner,sun5i-a13-usb-clk"; |
| 281 | reg = <0x01c200cc 0x4>; |
| 282 | clocks = <&pll6 1>; |
| 283 | clock-output-names = "usb_ohci0", "usb_phy"; |
| 284 | }; |
| 285 | |
Emilio López | 118c07a | 2013-12-23 00:32:44 -0300 | [diff] [blame] | 286 | mbus_clk: clk@01c2015c { |
| 287 | #clock-cells = <0>; |
Maxime Ripard | bf6534a | 2014-02-06 09:55:58 +0100 | [diff] [blame] | 288 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
Emilio López | 118c07a | 2013-12-23 00:32:44 -0300 | [diff] [blame] | 289 | reg = <0x01c2015c 0x4>; |
| 290 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; |
| 291 | clock-output-names = "mbus"; |
| 292 | }; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 293 | }; |
| 294 | |
Maxime Ripard | 278fe8b | 2013-08-03 16:07:36 +0200 | [diff] [blame] | 295 | soc@01c00000 { |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 296 | compatible = "simple-bus"; |
| 297 | #address-cells = <1>; |
| 298 | #size-cells = <1>; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 299 | ranges; |
| 300 | |
Maxime Ripard | 8f8658b | 2014-02-22 22:35:57 +0100 | [diff] [blame] | 301 | spi0: spi@01c05000 { |
| 302 | compatible = "allwinner,sun4i-a10-spi"; |
| 303 | reg = <0x01c05000 0x1000>; |
| 304 | interrupts = <10>; |
| 305 | clocks = <&ahb_gates 20>, <&spi0_clk>; |
| 306 | clock-names = "ahb", "mod"; |
| 307 | status = "disabled"; |
| 308 | #address-cells = <1>; |
| 309 | #size-cells = <0>; |
| 310 | }; |
| 311 | |
| 312 | spi1: spi@01c06000 { |
| 313 | compatible = "allwinner,sun4i-a10-spi"; |
| 314 | reg = <0x01c06000 0x1000>; |
| 315 | interrupts = <11>; |
| 316 | clocks = <&ahb_gates 21>, <&spi1_clk>; |
| 317 | clock-names = "ahb", "mod"; |
| 318 | status = "disabled"; |
| 319 | #address-cells = <1>; |
| 320 | #size-cells = <0>; |
| 321 | }; |
| 322 | |
Roman Byshko | 06c7d52 | 2014-03-01 20:26:24 +0100 | [diff] [blame] | 323 | usbphy: phy@01c13400 { |
| 324 | #phy-cells = <1>; |
| 325 | compatible = "allwinner,sun5i-a13-usb-phy"; |
| 326 | reg = <0x01c13400 0x10 0x01c14800 0x4>; |
| 327 | reg-names = "phy_ctrl", "pmu1"; |
| 328 | clocks = <&usb_clk 8>; |
| 329 | clock-names = "usb_phy"; |
| 330 | resets = <&usb_clk 1>; |
| 331 | reset-names = "usb1_reset"; |
| 332 | status = "disabled"; |
| 333 | }; |
| 334 | |
| 335 | ehci0: usb@01c14000 { |
| 336 | compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; |
| 337 | reg = <0x01c14000 0x100>; |
| 338 | interrupts = <39>; |
| 339 | clocks = <&ahb_gates 1>; |
| 340 | phys = <&usbphy 1>; |
| 341 | phy-names = "usb"; |
| 342 | status = "disabled"; |
| 343 | }; |
| 344 | |
| 345 | ohci0: usb@01c14400 { |
| 346 | compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; |
| 347 | reg = <0x01c14400 0x100>; |
| 348 | interrupts = <40>; |
| 349 | clocks = <&usb_clk 6>, <&ahb_gates 2>; |
| 350 | phys = <&usbphy 1>; |
| 351 | phy-names = "usb"; |
| 352 | status = "disabled"; |
| 353 | }; |
| 354 | |
Maxime Ripard | 8f8658b | 2014-02-22 22:35:57 +0100 | [diff] [blame] | 355 | spi2: spi@01c17000 { |
| 356 | compatible = "allwinner,sun4i-a10-spi"; |
| 357 | reg = <0x01c17000 0x1000>; |
| 358 | interrupts = <12>; |
| 359 | clocks = <&ahb_gates 22>, <&spi2_clk>; |
| 360 | clock-names = "ahb", "mod"; |
| 361 | status = "disabled"; |
| 362 | #address-cells = <1>; |
| 363 | #size-cells = <0>; |
| 364 | }; |
| 365 | |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 366 | intc: interrupt-controller@01c20400 { |
Maxime Ripard | 09504a7 | 2014-02-07 21:50:26 +0100 | [diff] [blame] | 367 | compatible = "allwinner,sun4i-a10-ic"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 368 | reg = <0x01c20400 0x400>; |
| 369 | interrupt-controller; |
| 370 | #interrupt-cells = <1>; |
| 371 | }; |
| 372 | |
Maxime Ripard | e10911e | 2013-01-27 19:26:05 +0100 | [diff] [blame] | 373 | pio: pinctrl@01c20800 { |
Maxime Ripard | 9e2dcb2 | 2013-01-18 22:30:36 +0100 | [diff] [blame] | 374 | compatible = "allwinner,sun5i-a13-pinctrl"; |
| 375 | reg = <0x01c20800 0x400>; |
Maxime Ripard | 39138bc | 2013-04-06 15:00:48 +0200 | [diff] [blame] | 376 | interrupts = <28>; |
Emilio López | 36386d6 | 2013-03-27 18:20:41 -0300 | [diff] [blame] | 377 | clocks = <&apb0_gates 5>; |
Maxime Ripard | e10911e | 2013-01-27 19:26:05 +0100 | [diff] [blame] | 378 | gpio-controller; |
Maxime Ripard | 39138bc | 2013-04-06 15:00:48 +0200 | [diff] [blame] | 379 | interrupt-controller; |
Maxime Ripard | 9e2dcb2 | 2013-01-18 22:30:36 +0100 | [diff] [blame] | 380 | #address-cells = <1>; |
| 381 | #size-cells = <0>; |
Maxime Ripard | e10911e | 2013-01-27 19:26:05 +0100 | [diff] [blame] | 382 | #gpio-cells = <3>; |
Maxime Ripard | 4348cc6 | 2013-01-18 22:30:37 +0100 | [diff] [blame] | 383 | |
| 384 | uart1_pins_a: uart1@0 { |
| 385 | allwinner,pins = "PE10", "PE11"; |
| 386 | allwinner,function = "uart1"; |
| 387 | allwinner,drive = <0>; |
| 388 | allwinner,pull = <0>; |
| 389 | }; |
| 390 | |
| 391 | uart1_pins_b: uart1@1 { |
| 392 | allwinner,pins = "PG3", "PG4"; |
| 393 | allwinner,function = "uart1"; |
| 394 | allwinner,drive = <0>; |
| 395 | allwinner,pull = <0>; |
| 396 | }; |
Maxime Ripard | b4d7c23 | 2013-03-10 13:36:02 +0100 | [diff] [blame] | 397 | |
| 398 | i2c0_pins_a: i2c0@0 { |
| 399 | allwinner,pins = "PB0", "PB1"; |
| 400 | allwinner,function = "i2c0"; |
| 401 | allwinner,drive = <0>; |
| 402 | allwinner,pull = <0>; |
| 403 | }; |
| 404 | |
| 405 | i2c1_pins_a: i2c1@0 { |
| 406 | allwinner,pins = "PB15", "PB16"; |
| 407 | allwinner,function = "i2c1"; |
| 408 | allwinner,drive = <0>; |
| 409 | allwinner,pull = <0>; |
| 410 | }; |
| 411 | |
| 412 | i2c2_pins_a: i2c2@0 { |
| 413 | allwinner,pins = "PB17", "PB18"; |
| 414 | allwinner,function = "i2c2"; |
| 415 | allwinner,drive = <0>; |
| 416 | allwinner,pull = <0>; |
| 417 | }; |
Maxime Ripard | 9e2dcb2 | 2013-01-18 22:30:36 +0100 | [diff] [blame] | 418 | }; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 419 | |
| 420 | timer@01c20c00 { |
Maxime Ripard | b4f2644 | 2014-02-06 10:40:32 +0100 | [diff] [blame] | 421 | compatible = "allwinner,sun4i-a10-timer"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 422 | reg = <0x01c20c00 0x90>; |
| 423 | interrupts = <22>; |
| 424 | clocks = <&osc24M>; |
| 425 | }; |
| 426 | |
| 427 | wdt: watchdog@01c20c90 { |
Maxime Ripard | ca5d04d | 2014-02-07 22:29:26 +0100 | [diff] [blame] | 428 | compatible = "allwinner,sun4i-a10-wdt"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 429 | reg = <0x01c20c90 0x10>; |
| 430 | }; |
| 431 | |
Oliver Schinagl | 2bad969 | 2013-09-03 12:33:28 +0200 | [diff] [blame] | 432 | sid: eeprom@01c23800 { |
Maxime Ripard | 043d56e | 2014-02-07 22:20:40 +0100 | [diff] [blame] | 433 | compatible = "allwinner,sun4i-a10-sid"; |
Oliver Schinagl | 2bad969 | 2013-09-03 12:33:28 +0200 | [diff] [blame] | 434 | reg = <0x01c23800 0x10>; |
| 435 | }; |
| 436 | |
Hans de Goede | f65c93a | 2013-12-31 17:20:51 +0100 | [diff] [blame] | 437 | rtp: rtp@01c25000 { |
Maxime Ripard | 40dd8f3 | 2014-02-02 14:52:40 +0100 | [diff] [blame] | 438 | compatible = "allwinner,sun4i-a10-ts"; |
Hans de Goede | f65c93a | 2013-12-31 17:20:51 +0100 | [diff] [blame] | 439 | reg = <0x01c25000 0x100>; |
| 440 | interrupts = <29>; |
| 441 | }; |
| 442 | |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 443 | uart1: serial@01c28400 { |
| 444 | compatible = "snps,dw-apb-uart"; |
| 445 | reg = <0x01c28400 0x400>; |
| 446 | interrupts = <2>; |
| 447 | reg-shift = <2>; |
| 448 | reg-io-width = <4>; |
| 449 | clocks = <&apb1_gates 17>; |
| 450 | status = "disabled"; |
| 451 | }; |
| 452 | |
| 453 | uart3: serial@01c28c00 { |
| 454 | compatible = "snps,dw-apb-uart"; |
| 455 | reg = <0x01c28c00 0x400>; |
| 456 | interrupts = <4>; |
| 457 | reg-shift = <2>; |
| 458 | reg-io-width = <4>; |
| 459 | clocks = <&apb1_gates 19>; |
| 460 | status = "disabled"; |
| 461 | }; |
Maxime Ripard | f1741fd | 2013-03-10 13:34:36 +0100 | [diff] [blame] | 462 | |
| 463 | i2c0: i2c@01c2ac00 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame^] | 464 | compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | f1741fd | 2013-03-10 13:34:36 +0100 | [diff] [blame] | 465 | reg = <0x01c2ac00 0x400>; |
| 466 | interrupts = <7>; |
| 467 | clocks = <&apb1_gates 0>; |
| 468 | clock-frequency = <100000>; |
| 469 | status = "disabled"; |
| 470 | }; |
| 471 | |
| 472 | i2c1: i2c@01c2b000 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame^] | 473 | compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | f1741fd | 2013-03-10 13:34:36 +0100 | [diff] [blame] | 474 | reg = <0x01c2b000 0x400>; |
| 475 | interrupts = <8>; |
| 476 | clocks = <&apb1_gates 1>; |
| 477 | clock-frequency = <100000>; |
| 478 | status = "disabled"; |
| 479 | }; |
| 480 | |
| 481 | i2c2: i2c@01c2b400 { |
Maxime Ripard | d275545 | 2014-03-31 14:54:58 +0200 | [diff] [blame^] | 482 | compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; |
Maxime Ripard | f1741fd | 2013-03-10 13:34:36 +0100 | [diff] [blame] | 483 | reg = <0x01c2b400 0x400>; |
| 484 | interrupts = <9>; |
| 485 | clocks = <&apb1_gates 2>; |
| 486 | clock-frequency = <100000>; |
| 487 | status = "disabled"; |
| 488 | }; |
Maxime Ripard | 4411902 | 2013-11-07 12:01:48 +0100 | [diff] [blame] | 489 | |
| 490 | timer@01c60000 { |
| 491 | compatible = "allwinner,sun5i-a13-hstimer"; |
| 492 | reg = <0x01c60000 0x1000>; |
| 493 | interrupts = <82>, <83>; |
| 494 | clocks = <&ahb_gates 28>; |
| 495 | }; |
Maxime Ripard | 9e2dcb2 | 2013-01-18 22:30:36 +0100 | [diff] [blame] | 496 | }; |
Maxime Ripard | d4da2eb | 2012-11-14 20:17:04 +0100 | [diff] [blame] | 497 | }; |