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gerrit-public.fairphone.software / kernel / msm-4.19 / d3a7a7479f149492b151516d62fff42328446e04 / . / arch / arm / boot / dts / stih407.dtsi
blob: 4f9024f19866eeb67d4020851685778b4d79568d [file] [log] [blame]
Maxime Coquelinf563a572014-02-27 13:27:27 +0100[diff] [blame]1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih407-clock.dtsi"
10#include "stih407-pinctrl.dtsi"
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 cpu@0 {
19 device_type = "cpu";
20 compatible = "arm,cortex-a9";
21 reg = <0>;
22 };
23 cpu@1 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a9";
26 reg = <1>;
27 };
28 };
29
30 intc: interrupt-controller@08761000 {
31 compatible = "arm,cortex-a9-gic";
32 #interrupt-cells = <3>;
33 interrupt-controller;
34 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
35 };
36
37 scu@08760000 {
38 compatible = "arm,cortex-a9-scu";
39 reg = <0x08760000 0x1000>;
40 };
41
42 timer@08760200 {
43 interrupt-parent = <&intc>;
44 compatible = "arm,cortex-a9-global-timer";
45 reg = <0x08760200 0x100>;
46 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
47 clocks = <&arm_periph_clk>;
48 };
49
50 l2: cache-controller {
51 compatible = "arm,pl310-cache";
52 reg = <0x08762000 0x1000>;
53 arm,data-latency = <3 3 3>;
54 arm,tag-latency = <2 2 2>;
55 cache-unified;
56 cache-level = <2>;
57 };
58
59 soc {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 interrupt-parent = <&intc>;
63 ranges;
64 compatible = "simple-bus";
65
66 syscfg_sbc: sbc-syscfg@9620000 {
67 compatible = "st,stih407-sbc-syscfg", "syscon";
68 reg = <0x9620000 0x1000>;
69 };
70
71 syscfg_front: front-syscfg@9280000 {
72 compatible = "st,stih407-front-syscfg", "syscon";
73 reg = <0x9280000 0x1000>;
74 };
75
76 syscfg_rear: rear-syscfg@9290000 {
77 compatible = "st,stih407-rear-syscfg", "syscon";
78 reg = <0x9290000 0x1000>;
79 };
80
81 syscfg_flash: flash-syscfg@92a0000 {
82 compatible = "st,stih407-flash-syscfg", "syscon";
83 reg = <0x92a0000 0x1000>;
84 };
85
86 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
87 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
88 reg = <0x9600000 0x1000>;
89 };
90
91 syscfg_core: core-syscfg@92b0000 {
92 compatible = "st,stih407-core-syscfg", "syscon";
93 reg = <0x92b0000 0x1000>;
94 };
95
96 syscfg_lpm: lpm-syscfg@94b5100 {
97 compatible = "st,stih407-lpm-syscfg", "syscon";
98 reg = <0x94b5100 0x1000>;
99 };
100
101 serial@9830000 {
102 compatible = "st,asc";
103 reg = <0x9830000 0x2c>;
104 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_serial0>;
107 clocks = <&clk_ext2f_a9>;
108
109 status = "disabled";
110 };
111
112 serial@9831000 {
113 compatible = "st,asc";
114 reg = <0x9831000 0x2c>;
115 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_serial1>;
118 clocks = <&clk_ext2f_a9>;
119
120 status = "disabled";
121 };
122
123 serial@9832000 {
124 compatible = "st,asc";
125 reg = <0x9832000 0x2c>;
126 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_serial2>;
129 clocks = <&clk_ext2f_a9>;
130
131 status = "disabled";
132 };
133
134 /* SBC_ASC0 - UART10 */
135 sbc_serial0: serial@9530000 {
136 compatible = "st,asc";
137 reg = <0x9530000 0x2c>;
138 interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_sbc_serial0>;
141 clocks = <&clk_sysin>;
142
143 status = "disabled";
144 };
145
146 serial@9531000 {
147 compatible = "st,asc";
148 reg = <0x9531000 0x2c>;
149 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_sbc_serial1>;
152 clocks = <&clk_sysin>;
153
154 status = "disabled";
155 };
156
157 i2c@9840000 {
158 compatible = "st,comms-ssc4-i2c";
159 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
160 reg = <0x9840000 0x110>;
161 clocks = <&clk_ext2f_a9>;
162 clock-names = "ssc";
163 clock-frequency = <400000>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_i2c0_default>;
166
167 status = "disabled";
168 };
169
170 i2c@9841000 {
171 compatible = "st,comms-ssc4-i2c";
172 reg = <0x9841000 0x110>;
173 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&clk_ext2f_a9>;
175 clock-names = "ssc";
176 clock-frequency = <400000>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_i2c1_default>;
179
180 status = "disabled";
181 };
182
183 i2c@9842000 {
184 compatible = "st,comms-ssc4-i2c";
185 reg = <0x9842000 0x110>;
186 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clk_ext2f_a9>;
188 clock-names = "ssc";
189 clock-frequency = <400000>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_i2c2_default>;
192
193 status = "disabled";
194 };
195
196 i2c@9843000 {
197 compatible = "st,comms-ssc4-i2c";
198 reg = <0x9843000 0x110>;
199 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clk_ext2f_a9>;
201 clock-names = "ssc";
202 clock-frequency = <400000>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_i2c3_default>;
205
206 status = "disabled";
207 };
208
209 i2c@9844000 {
210 compatible = "st,comms-ssc4-i2c";
211 reg = <0x9844000 0x110>;
212 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&clk_ext2f_a9>;
214 clock-names = "ssc";
215 clock-frequency = <400000>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_i2c4_default>;
218
219 status = "disabled";
220 };
221
222 i2c@9845000 {
223 compatible = "st,comms-ssc4-i2c";
224 reg = <0x9845000 0x110>;
225 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clk_ext2f_a9>;
227 clock-names = "ssc";
228 clock-frequency = <400000>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_i2c5_default>;
231
232 status = "disabled";
233 };
234
235
236 /* SSCs on SBC */
237 i2c@9540000 {
238 compatible = "st,comms-ssc4-i2c";
239 reg = <0x9540000 0x110>;
240 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&clk_sysin>;
242 clock-names = "ssc";
243 clock-frequency = <400000>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_i2c10_default>;
246
247 status = "disabled";
248 };
249
250 i2c@9541000 {
251 compatible = "st,comms-ssc4-i2c";
252 reg = <0x9541000 0x110>;
253 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clk_sysin>;
255 clock-names = "ssc";
256 clock-frequency = <400000>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_i2c11_default>;
259
260 status = "disabled";
261 };
262 };
263};