Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __ASM_SPINLOCK_H |
| 2 | #define __ASM_SPINLOCK_H |
| 3 | |
| 4 | #if __LINUX_ARM_ARCH__ < 6 |
| 5 | #error SMP not supported on pre-ARMv6 CPUs |
| 6 | #endif |
| 7 | |
Will Deacon | 9bb17be | 2013-07-02 14:54:33 +0100 | [diff] [blame] | 8 | #include <linux/prefetch.h> |
Marc Zyngier | 603605a | 2011-05-23 17:16:59 +0100 | [diff] [blame] | 9 | |
Russell King | 000d9c7 | 2011-01-15 16:22:12 +0000 | [diff] [blame] | 10 | /* |
| 11 | * sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K |
| 12 | * extensions, so when running on UP, we have to patch these instructions away. |
| 13 | */ |
Russell King | 000d9c7 | 2011-01-15 16:22:12 +0000 | [diff] [blame] | 14 | #ifdef CONFIG_THUMB2_KERNEL |
Dave Martin | 917692f | 2011-02-09 12:06:59 +0100 | [diff] [blame] | 15 | /* |
| 16 | * For Thumb-2, special care is needed to ensure that the conditional WFE |
| 17 | * instruction really does assemble to exactly 4 bytes (as required by |
| 18 | * the SMP_ON_UP fixup code). By itself "wfene" might cause the |
| 19 | * assembler to insert a extra (16-bit) IT instruction, depending on the |
| 20 | * presence or absence of neighbouring conditional instructions. |
| 21 | * |
| 22 | * To avoid this unpredictableness, an approprite IT is inserted explicitly: |
| 23 | * the assembler won't change IT instructions which are explicitly present |
| 24 | * in the input. |
| 25 | */ |
Will Deacon | 27a8479 | 2013-07-02 12:10:42 +0100 | [diff] [blame] | 26 | #define WFE(cond) __ALT_SMP_ASM( \ |
Dave Martin | 917692f | 2011-02-09 12:06:59 +0100 | [diff] [blame] | 27 | "it " cond "\n\t" \ |
| 28 | "wfe" cond ".n", \ |
| 29 | \ |
| 30 | "nop.w" \ |
| 31 | ) |
Russell King | 000d9c7 | 2011-01-15 16:22:12 +0000 | [diff] [blame] | 32 | #else |
Will Deacon | 27a8479 | 2013-07-02 12:10:42 +0100 | [diff] [blame] | 33 | #define WFE(cond) __ALT_SMP_ASM("wfe" cond, "nop") |
Russell King | 000d9c7 | 2011-01-15 16:22:12 +0000 | [diff] [blame] | 34 | #endif |
| 35 | |
Will Deacon | 27a8479 | 2013-07-02 12:10:42 +0100 | [diff] [blame] | 36 | #define SEV __ALT_SMP_ASM(WASM(sev), WASM(nop)) |
| 37 | |
Rabin Vincent | c5113b6 | 2010-01-25 19:43:03 +0100 | [diff] [blame] | 38 | static inline void dsb_sev(void) |
| 39 | { |
Will Deacon | 7c8746a | 2014-02-07 19:12:32 +0100 | [diff] [blame] | 40 | |
| 41 | dsb(ishst); |
| 42 | __asm__(SEV); |
Rabin Vincent | c5113b6 | 2010-01-25 19:43:03 +0100 | [diff] [blame] | 43 | } |
| 44 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | /* |
Will Deacon | 546c289 | 2012-07-06 15:43:41 +0100 | [diff] [blame] | 46 | * ARMv6 ticket-based spin-locking. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | * |
Will Deacon | 546c289 | 2012-07-06 15:43:41 +0100 | [diff] [blame] | 48 | * A memory barrier is required after we get a lock, and before we |
| 49 | * release it, because V6 CPUs are assumed to have weakly ordered |
| 50 | * memory. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | |
Thomas Gleixner | 0199c4e | 2009-12-02 20:01:25 +0100 | [diff] [blame] | 53 | #define arch_spin_unlock_wait(lock) \ |
| 54 | do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | |
Thomas Gleixner | 0199c4e | 2009-12-02 20:01:25 +0100 | [diff] [blame] | 56 | #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | |
Thomas Gleixner | 0199c4e | 2009-12-02 20:01:25 +0100 | [diff] [blame] | 58 | static inline void arch_spin_lock(arch_spinlock_t *lock) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | { |
| 60 | unsigned long tmp; |
Will Deacon | 546c289 | 2012-07-06 15:43:41 +0100 | [diff] [blame] | 61 | u32 newval; |
| 62 | arch_spinlock_t lockval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | |
Will Deacon | 9bb17be | 2013-07-02 14:54:33 +0100 | [diff] [blame] | 64 | prefetchw(&lock->slock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | __asm__ __volatile__( |
Will Deacon | 546c289 | 2012-07-06 15:43:41 +0100 | [diff] [blame] | 66 | "1: ldrex %0, [%3]\n" |
| 67 | " add %1, %0, %4\n" |
| 68 | " strex %2, %1, [%3]\n" |
| 69 | " teq %2, #0\n" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | " bne 1b" |
Will Deacon | 546c289 | 2012-07-06 15:43:41 +0100 | [diff] [blame] | 71 | : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) |
| 72 | : "r" (&lock->slock), "I" (1 << TICKET_SHIFT) |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 73 | : "cc"); |
| 74 | |
Will Deacon | 546c289 | 2012-07-06 15:43:41 +0100 | [diff] [blame] | 75 | while (lockval.tickets.next != lockval.tickets.owner) { |
| 76 | wfe(); |
| 77 | lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner); |
| 78 | } |
| 79 | |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 80 | smp_mb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | } |
| 82 | |
Thomas Gleixner | 0199c4e | 2009-12-02 20:01:25 +0100 | [diff] [blame] | 83 | static inline int arch_spin_trylock(arch_spinlock_t *lock) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | { |
Will Deacon | 15e7e5c | 2013-06-05 11:27:26 +0100 | [diff] [blame] | 85 | unsigned long contended, res; |
Will Deacon | 546c289 | 2012-07-06 15:43:41 +0100 | [diff] [blame] | 86 | u32 slock; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | |
Will Deacon | 9bb17be | 2013-07-02 14:54:33 +0100 | [diff] [blame] | 88 | prefetchw(&lock->slock); |
Will Deacon | 15e7e5c | 2013-06-05 11:27:26 +0100 | [diff] [blame] | 89 | do { |
| 90 | __asm__ __volatile__( |
| 91 | " ldrex %0, [%3]\n" |
| 92 | " mov %2, #0\n" |
| 93 | " subs %1, %0, %0, ror #16\n" |
| 94 | " addeq %0, %0, %4\n" |
| 95 | " strexeq %2, %0, [%3]" |
Will Deacon | afa31d8 | 2013-08-12 18:03:26 +0100 | [diff] [blame] | 96 | : "=&r" (slock), "=&r" (contended), "=&r" (res) |
Will Deacon | 15e7e5c | 2013-06-05 11:27:26 +0100 | [diff] [blame] | 97 | : "r" (&lock->slock), "I" (1 << TICKET_SHIFT) |
| 98 | : "cc"); |
| 99 | } while (res); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | |
Will Deacon | 15e7e5c | 2013-06-05 11:27:26 +0100 | [diff] [blame] | 101 | if (!contended) { |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 102 | smp_mb(); |
| 103 | return 1; |
| 104 | } else { |
| 105 | return 0; |
| 106 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | } |
| 108 | |
Thomas Gleixner | 0199c4e | 2009-12-02 20:01:25 +0100 | [diff] [blame] | 109 | static inline void arch_spin_unlock(arch_spinlock_t *lock) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | { |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 111 | smp_mb(); |
Will Deacon | 20e260b | 2013-01-24 14:47:38 +0100 | [diff] [blame] | 112 | lock->tickets.owner++; |
Rabin Vincent | c5113b6 | 2010-01-25 19:43:03 +0100 | [diff] [blame] | 113 | dsb_sev(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | } |
| 115 | |
Will Deacon | 0cbad9c | 2013-10-09 17:19:22 +0100 | [diff] [blame] | 116 | static inline int arch_spin_value_unlocked(arch_spinlock_t lock) |
| 117 | { |
| 118 | return lock.tickets.owner == lock.tickets.next; |
| 119 | } |
| 120 | |
Will Deacon | 546c289 | 2012-07-06 15:43:41 +0100 | [diff] [blame] | 121 | static inline int arch_spin_is_locked(arch_spinlock_t *lock) |
| 122 | { |
Will Deacon | 0cbad9c | 2013-10-09 17:19:22 +0100 | [diff] [blame] | 123 | return !arch_spin_value_unlocked(ACCESS_ONCE(*lock)); |
Will Deacon | 546c289 | 2012-07-06 15:43:41 +0100 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | static inline int arch_spin_is_contended(arch_spinlock_t *lock) |
| 127 | { |
| 128 | struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets); |
| 129 | return (tickets.next - tickets.owner) > 1; |
| 130 | } |
| 131 | #define arch_spin_is_contended arch_spin_is_contended |
| 132 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 133 | /* |
| 134 | * RWLOCKS |
Ingo Molnar | fb1c8f9 | 2005-09-10 00:25:56 -0700 | [diff] [blame] | 135 | * |
| 136 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | * Write locks are easy - we just set bit 31. When unlocking, we can |
| 138 | * just write zero since the lock is exclusively held. |
| 139 | */ |
Ingo Molnar | fb1c8f9 | 2005-09-10 00:25:56 -0700 | [diff] [blame] | 140 | |
Thomas Gleixner | e593194 | 2009-12-03 20:08:46 +0100 | [diff] [blame] | 141 | static inline void arch_write_lock(arch_rwlock_t *rw) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | { |
| 143 | unsigned long tmp; |
| 144 | |
Will Deacon | 9bb17be | 2013-07-02 14:54:33 +0100 | [diff] [blame] | 145 | prefetchw(&rw->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | __asm__ __volatile__( |
| 147 | "1: ldrex %0, [%1]\n" |
| 148 | " teq %0, #0\n" |
Russell King | 000d9c7 | 2011-01-15 16:22:12 +0000 | [diff] [blame] | 149 | WFE("ne") |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | " strexeq %0, %2, [%1]\n" |
| 151 | " teq %0, #0\n" |
| 152 | " bne 1b" |
| 153 | : "=&r" (tmp) |
| 154 | : "r" (&rw->lock), "r" (0x80000000) |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 155 | : "cc"); |
| 156 | |
| 157 | smp_mb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | } |
| 159 | |
Thomas Gleixner | e593194 | 2009-12-03 20:08:46 +0100 | [diff] [blame] | 160 | static inline int arch_write_trylock(arch_rwlock_t *rw) |
Russell King | 4e8fd22 | 2005-07-24 12:13:40 +0100 | [diff] [blame] | 161 | { |
Will Deacon | 00efaa0 | 2013-08-12 18:04:05 +0100 | [diff] [blame] | 162 | unsigned long contended, res; |
Russell King | 4e8fd22 | 2005-07-24 12:13:40 +0100 | [diff] [blame] | 163 | |
Will Deacon | 9bb17be | 2013-07-02 14:54:33 +0100 | [diff] [blame] | 164 | prefetchw(&rw->lock); |
Will Deacon | 00efaa0 | 2013-08-12 18:04:05 +0100 | [diff] [blame] | 165 | do { |
| 166 | __asm__ __volatile__( |
| 167 | " ldrex %0, [%2]\n" |
| 168 | " mov %1, #0\n" |
| 169 | " teq %0, #0\n" |
| 170 | " strexeq %1, %3, [%2]" |
| 171 | : "=&r" (contended), "=&r" (res) |
| 172 | : "r" (&rw->lock), "r" (0x80000000) |
| 173 | : "cc"); |
| 174 | } while (res); |
Russell King | 4e8fd22 | 2005-07-24 12:13:40 +0100 | [diff] [blame] | 175 | |
Will Deacon | 00efaa0 | 2013-08-12 18:04:05 +0100 | [diff] [blame] | 176 | if (!contended) { |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 177 | smp_mb(); |
| 178 | return 1; |
| 179 | } else { |
| 180 | return 0; |
| 181 | } |
Russell King | 4e8fd22 | 2005-07-24 12:13:40 +0100 | [diff] [blame] | 182 | } |
| 183 | |
Thomas Gleixner | e593194 | 2009-12-03 20:08:46 +0100 | [diff] [blame] | 184 | static inline void arch_write_unlock(arch_rwlock_t *rw) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 185 | { |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 186 | smp_mb(); |
| 187 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | __asm__ __volatile__( |
Russell King | 00b4c90 | 2005-12-01 15:47:24 +0000 | [diff] [blame] | 189 | "str %1, [%0]\n" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 190 | : |
| 191 | : "r" (&rw->lock), "r" (0) |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 192 | : "cc"); |
Rabin Vincent | c5113b6 | 2010-01-25 19:43:03 +0100 | [diff] [blame] | 193 | |
| 194 | dsb_sev(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | } |
| 196 | |
Catalin Marinas | c2a4c40 | 2006-05-19 21:55:35 +0100 | [diff] [blame] | 197 | /* write_can_lock - would write_trylock() succeed? */ |
Will Deacon | 9bb17be | 2013-07-02 14:54:33 +0100 | [diff] [blame] | 198 | #define arch_write_can_lock(x) (ACCESS_ONCE((x)->lock) == 0) |
Catalin Marinas | c2a4c40 | 2006-05-19 21:55:35 +0100 | [diff] [blame] | 199 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | /* |
| 201 | * Read locks are a bit more hairy: |
| 202 | * - Exclusively load the lock value. |
| 203 | * - Increment it. |
| 204 | * - Store new lock value if positive, and we still own this location. |
| 205 | * If the value is negative, we've already failed. |
| 206 | * - If we failed to store the value, we want a negative result. |
| 207 | * - If we failed, try again. |
| 208 | * Unlocking is similarly hairy. We may have multiple read locks |
| 209 | * currently active. However, we know we won't have any write |
| 210 | * locks. |
| 211 | */ |
Thomas Gleixner | e593194 | 2009-12-03 20:08:46 +0100 | [diff] [blame] | 212 | static inline void arch_read_lock(arch_rwlock_t *rw) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | { |
| 214 | unsigned long tmp, tmp2; |
| 215 | |
Will Deacon | 9bb17be | 2013-07-02 14:54:33 +0100 | [diff] [blame] | 216 | prefetchw(&rw->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | __asm__ __volatile__( |
| 218 | "1: ldrex %0, [%2]\n" |
| 219 | " adds %0, %0, #1\n" |
| 220 | " strexpl %1, %0, [%2]\n" |
Russell King | 000d9c7 | 2011-01-15 16:22:12 +0000 | [diff] [blame] | 221 | WFE("mi") |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | " rsbpls %0, %1, #0\n" |
| 223 | " bmi 1b" |
| 224 | : "=&r" (tmp), "=&r" (tmp2) |
| 225 | : "r" (&rw->lock) |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 226 | : "cc"); |
| 227 | |
| 228 | smp_mb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | } |
| 230 | |
Thomas Gleixner | e593194 | 2009-12-03 20:08:46 +0100 | [diff] [blame] | 231 | static inline void arch_read_unlock(arch_rwlock_t *rw) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | { |
Russell King | 4e8fd22 | 2005-07-24 12:13:40 +0100 | [diff] [blame] | 233 | unsigned long tmp, tmp2; |
| 234 | |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 235 | smp_mb(); |
| 236 | |
Will Deacon | 9bb17be | 2013-07-02 14:54:33 +0100 | [diff] [blame] | 237 | prefetchw(&rw->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | __asm__ __volatile__( |
| 239 | "1: ldrex %0, [%2]\n" |
| 240 | " sub %0, %0, #1\n" |
| 241 | " strex %1, %0, [%2]\n" |
| 242 | " teq %1, #0\n" |
| 243 | " bne 1b" |
| 244 | : "=&r" (tmp), "=&r" (tmp2) |
| 245 | : "r" (&rw->lock) |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 246 | : "cc"); |
Rabin Vincent | c5113b6 | 2010-01-25 19:43:03 +0100 | [diff] [blame] | 247 | |
| 248 | if (tmp == 0) |
| 249 | dsb_sev(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 250 | } |
| 251 | |
Thomas Gleixner | e593194 | 2009-12-03 20:08:46 +0100 | [diff] [blame] | 252 | static inline int arch_read_trylock(arch_rwlock_t *rw) |
Russell King | 8e34703 | 2006-08-31 15:09:30 +0100 | [diff] [blame] | 253 | { |
Will Deacon | 00efaa0 | 2013-08-12 18:04:05 +0100 | [diff] [blame] | 254 | unsigned long contended, res; |
Russell King | 8e34703 | 2006-08-31 15:09:30 +0100 | [diff] [blame] | 255 | |
Will Deacon | 9bb17be | 2013-07-02 14:54:33 +0100 | [diff] [blame] | 256 | prefetchw(&rw->lock); |
Will Deacon | 00efaa0 | 2013-08-12 18:04:05 +0100 | [diff] [blame] | 257 | do { |
| 258 | __asm__ __volatile__( |
| 259 | " ldrex %0, [%2]\n" |
| 260 | " mov %1, #0\n" |
| 261 | " adds %0, %0, #1\n" |
| 262 | " strexpl %1, %0, [%2]" |
| 263 | : "=&r" (contended), "=&r" (res) |
| 264 | : "r" (&rw->lock) |
| 265 | : "cc"); |
| 266 | } while (res); |
Russell King | 8e34703 | 2006-08-31 15:09:30 +0100 | [diff] [blame] | 267 | |
Will Deacon | 00efaa0 | 2013-08-12 18:04:05 +0100 | [diff] [blame] | 268 | /* If the lock is negative, then it is already held for write. */ |
| 269 | if (contended < 0x80000000) { |
| 270 | smp_mb(); |
| 271 | return 1; |
| 272 | } else { |
| 273 | return 0; |
| 274 | } |
Russell King | 8e34703 | 2006-08-31 15:09:30 +0100 | [diff] [blame] | 275 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | |
Catalin Marinas | c2a4c40 | 2006-05-19 21:55:35 +0100 | [diff] [blame] | 277 | /* read_can_lock - would read_trylock() succeed? */ |
Will Deacon | 9bb17be | 2013-07-02 14:54:33 +0100 | [diff] [blame] | 278 | #define arch_read_can_lock(x) (ACCESS_ONCE((x)->lock) < 0x80000000) |
Catalin Marinas | c2a4c40 | 2006-05-19 21:55:35 +0100 | [diff] [blame] | 279 | |
Thomas Gleixner | e593194 | 2009-12-03 20:08:46 +0100 | [diff] [blame] | 280 | #define arch_read_lock_flags(lock, flags) arch_read_lock(lock) |
| 281 | #define arch_write_lock_flags(lock, flags) arch_write_lock(lock) |
Robin Holt | f5f7eac | 2009-04-02 16:59:46 -0700 | [diff] [blame] | 282 | |
Thomas Gleixner | 0199c4e | 2009-12-02 20:01:25 +0100 | [diff] [blame] | 283 | #define arch_spin_relax(lock) cpu_relax() |
| 284 | #define arch_read_relax(lock) cpu_relax() |
| 285 | #define arch_write_relax(lock) cpu_relax() |
Martin Schwidefsky | ef6edc9 | 2006-09-30 23:27:43 -0700 | [diff] [blame] | 286 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | #endif /* __ASM_SPINLOCK_H */ |