blob: f3f87ef30558bf970f7bffff62bc97536449ee33 [file] [log] [blame]
Hong Xucce783c2012-04-17 14:26:29 +08001/*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9N12 SoC";
14 compatible = "atmel,at91sam9n12";
15 interrupt-parent = <&aic>;
16
17 aliases {
18 serial0 = &dbgu;
19 serial1 = &usart0;
20 serial2 = &usart1;
21 serial3 = &usart2;
22 serial4 = &usart3;
23 gpio0 = &pioA;
24 gpio1 = &pioB;
25 gpio2 = &pioC;
26 gpio3 = &pioD;
27 tcb0 = &tcb0;
28 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020029 i2c0 = &i2c0;
30 i2c1 = &i2c1;
Bo Shen544ae6b2013-01-11 15:08:30 +010031 ssc0 = &ssc0;
Hong Xucce783c2012-04-17 14:26:29 +080032 };
33 cpus {
34 cpu@0 {
35 compatible = "arm,arm926ejs";
36 };
37 };
38
39 memory {
40 reg = <0x20000000 0x10000000>;
41 };
42
43 ahb {
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 apb {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54
55 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020056 #interrupt-cells = <3>;
Hong Xucce783c2012-04-17 14:26:29 +080057 compatible = "atmel,at91rm9200-aic";
58 interrupt-controller;
59 reg = <0xfffff000 0x200>;
60 };
61
62 ramc0: ramc@ffffe800 {
63 compatible = "atmel,at91sam9g45-ddramc";
64 reg = <0xffffe800 0x200>;
65 };
66
67 pmc: pmc@fffffc00 {
68 compatible = "atmel,at91rm9200-pmc";
69 reg = <0xfffffc00 0x100>;
70 };
71
72 rstc@fffffe00 {
73 compatible = "atmel,at91sam9g45-rstc";
74 reg = <0xfffffe00 0x10>;
75 };
76
77 pit: timer@fffffe30 {
78 compatible = "atmel,at91sam9260-pit";
79 reg = <0xfffffe30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020080 interrupts = <1 4 7>;
Hong Xucce783c2012-04-17 14:26:29 +080081 };
82
83 shdwc@fffffe10 {
84 compatible = "atmel,at91sam9x5-shdwc";
85 reg = <0xfffffe10 0x10>;
86 };
87
Ludovic Desroches98731372012-11-19 12:23:36 +010088 mmc0: mmc@f0008000 {
89 compatible = "atmel,hsmci";
90 reg = <0xf0008000 0x600>;
91 interrupts = <12 4 0>;
92 #address-cells = <1>;
93 #size-cells = <0>;
94 status = "disabled";
95 };
96
Hong Xucce783c2012-04-17 14:26:29 +080097 tcb0: timer@f8008000 {
98 compatible = "atmel,at91sam9x5-tcb";
99 reg = <0xf8008000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200100 interrupts = <17 4 0>;
Hong Xucce783c2012-04-17 14:26:29 +0800101 };
102
103 tcb1: timer@f800c000 {
104 compatible = "atmel,at91sam9x5-tcb";
105 reg = <0xf800c000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200106 interrupts = <17 4 0>;
Hong Xucce783c2012-04-17 14:26:29 +0800107 };
108
109 dma: dma-controller@ffffec00 {
110 compatible = "atmel,at91sam9g45-dma";
111 reg = <0xffffec00 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200112 interrupts = <20 4 0>;
Hong Xucce783c2012-04-17 14:26:29 +0800113 };
114
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800115 pinctrl@fffff400 {
116 #address-cells = <1>;
117 #size-cells = <1>;
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800118 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800119 ranges = <0xfffff400 0xfffff400 0x800>;
Hong Xucce783c2012-04-17 14:26:29 +0800120
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800121 atmel,mux-mask = <
122 /* A B C */
123 0xffffffff 0xffe07983 0x00000000 /* pioA */
124 0x00040000 0x00047e0f 0x00000000 /* pioB */
125 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
126 0x003fffff 0x003f8000 0x00000000 /* pioD */
127 >;
128
129 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800130 dbgu {
131 pinctrl_dbgu: dbgu-0 {
132 atmel,pins =
133 <0 9 0x1 0x0 /* PA9 periph A */
134 0 10 0x1 0x1>; /* PA10 periph with pullup */
135 };
136 };
137
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800138 usart0 {
139 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800140 atmel,pins =
141 <0 1 0x1 0x1 /* PA1 periph A with pullup */
142 0 0 0x1 0x0>; /* PA0 periph A */
143 };
144
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800145 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800146 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800147 <0 2 0x1 0x0>; /* PA2 periph A */
148 };
149
150 pinctrl_usart0_cts: usart0_cts-0 {
151 atmel,pins =
152 <0 3 0x1 0x0>; /* PA3 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800153 };
154 };
155
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800156 usart1 {
157 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800158 atmel,pins =
159 <0 6 0x1 0x1 /* PA6 periph A with pullup */
160 0 5 0x1 0x0>; /* PA5 periph A */
161 };
162 };
163
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800164 usart2 {
165 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800166 atmel,pins =
167 <0 8 0x1 0x1 /* PA8 periph A with pullup */
168 0 7 0x1 0x0>; /* PA7 periph A */
169 };
170
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800171 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800172 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800173 <1 0 0x2 0x0>; /* PB0 periph B */
174 };
175
176 pinctrl_usart2_cts: usart2_cts-0 {
177 atmel,pins =
178 <1 1 0x2 0x0>; /* PB1 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800179 };
180 };
181
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800182 usart3 {
183 pinctrl_usart3: usart3-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800184 atmel,pins =
185 <2 23 0x2 0x1 /* PC23 periph B with pullup */
186 2 22 0x2 0x0>; /* PC22 periph B */
187 };
188
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800189 pinctrl_usart3_rts: usart3_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800190 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800191 <2 24 0x2 0x0>; /* PC24 periph B */
192 };
193
194 pinctrl_usart3_cts: usart3_cts-0 {
195 atmel,pins =
196 <2 25 0x2 0x0>; /* PC25 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800197 };
198 };
199
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800200 uart0 {
201 pinctrl_uart0: uart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800202 atmel,pins =
203 <2 9 0x3 0x1 /* PC9 periph C with pullup */
204 2 8 0x3 0x0>; /* PC8 periph C */
205 };
206 };
207
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800208 uart1 {
209 pinctrl_uart1: uart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800210 atmel,pins =
211 <2 16 0x3 0x1 /* PC17 periph C with pullup */
212 2 17 0x3 0x0>; /* PC16 periph C */
213 };
214 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800215
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800216 nand {
217 pinctrl_nand: nand-0 {
218 atmel,pins =
219 <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
220 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
221 };
222 };
223
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800224 mmc0 {
225 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
226 atmel,pins =
227 <0 17 0x1 0x0 /* PA17 periph A */
228 0 16 0x1 0x1 /* PA16 periph A with pullup */
229 0 15 0x1 0x1>; /* PA15 periph A with pullup */
230 };
231
232 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
233 atmel,pins =
234 <0 18 0x1 0x1 /* PA18 periph A with pullup */
235 0 19 0x1 0x1 /* PA19 periph A with pullup */
236 0 20 0x1 0x1>; /* PA20 periph A with pullup */
237 };
238
239 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
240 atmel,pins =
241 <0 11 0x2 0x1 /* PA11 periph B with pullup */
242 0 12 0x2 0x1 /* PA12 periph B with pullup */
243 0 13 0x2 0x1 /* PA13 periph B with pullup */
244 0 14 0x2 0x1>; /* PA14 periph B with pullup */
245 };
246 };
247
Bo Shen544ae6b2013-01-11 15:08:30 +0100248 ssc0 {
249 pinctrl_ssc0_tx: ssc0_tx-0 {
250 atmel,pins =
251 <0 24 0x2 0x0 /* PA24 periph B */
252 0 25 0x2 0x0 /* PA25 periph B */
253 0 26 0x2 0x0>; /* PA26 periph B */
254 };
255
256 pinctrl_ssc0_rx: ssc0_rx-0 {
257 atmel,pins =
258 <0 27 0x2 0x0 /* PA27 periph B */
259 0 28 0x2 0x0 /* PA28 periph B */
260 0 29 0x2 0x0>; /* PA29 periph B */
261 };
262 };
263
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800264 pioA: gpio@fffff400 {
265 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
266 reg = <0xfffff400 0x200>;
267 interrupts = <2 4 1>;
268 #gpio-cells = <2>;
269 gpio-controller;
270 interrupt-controller;
271 #interrupt-cells = <2>;
272 };
Hong Xucce783c2012-04-17 14:26:29 +0800273
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800274 pioB: gpio@fffff600 {
275 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
276 reg = <0xfffff600 0x200>;
277 interrupts = <2 4 1>;
278 #gpio-cells = <2>;
279 gpio-controller;
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 };
Hong Xucce783c2012-04-17 14:26:29 +0800283
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800284 pioC: gpio@fffff800 {
285 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
286 reg = <0xfffff800 0x200>;
287 interrupts = <3 4 1>;
288 #gpio-cells = <2>;
289 gpio-controller;
290 interrupt-controller;
291 #interrupt-cells = <2>;
292 };
293
294 pioD: gpio@fffffa00 {
295 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
296 reg = <0xfffffa00 0x200>;
297 interrupts = <3 4 1>;
298 #gpio-cells = <2>;
299 gpio-controller;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 };
Hong Xucce783c2012-04-17 14:26:29 +0800303 };
304
305 dbgu: serial@fffff200 {
306 compatible = "atmel,at91sam9260-usart";
307 reg = <0xfffff200 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200308 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_dbgu>;
Hong Xucce783c2012-04-17 14:26:29 +0800311 status = "disabled";
312 };
313
Bo Shen544ae6b2013-01-11 15:08:30 +0100314 ssc0: ssc@f0010000 {
315 compatible = "atmel,at91sam9g45-ssc";
316 reg = <0xf0010000 0x4000>;
317 interrupts = <28 4 5>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
320 status = "disabled";
321 };
322
Hong Xucce783c2012-04-17 14:26:29 +0800323 usart0: serial@f801c000 {
324 compatible = "atmel,at91sam9260-usart";
325 reg = <0xf801c000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200326 interrupts = <5 4 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800327 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800328 pinctrl-0 = <&pinctrl_usart0>;
Hong Xucce783c2012-04-17 14:26:29 +0800329 status = "disabled";
330 };
331
332 usart1: serial@f8020000 {
333 compatible = "atmel,at91sam9260-usart";
334 reg = <0xf8020000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200335 interrupts = <6 4 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800336 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800337 pinctrl-0 = <&pinctrl_usart1>;
Hong Xucce783c2012-04-17 14:26:29 +0800338 status = "disabled";
339 };
340
341 usart2: serial@f8024000 {
342 compatible = "atmel,at91sam9260-usart";
343 reg = <0xf8024000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200344 interrupts = <7 4 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800345 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800346 pinctrl-0 = <&pinctrl_usart2>;
Hong Xucce783c2012-04-17 14:26:29 +0800347 status = "disabled";
348 };
349
350 usart3: serial@f8028000 {
351 compatible = "atmel,at91sam9260-usart";
352 reg = <0xf8028000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200353 interrupts = <8 4 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800354 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800355 pinctrl-0 = <&pinctrl_usart3>;
Hong Xucce783c2012-04-17 14:26:29 +0800356 status = "disabled";
357 };
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200358
359 i2c0: i2c@f8010000 {
360 compatible = "atmel,at91sam9x5-i2c";
361 reg = <0xf8010000 0x100>;
362 interrupts = <9 4 6>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365 status = "disabled";
366 };
367
368 i2c1: i2c@f8014000 {
369 compatible = "atmel,at91sam9x5-i2c";
370 reg = <0xf8014000 0x100>;
371 interrupts = <10 4 6>;
372 #address-cells = <1>;
373 #size-cells = <0>;
374 status = "disabled";
375 };
Richard Genoudd50f88a2013-04-03 14:02:18 +0800376
377 spi0: spi@f0000000 {
378 #address-cells = <1>;
379 #size-cells = <0>;
380 compatible = "atmel,at91rm9200-spi";
381 reg = <0xf0000000 0x100>;
382 interrupts = <13 4 3>;
383 status = "disabled";
384 };
385
386 spi1: spi@f0004000 {
387 #address-cells = <1>;
388 #size-cells = <0>;
389 compatible = "atmel,at91rm9200-spi";
390 reg = <0xf0004000 0x100>;
391 interrupts = <14 4 3>;
392 status = "disabled";
393 };
Hong Xucce783c2012-04-17 14:26:29 +0800394 };
395
396 nand0: nand@40000000 {
397 compatible = "atmel,at91rm9200-nand";
398 #address-cells = <1>;
399 #size-cells = <1>;
400 reg = < 0x40000000 0x10000000
401 0xffffe000 0x00000600
402 0xffffe600 0x00000200
Josh Wuc18c6b22013-01-23 20:47:10 +0800403 0x00108000 0x00018000
Hong Xucce783c2012-04-17 14:26:29 +0800404 >;
Josh Wuc18c6b22013-01-23 20:47:10 +0800405 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
Hong Xucce783c2012-04-17 14:26:29 +0800406 atmel,nand-addr-offset = <21>;
407 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_nand>;
Hong Xucce783c2012-04-17 14:26:29 +0800410 gpios = <&pioD 5 0
411 &pioD 4 0
412 0
413 >;
414 status = "disabled";
415 };
416
417 usb0: ohci@00500000 {
418 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
419 reg = <0x00500000 0x00100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200420 interrupts = <22 4 2>;
Hong Xucce783c2012-04-17 14:26:29 +0800421 status = "disabled";
422 };
423 };
424
425 i2c@0 {
426 compatible = "i2c-gpio";
427 gpios = <&pioA 30 0 /* sda */
428 &pioA 31 0 /* scl */
429 >;
430 i2c-gpio,sda-open-drain;
431 i2c-gpio,scl-open-drain;
432 i2c-gpio,delay-us = <2>; /* ~100 kHz */
433 #address-cells = <1>;
434 #size-cells = <0>;
435 status = "disabled";
436 };
437};