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gerrit-public.fairphone.software / kernel / msm-4.19 / d5553cb05a041d7c31e4e70950ecbb4ee52049cb / . / drivers / pinctrl / meson / pinctrl-meson8.c
blob: 7b1cc91733efaf6a5def1fc951660d7209eebf3a [file] [log] [blame]
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1/*
2 * Pin controller and GPIO driver for Amlogic Meson8.
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#include <dt-bindings/gpio/meson8-gpio.h>
15#include "pinctrl-meson.h"
16
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]17#define AO_OFF 120
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]18
19static const struct pinctrl_pin_desc meson8_pins[] = {
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]20 MESON_PIN(GPIOX_0, 0),
21 MESON_PIN(GPIOX_1, 0),
22 MESON_PIN(GPIOX_2, 0),
23 MESON_PIN(GPIOX_3, 0),
24 MESON_PIN(GPIOX_4, 0),
25 MESON_PIN(GPIOX_5, 0),
26 MESON_PIN(GPIOX_6, 0),
27 MESON_PIN(GPIOX_7, 0),
28 MESON_PIN(GPIOX_8, 0),
29 MESON_PIN(GPIOX_9, 0),
30 MESON_PIN(GPIOX_10, 0),
31 MESON_PIN(GPIOX_11, 0),
32 MESON_PIN(GPIOX_12, 0),
33 MESON_PIN(GPIOX_13, 0),
34 MESON_PIN(GPIOX_14, 0),
35 MESON_PIN(GPIOX_15, 0),
36 MESON_PIN(GPIOX_16, 0),
37 MESON_PIN(GPIOX_17, 0),
38 MESON_PIN(GPIOX_18, 0),
39 MESON_PIN(GPIOX_19, 0),
40 MESON_PIN(GPIOX_20, 0),
41 MESON_PIN(GPIOX_21, 0),
42 MESON_PIN(GPIOY_0, 0),
43 MESON_PIN(GPIOY_1, 0),
44 MESON_PIN(GPIOY_2, 0),
45 MESON_PIN(GPIOY_3, 0),
46 MESON_PIN(GPIOY_4, 0),
47 MESON_PIN(GPIOY_5, 0),
48 MESON_PIN(GPIOY_6, 0),
49 MESON_PIN(GPIOY_7, 0),
50 MESON_PIN(GPIOY_8, 0),
51 MESON_PIN(GPIOY_9, 0),
52 MESON_PIN(GPIOY_10, 0),
53 MESON_PIN(GPIOY_11, 0),
54 MESON_PIN(GPIOY_12, 0),
55 MESON_PIN(GPIOY_13, 0),
56 MESON_PIN(GPIOY_14, 0),
57 MESON_PIN(GPIOY_15, 0),
58 MESON_PIN(GPIOY_16, 0),
59 MESON_PIN(GPIODV_0, 0),
60 MESON_PIN(GPIODV_1, 0),
61 MESON_PIN(GPIODV_2, 0),
62 MESON_PIN(GPIODV_3, 0),
63 MESON_PIN(GPIODV_4, 0),
64 MESON_PIN(GPIODV_5, 0),
65 MESON_PIN(GPIODV_6, 0),
66 MESON_PIN(GPIODV_7, 0),
67 MESON_PIN(GPIODV_8, 0),
68 MESON_PIN(GPIODV_9, 0),
69 MESON_PIN(GPIODV_10, 0),
70 MESON_PIN(GPIODV_11, 0),
71 MESON_PIN(GPIODV_12, 0),
72 MESON_PIN(GPIODV_13, 0),
73 MESON_PIN(GPIODV_14, 0),
74 MESON_PIN(GPIODV_15, 0),
75 MESON_PIN(GPIODV_16, 0),
76 MESON_PIN(GPIODV_17, 0),
77 MESON_PIN(GPIODV_18, 0),
78 MESON_PIN(GPIODV_19, 0),
79 MESON_PIN(GPIODV_20, 0),
80 MESON_PIN(GPIODV_21, 0),
81 MESON_PIN(GPIODV_22, 0),
82 MESON_PIN(GPIODV_23, 0),
83 MESON_PIN(GPIODV_24, 0),
84 MESON_PIN(GPIODV_25, 0),
85 MESON_PIN(GPIODV_26, 0),
86 MESON_PIN(GPIODV_27, 0),
87 MESON_PIN(GPIODV_28, 0),
88 MESON_PIN(GPIODV_29, 0),
89 MESON_PIN(GPIOH_0, 0),
90 MESON_PIN(GPIOH_1, 0),
91 MESON_PIN(GPIOH_2, 0),
92 MESON_PIN(GPIOH_3, 0),
93 MESON_PIN(GPIOH_4, 0),
94 MESON_PIN(GPIOH_5, 0),
95 MESON_PIN(GPIOH_6, 0),
96 MESON_PIN(GPIOH_7, 0),
97 MESON_PIN(GPIOH_8, 0),
98 MESON_PIN(GPIOH_9, 0),
99 MESON_PIN(GPIOZ_0, 0),
100 MESON_PIN(GPIOZ_1, 0),
101 MESON_PIN(GPIOZ_2, 0),
102 MESON_PIN(GPIOZ_3, 0),
103 MESON_PIN(GPIOZ_4, 0),
104 MESON_PIN(GPIOZ_5, 0),
105 MESON_PIN(GPIOZ_6, 0),
106 MESON_PIN(GPIOZ_7, 0),
107 MESON_PIN(GPIOZ_8, 0),
108 MESON_PIN(GPIOZ_9, 0),
109 MESON_PIN(GPIOZ_10, 0),
110 MESON_PIN(GPIOZ_11, 0),
111 MESON_PIN(GPIOZ_12, 0),
112 MESON_PIN(GPIOZ_13, 0),
113 MESON_PIN(GPIOZ_14, 0),
114 MESON_PIN(CARD_0, 0),
115 MESON_PIN(CARD_1, 0),
116 MESON_PIN(CARD_2, 0),
117 MESON_PIN(CARD_3, 0),
118 MESON_PIN(CARD_4, 0),
119 MESON_PIN(CARD_5, 0),
120 MESON_PIN(CARD_6, 0),
121 MESON_PIN(BOOT_0, 0),
122 MESON_PIN(BOOT_1, 0),
123 MESON_PIN(BOOT_2, 0),
124 MESON_PIN(BOOT_3, 0),
125 MESON_PIN(BOOT_4, 0),
126 MESON_PIN(BOOT_5, 0),
127 MESON_PIN(BOOT_6, 0),
128 MESON_PIN(BOOT_7, 0),
129 MESON_PIN(BOOT_8, 0),
130 MESON_PIN(BOOT_9, 0),
131 MESON_PIN(BOOT_10, 0),
132 MESON_PIN(BOOT_11, 0),
133 MESON_PIN(BOOT_12, 0),
134 MESON_PIN(BOOT_13, 0),
135 MESON_PIN(BOOT_14, 0),
136 MESON_PIN(BOOT_15, 0),
137 MESON_PIN(BOOT_16, 0),
138 MESON_PIN(BOOT_17, 0),
139 MESON_PIN(BOOT_18, 0),
140 MESON_PIN(GPIOAO_0, AO_OFF),
141 MESON_PIN(GPIOAO_1, AO_OFF),
142 MESON_PIN(GPIOAO_2, AO_OFF),
143 MESON_PIN(GPIOAO_3, AO_OFF),
144 MESON_PIN(GPIOAO_4, AO_OFF),
145 MESON_PIN(GPIOAO_5, AO_OFF),
146 MESON_PIN(GPIOAO_6, AO_OFF),
147 MESON_PIN(GPIOAO_7, AO_OFF),
148 MESON_PIN(GPIOAO_8, AO_OFF),
149 MESON_PIN(GPIOAO_9, AO_OFF),
150 MESON_PIN(GPIOAO_10, AO_OFF),
151 MESON_PIN(GPIOAO_11, AO_OFF),
152 MESON_PIN(GPIOAO_12, AO_OFF),
153 MESON_PIN(GPIOAO_13, AO_OFF),
154 MESON_PIN(GPIO_BSD_EN, AO_OFF),
155 MESON_PIN(GPIO_TEST_N, AO_OFF),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]156};
157
158/* bank X */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]159static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) };
160static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) };
161static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) };
162static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) };
163static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) };
164static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]165
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]166static const unsigned int sdxc_d0_a_pins[] = { PIN(GPIOX_0, 0) };
167static const unsigned int sdxc_d13_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0),
168 PIN(GPIOX_3, 0) };
169static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0),
170 PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) };
171static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) };
172static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]173
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]174static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) };
175static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) };
176static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) };
177static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]178
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]179static const unsigned int uart_tx_a0_pins[] = { PIN(GPIOX_4, 0) };
180static const unsigned int uart_rx_a0_pins[] = { PIN(GPIOX_5, 0) };
181static const unsigned int uart_cts_a0_pins[] = { PIN(GPIOX_6, 0) };
182static const unsigned int uart_rts_a0_pins[] = { PIN(GPIOX_7, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]183
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]184static const unsigned int uart_tx_a1_pins[] = { PIN(GPIOX_12, 0) };
185static const unsigned int uart_rx_a1_pins[] = { PIN(GPIOX_13, 0) };
186static const unsigned int uart_cts_a1_pins[] = { PIN(GPIOX_14, 0) };
187static const unsigned int uart_rts_a1_pins[] = { PIN(GPIOX_15, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]188
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]189static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) };
190static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) };
191static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) };
192static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]193
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]194static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) };
195static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) };
196static const unsigned int iso7816_clk_pins[] = { PIN(GPIOX_18, 0) };
197static const unsigned int iso7816_data_pins[] = { PIN(GPIOX_19, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]198
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]199static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) };
200static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]201
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]202static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) };
203static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]204
205/* bank Y */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]206static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_0, 0) };
207static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_1, 0) };
208static const unsigned int uart_cts_c_pins[] = { PIN(GPIOY_2, 0) };
209static const unsigned int uart_rts_c_pins[] = { PIN(GPIOY_3, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]210
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]211static const unsigned int pcm_out_b_pins[] = { PIN(GPIOY_4, 0) };
212static const unsigned int pcm_in_b_pins[] = { PIN(GPIOY_5, 0) };
213static const unsigned int pcm_fs_b_pins[] = { PIN(GPIOY_6, 0) };
214static const unsigned int pcm_clk_b_pins[] = { PIN(GPIOY_7, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]215
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]216static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIOY_0, 0) };
217static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIOY_1, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]218
219/* bank DV */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]220static const unsigned int dvin_rgb_pins[] = { PIN(GPIODV_0, 0), PIN(GPIODV_1, 0),
221 PIN(GPIODV_2, 0), PIN(GPIODV_3, 0),
222 PIN(GPIODV_4, 0), PIN(GPIODV_5, 0),
223 PIN(GPIODV_6, 0), PIN(GPIODV_7, 0),
224 PIN(GPIODV_8, 0), PIN(GPIODV_9, 0),
225 PIN(GPIODV_10, 0), PIN(GPIODV_11, 0),
226 PIN(GPIODV_12, 0), PIN(GPIODV_13, 0),
227 PIN(GPIODV_14, 0), PIN(GPIODV_15, 0),
228 PIN(GPIODV_16, 0), PIN(GPIODV_17, 0),
229 PIN(GPIODV_18, 0), PIN(GPIODV_19, 0),
230 PIN(GPIODV_20, 0), PIN(GPIODV_21, 0),
231 PIN(GPIODV_22, 0), PIN(GPIODV_23, 0) };
232static const unsigned int dvin_vs_pins[] = { PIN(GPIODV_24, 0) };
233static const unsigned int dvin_hs_pins[] = { PIN(GPIODV_25, 0) };
234static const unsigned int dvin_clk_pins[] = { PIN(GPIODV_26, 0) };
235static const unsigned int dvin_de_pins[] = { PIN(GPIODV_27, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]236
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]237static const unsigned int enc_0_pins[] = { PIN(GPIODV_0, 0) };
238static const unsigned int enc_1_pins[] = { PIN(GPIODV_1, 0) };
239static const unsigned int enc_2_pins[] = { PIN(GPIODV_2, 0) };
240static const unsigned int enc_3_pins[] = { PIN(GPIODV_3, 0) };
241static const unsigned int enc_4_pins[] = { PIN(GPIODV_4, 0) };
242static const unsigned int enc_5_pins[] = { PIN(GPIODV_5, 0) };
243static const unsigned int enc_6_pins[] = { PIN(GPIODV_6, 0) };
244static const unsigned int enc_7_pins[] = { PIN(GPIODV_7, 0) };
245static const unsigned int enc_8_pins[] = { PIN(GPIODV_8, 0) };
246static const unsigned int enc_9_pins[] = { PIN(GPIODV_9, 0) };
247static const unsigned int enc_10_pins[] = { PIN(GPIODV_10, 0) };
248static const unsigned int enc_11_pins[] = { PIN(GPIODV_11, 0) };
249static const unsigned int enc_12_pins[] = { PIN(GPIODV_12, 0) };
250static const unsigned int enc_13_pins[] = { PIN(GPIODV_13, 0) };
251static const unsigned int enc_14_pins[] = { PIN(GPIODV_14, 0) };
252static const unsigned int enc_15_pins[] = { PIN(GPIODV_15, 0) };
253static const unsigned int enc_16_pins[] = { PIN(GPIODV_16, 0) };
254static const unsigned int enc_17_pins[] = { PIN(GPIODV_17, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]255
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]256static const unsigned int uart_tx_b1_pins[] = { PIN(GPIODV_24, 0) };
257static const unsigned int uart_rx_b1_pins[] = { PIN(GPIODV_25, 0) };
258static const unsigned int uart_cts_b1_pins[] = { PIN(GPIODV_26, 0) };
259static const unsigned int uart_rts_b1_pins[] = { PIN(GPIODV_27, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]260
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]261static const unsigned int vga_vs_pins[] = { PIN(GPIODV_24, 0) };
262static const unsigned int vga_hs_pins[] = { PIN(GPIODV_25, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]263
264/* bank H */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]265static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) };
266static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) };
267static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) };
268static const unsigned int hdmi_cec_pins[] = { PIN(GPIOH_3, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]269
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]270static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOH_3, 0) };
271static const unsigned int spi_miso_0_pins[] = { PIN(GPIOH_4, 0) };
272static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOH_5, 0) };
273static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOH_6, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]274
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]275static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) };
276static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]277
278/* bank Z */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]279static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOZ_9, 0) };
280static const unsigned int spi_ss1_1_pins[] = { PIN(GPIOZ_10, 0) };
281static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOZ_11, 0) };
282static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOZ_12, 0) };
283static const unsigned int spi_miso_1_pins[] = { PIN(GPIOZ_13, 0) };
284static const unsigned int spi_ss2_1_pins[] = { PIN(GPIOZ_14, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]285
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]286static const unsigned int eth_tx_clk_50m_pins[] = { PIN(GPIOZ_4, 0) };
287static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_5, 0) };
288static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_6, 0) };
289static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_7, 0) };
290static const unsigned int eth_rx_clk_in_pins[] = { PIN(GPIOZ_8, 0) };
291static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_9, 0) };
292static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_10, 0) };
293static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_11, 0) };
294static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_12, 0) };
295static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_13, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]296
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]297static const unsigned int i2c_sda_a0_pins[] = { PIN(GPIOZ_0, 0) };
298static const unsigned int i2c_sck_a0_pins[] = { PIN(GPIOZ_1, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]299
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]300static const unsigned int i2c_sda_b_pins[] = { PIN(GPIOZ_2, 0) };
301static const unsigned int i2c_sck_b_pins[] = { PIN(GPIOZ_3, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]302
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]303static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOZ_4, 0) };
304static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOZ_5, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]305
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]306static const unsigned int i2c_sda_a1_pins[] = { PIN(GPIOZ_0, 0) };
307static const unsigned int i2c_sck_a1_pins[] = { PIN(GPIOZ_1, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]308
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]309static const unsigned int i2c_sda_a2_pins[] = { PIN(GPIOZ_0, 0) };
310static const unsigned int i2c_sck_a2_pins[] = { PIN(GPIOZ_1, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]311
312/* bank BOOT */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]313static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) };
314static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) };
315static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) };
316static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) };
317static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_16, 0) };
318static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_17, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]319
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]320static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)};
321static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0),
322 PIN(BOOT_3, 0) };
323static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0),
324 PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
325static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_16, 0) };
326static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_17, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]327
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]328static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0),
329 PIN(BOOT_2, 0), PIN(BOOT_3, 0),
330 PIN(BOOT_4, 0), PIN(BOOT_5, 0),
331 PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
332static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) };
333static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) };
334static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) };
335static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) };
336static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) };
337static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) };
338static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) };
339static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, 0) };
340static const unsigned int nand_ce2_pins[] = { PIN(BOOT_16, 0) };
341static const unsigned int nand_ce3_pins[] = { PIN(BOOT_17, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]342
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]343static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) };
344static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) };
345static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) };
346static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]347
348/* bank CARD */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]349static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) };
350static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) };
351static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) };
352static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) };
353static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) };
354static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]355
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]356static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0),
357 PIN(CARD_5, 0) };
358static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) };
359static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) };
360static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]361
362/* bank AO */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]363static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) };
364static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) };
365static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) };
366static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]367
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]368static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]369
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]370static const unsigned int i2c_slave_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
371static const unsigned int i2c_slave_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]372
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]373static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) };
374static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]375
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]376static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) };
377static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]378
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]379static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
380static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]381
382static struct meson_pmx_group meson8_groups[] = {
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]383 GPIO_GROUP(GPIOX_0, 0),
384 GPIO_GROUP(GPIOX_1, 0),
385 GPIO_GROUP(GPIOX_2, 0),
386 GPIO_GROUP(GPIOX_3, 0),
387 GPIO_GROUP(GPIOX_4, 0),
388 GPIO_GROUP(GPIOX_5, 0),
389 GPIO_GROUP(GPIOX_6, 0),
390 GPIO_GROUP(GPIOX_7, 0),
391 GPIO_GROUP(GPIOX_8, 0),
392 GPIO_GROUP(GPIOX_9, 0),
393 GPIO_GROUP(GPIOX_10, 0),
394 GPIO_GROUP(GPIOX_11, 0),
395 GPIO_GROUP(GPIOX_12, 0),
396 GPIO_GROUP(GPIOX_13, 0),
397 GPIO_GROUP(GPIOX_14, 0),
398 GPIO_GROUP(GPIOX_15, 0),
399 GPIO_GROUP(GPIOX_16, 0),
400 GPIO_GROUP(GPIOX_17, 0),
401 GPIO_GROUP(GPIOX_18, 0),
402 GPIO_GROUP(GPIOX_19, 0),
403 GPIO_GROUP(GPIOX_20, 0),
404 GPIO_GROUP(GPIOX_21, 0),
405 GPIO_GROUP(GPIOY_0, 0),
406 GPIO_GROUP(GPIOY_1, 0),
407 GPIO_GROUP(GPIOY_2, 0),
408 GPIO_GROUP(GPIOY_3, 0),
409 GPIO_GROUP(GPIOY_4, 0),
410 GPIO_GROUP(GPIOY_5, 0),
411 GPIO_GROUP(GPIOY_6, 0),
412 GPIO_GROUP(GPIOY_7, 0),
413 GPIO_GROUP(GPIOY_8, 0),
414 GPIO_GROUP(GPIOY_9, 0),
415 GPIO_GROUP(GPIOY_10, 0),
416 GPIO_GROUP(GPIOY_11, 0),
417 GPIO_GROUP(GPIOY_12, 0),
418 GPIO_GROUP(GPIOY_13, 0),
419 GPIO_GROUP(GPIOY_14, 0),
420 GPIO_GROUP(GPIOY_15, 0),
421 GPIO_GROUP(GPIOY_16, 0),
422 GPIO_GROUP(GPIODV_0, 0),
423 GPIO_GROUP(GPIODV_1, 0),
424 GPIO_GROUP(GPIODV_2, 0),
425 GPIO_GROUP(GPIODV_3, 0),
426 GPIO_GROUP(GPIODV_4, 0),
427 GPIO_GROUP(GPIODV_5, 0),
428 GPIO_GROUP(GPIODV_6, 0),
429 GPIO_GROUP(GPIODV_7, 0),
430 GPIO_GROUP(GPIODV_8, 0),
431 GPIO_GROUP(GPIODV_9, 0),
432 GPIO_GROUP(GPIODV_10, 0),
433 GPIO_GROUP(GPIODV_11, 0),
434 GPIO_GROUP(GPIODV_12, 0),
435 GPIO_GROUP(GPIODV_13, 0),
436 GPIO_GROUP(GPIODV_14, 0),
437 GPIO_GROUP(GPIODV_15, 0),
438 GPIO_GROUP(GPIODV_16, 0),
439 GPIO_GROUP(GPIODV_17, 0),
440 GPIO_GROUP(GPIODV_18, 0),
441 GPIO_GROUP(GPIODV_19, 0),
442 GPIO_GROUP(GPIODV_20, 0),
443 GPIO_GROUP(GPIODV_21, 0),
444 GPIO_GROUP(GPIODV_22, 0),
445 GPIO_GROUP(GPIODV_23, 0),
446 GPIO_GROUP(GPIODV_24, 0),
447 GPIO_GROUP(GPIODV_25, 0),
448 GPIO_GROUP(GPIODV_26, 0),
449 GPIO_GROUP(GPIODV_27, 0),
450 GPIO_GROUP(GPIODV_28, 0),
451 GPIO_GROUP(GPIODV_29, 0),
452 GPIO_GROUP(GPIOH_0, 0),
453 GPIO_GROUP(GPIOH_1, 0),
454 GPIO_GROUP(GPIOH_2, 0),
455 GPIO_GROUP(GPIOH_3, 0),
456 GPIO_GROUP(GPIOH_4, 0),
457 GPIO_GROUP(GPIOH_5, 0),
458 GPIO_GROUP(GPIOH_6, 0),
459 GPIO_GROUP(GPIOH_7, 0),
460 GPIO_GROUP(GPIOH_8, 0),
461 GPIO_GROUP(GPIOH_9, 0),
462 GPIO_GROUP(GPIOZ_0, 0),
463 GPIO_GROUP(GPIOZ_1, 0),
464 GPIO_GROUP(GPIOZ_2, 0),
465 GPIO_GROUP(GPIOZ_3, 0),
466 GPIO_GROUP(GPIOZ_4, 0),
467 GPIO_GROUP(GPIOZ_5, 0),
468 GPIO_GROUP(GPIOZ_6, 0),
469 GPIO_GROUP(GPIOZ_7, 0),
470 GPIO_GROUP(GPIOZ_8, 0),
471 GPIO_GROUP(GPIOZ_9, 0),
472 GPIO_GROUP(GPIOZ_10, 0),
473 GPIO_GROUP(GPIOZ_11, 0),
474 GPIO_GROUP(GPIOZ_12, 0),
475 GPIO_GROUP(GPIOZ_13, 0),
476 GPIO_GROUP(GPIOZ_14, 0),
477 GPIO_GROUP(GPIOAO_0, AO_OFF),
478 GPIO_GROUP(GPIOAO_1, AO_OFF),
479 GPIO_GROUP(GPIOAO_2, AO_OFF),
480 GPIO_GROUP(GPIOAO_3, AO_OFF),
481 GPIO_GROUP(GPIOAO_4, AO_OFF),
482 GPIO_GROUP(GPIOAO_5, AO_OFF),
483 GPIO_GROUP(GPIOAO_6, AO_OFF),
484 GPIO_GROUP(GPIOAO_7, AO_OFF),
485 GPIO_GROUP(GPIOAO_8, AO_OFF),
486 GPIO_GROUP(GPIOAO_9, AO_OFF),
487 GPIO_GROUP(GPIOAO_10, AO_OFF),
488 GPIO_GROUP(GPIOAO_11, AO_OFF),
489 GPIO_GROUP(GPIOAO_12, AO_OFF),
490 GPIO_GROUP(GPIOAO_13, AO_OFF),
491 GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
492 GPIO_GROUP(GPIO_TEST_N, AO_OFF),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]493
494 /* bank X */
495 GROUP(sd_d0_a, 8, 5),
496 GROUP(sd_d1_a, 8, 4),
497 GROUP(sd_d2_a, 8, 3),
498 GROUP(sd_d3_a, 8, 2),
499 GROUP(sd_clk_a, 8, 1),
500 GROUP(sd_cmd_a, 8, 0),
501
502 GROUP(sdxc_d0_a, 5, 14),
503 GROUP(sdxc_d13_a, 5, 13),
504 GROUP(sdxc_d47_a, 5, 12),
505 GROUP(sdxc_clk_a, 5, 11),
506 GROUP(sdxc_cmd_a, 5, 10),
507
508 GROUP(pcm_out_a, 3, 30),
509 GROUP(pcm_in_a, 3, 29),
510 GROUP(pcm_fs_a, 3, 28),
511 GROUP(pcm_clk_a, 3, 27),
512
513 GROUP(uart_tx_a0, 4, 17),
514 GROUP(uart_rx_a0, 4, 16),
515 GROUP(uart_cts_a0, 4, 15),
516 GROUP(uart_rts_a0, 4, 14),
517
518 GROUP(uart_tx_a1, 4, 13),
519 GROUP(uart_rx_a1, 4, 12),
520 GROUP(uart_cts_a1, 4, 11),
521 GROUP(uart_rts_a1, 4, 10),
522
523 GROUP(uart_tx_b0, 4, 9),
524 GROUP(uart_rx_b0, 4, 8),
525 GROUP(uart_cts_b0, 4, 7),
526 GROUP(uart_rts_b0, 4, 6),
527
528 GROUP(iso7816_det, 4, 21),
529 GROUP(iso7816_reset, 4, 20),
530 GROUP(iso7816_clk, 4, 19),
531 GROUP(iso7816_data, 4, 18),
532
533 GROUP(i2c_sda_d0, 4, 5),
534 GROUP(i2c_sck_d0, 4, 4),
535
536 GROUP(xtal_32k_out, 3, 22),
537 GROUP(xtal_24m_out, 3, 23),
538
539 /* bank Y */
540 GROUP(uart_tx_c, 1, 19),
541 GROUP(uart_rx_c, 1, 18),
542 GROUP(uart_cts_c, 1, 17),
543 GROUP(uart_rts_c, 1, 16),
544
545 GROUP(pcm_out_b, 4, 25),
546 GROUP(pcm_in_b, 4, 24),
547 GROUP(pcm_fs_b, 4, 23),
548 GROUP(pcm_clk_b, 4, 22),
549
550 GROUP(i2c_sda_c0, 1, 15),
551 GROUP(i2c_sck_c0, 1, 14),
552
553 /* bank DV */
554 GROUP(dvin_rgb, 0, 6),
555 GROUP(dvin_vs, 0, 9),
556 GROUP(dvin_hs, 0, 8),
557 GROUP(dvin_clk, 0, 7),
558 GROUP(dvin_de, 0, 10),
559
560 GROUP(enc_0, 7, 0),
561 GROUP(enc_1, 7, 1),
562 GROUP(enc_2, 7, 2),
563 GROUP(enc_3, 7, 3),
564 GROUP(enc_4, 7, 4),
565 GROUP(enc_5, 7, 5),
566 GROUP(enc_6, 7, 6),
567 GROUP(enc_7, 7, 7),
568 GROUP(enc_8, 7, 8),
569 GROUP(enc_9, 7, 9),
570 GROUP(enc_10, 7, 10),
571 GROUP(enc_11, 7, 11),
572 GROUP(enc_12, 7, 12),
573 GROUP(enc_13, 7, 13),
574 GROUP(enc_14, 7, 14),
575 GROUP(enc_15, 7, 15),
576 GROUP(enc_16, 7, 16),
577 GROUP(enc_17, 7, 17),
578
579 GROUP(uart_tx_b1, 6, 23),
580 GROUP(uart_rx_b1, 6, 22),
581 GROUP(uart_cts_b1, 6, 21),
582 GROUP(uart_rts_b1, 6, 20),
583
584 GROUP(vga_vs, 0, 21),
585 GROUP(vga_hs, 0, 20),
586
587 /* bank H */
588 GROUP(hdmi_hpd, 1, 26),
589 GROUP(hdmi_sda, 1, 25),
590 GROUP(hdmi_scl, 1, 24),
591 GROUP(hdmi_cec, 1, 23),
592
593 GROUP(spi_ss0_0, 9, 13),
594 GROUP(spi_miso_0, 9, 12),
595 GROUP(spi_mosi_0, 9, 11),
596 GROUP(spi_sclk_0, 9, 10),
597
598 GROUP(i2c_sda_d1, 4, 3),
599 GROUP(i2c_sck_d1, 4, 2),
600
601 /* bank Z */
602 GROUP(spi_ss0_1, 8, 16),
603 GROUP(spi_ss1_1, 8, 12),
604 GROUP(spi_sclk_1, 8, 15),
605 GROUP(spi_mosi_1, 8, 14),
606 GROUP(spi_miso_1, 8, 13),
607 GROUP(spi_ss2_1, 8, 17),
608
609 GROUP(eth_tx_clk_50m, 6, 15),
610 GROUP(eth_tx_en, 6, 14),
611 GROUP(eth_txd1, 6, 13),
612 GROUP(eth_txd0, 6, 12),
613 GROUP(eth_rx_clk_in, 6, 10),
614 GROUP(eth_rx_dv, 6, 11),
615 GROUP(eth_rxd1, 6, 8),
616 GROUP(eth_rxd0, 6, 7),
617 GROUP(eth_mdio, 6, 6),
618 GROUP(eth_mdc, 6, 5),
619
620 GROUP(i2c_sda_a0, 5, 31),
621 GROUP(i2c_sck_a0, 5, 30),
622
623 GROUP(i2c_sda_b, 5, 27),
624 GROUP(i2c_sck_b, 5, 26),
625
626 GROUP(i2c_sda_c1, 5, 25),
627 GROUP(i2c_sck_c1, 5, 24),
628
629 GROUP(i2c_sda_a1, 5, 9),
630 GROUP(i2c_sck_a1, 5, 8),
631
632 GROUP(i2c_sda_a2, 5, 7),
633 GROUP(i2c_sck_a2, 5, 6),
634
635 /* bank BOOT */
636 GROUP(sd_d0_c, 6, 29),
637 GROUP(sd_d1_c, 6, 28),
638 GROUP(sd_d2_c, 6, 27),
639 GROUP(sd_d3_c, 6, 26),
640 GROUP(sd_cmd_c, 6, 25),
641 GROUP(sd_clk_c, 6, 24),
642
643 GROUP(sdxc_d0_c, 4, 30),
644 GROUP(sdxc_d13_c, 4, 29),
645 GROUP(sdxc_d47_c, 4, 28),
646 GROUP(sdxc_cmd_c, 4, 27),
647 GROUP(sdxc_clk_c, 4, 26),
648
649 GROUP(nand_io, 2, 26),
650 GROUP(nand_io_ce0, 2, 25),
651 GROUP(nand_io_ce1, 2, 24),
652 GROUP(nand_io_rb0, 2, 17),
653 GROUP(nand_ale, 2, 21),
654 GROUP(nand_cle, 2, 20),
655 GROUP(nand_wen_clk, 2, 19),
656 GROUP(nand_ren_clk, 2, 18),
657 GROUP(nand_dqs, 2, 27),
658 GROUP(nand_ce2, 2, 23),
659 GROUP(nand_ce3, 2, 22),
660
661 GROUP(nor_d, 5, 1),
662 GROUP(nor_q, 5, 3),
663 GROUP(nor_c, 5, 2),
664 GROUP(nor_cs, 5, 0),
665
666 /* bank CARD */
667 GROUP(sd_d1_b, 2, 14),
668 GROUP(sd_d0_b, 2, 15),
669 GROUP(sd_clk_b, 2, 11),
670 GROUP(sd_cmd_b, 2, 10),
671 GROUP(sd_d3_b, 2, 12),
672 GROUP(sd_d2_b, 2, 13),
673
674 GROUP(sdxc_d13_b, 2, 6),
675 GROUP(sdxc_d0_b, 2, 7),
676 GROUP(sdxc_clk_b, 2, 5),
677 GROUP(sdxc_cmd_b, 2, 4),
678
679 /* bank AO */
680 GROUP_AO(uart_tx_ao_a, 0, 12),
681 GROUP_AO(uart_rx_ao_a, 0, 11),
682 GROUP_AO(uart_cts_ao_a, 0, 10),
683 GROUP_AO(uart_rts_ao_a, 0, 9),
684
685 GROUP_AO(remote_input, 0, 0),
686
687 GROUP_AO(i2c_slave_sck_ao, 0, 2),
688 GROUP_AO(i2c_slave_sda_ao, 0, 1),
689
690 GROUP_AO(uart_tx_ao_b0, 0, 26),
691 GROUP_AO(uart_rx_ao_b0, 0, 25),
692
693 GROUP_AO(uart_tx_ao_b1, 0, 24),
694 GROUP_AO(uart_rx_ao_b1, 0, 23),
695
696 GROUP_AO(i2c_mst_sck_ao, 0, 6),
697 GROUP_AO(i2c_mst_sda_ao, 0, 5),
698};
699
700static const char * const gpio_groups[] = {
701 "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
702 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
703 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
704 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
705 "GPIOX_20", "GPIOX_21",
706
707 "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
708 "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
709 "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
710 "GPIOY_15", "GPIOY_16",
711
712 "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
713 "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
714 "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
715 "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
716 "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
717 "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
718
719 "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
720 "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
721
722 "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
723 "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
724 "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
725
726 "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
727 "CARD_5", "CARD_6",
728
729 "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
730 "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
731 "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
732 "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
733
734 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
735 "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
736 "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
737 "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N"
738};
739
740static const char * const sd_a_groups[] = {
741 "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a"
742};
743
744static const char * const sdxc_a_groups[] = {
745 "sdxc_d0_a", "sdxc_d13_a", "sdxc_d47_a", "sdxc_clk_a", "sdxc_cmd_a"
746};
747
748static const char * const pcm_a_groups[] = {
749 "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
750};
751
752static const char * const uart_a_groups[] = {
753 "uart_tx_a0", "uart_rx_a0", "uart_cts_a0", "uart_rts_a0",
754 "uart_tx_a1", "uart_rx_a1", "uart_cts_a1", "uart_rts_a1"
755};
756
757static const char * const uart_b_groups[] = {
758 "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
759 "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
760};
761
762static const char * const iso7816_groups[] = {
763 "iso7816_det", "iso7816_reset", "iso7816_clk", "iso7816_data"
764};
765
766static const char * const i2c_d_groups[] = {
767 "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
768};
769
770static const char * const xtal_groups[] = {
771 "xtal_32k_out", "xtal_24m_out"
772};
773
774static const char * const uart_c_groups[] = {
775 "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
776};
777
778static const char * const pcm_b_groups[] = {
779 "pcm_out_b", "pcm_in_b", "pcm_fs_b", "pcm_clk_b"
780};
781
782static const char * const i2c_c_groups[] = {
783 "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
784};
785
786static const char * const dvin_groups[] = {
787 "dvin_rgb", "dvin_vs", "dvin_hs", "dvin_clk", "dvin_de"
788};
789
790static const char * const enc_groups[] = {
791 "enc_0", "enc_1", "enc_2", "enc_3", "enc_4", "enc_5",
792 "enc_6", "enc_7", "enc_8", "enc_9", "enc_10", "enc_11",
793 "enc_12", "enc_13", "enc_14", "enc_15", "enc_16", "enc_17"
794};
795
796static const char * const vga_groups[] = {
797 "vga_vs", "vga_hs"
798};
799
800static const char * const hdmi_groups[] = {
801 "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec"
802};
803
804static const char * const spi_groups[] = {
805 "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
806 "spi_ss0_1", "spi_ss1_1", "spi_sclk_1", "spi_mosi_1",
807 "spi_miso_1", "spi_ss2_1"
808};
809
810static const char * const ethernet_groups[] = {
811 "eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
812 "eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
813 "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"
814};
815
816static const char * const i2c_a_groups[] = {
817 "i2c_sda_a0", "i2c_sck_a0", "i2c_sda_a1", "i2c_sck_a1",
818 "i2c_sda_a2", "i2c_sck_a2"
819};
820
821static const char * const i2c_b_groups[] = {
822 "i2c_sda_b", "i2c_sck_b"
823};
824
825static const char * const sd_c_groups[] = {
826 "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
827 "sd_cmd_c", "sd_clk_c"
828};
829
830static const char * const sdxc_c_groups[] = {
831 "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
832 "sdxc_clk_c"
833};
834
835static const char * const nand_groups[] = {
836 "nand_io", "nand_io_ce0", "nand_io_ce1",
837 "nand_io_rb0", "nand_ale", "nand_cle",
838 "nand_wen_clk", "nand_ren_clk", "nand_dqs",
839 "nand_ce2", "nand_ce3"
840};
841
842static const char * const nor_groups[] = {
843 "nor_d", "nor_q", "nor_c", "nor_cs"
844};
845
846static const char * const sd_b_groups[] = {
847 "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
848 "sd_d3_b", "sd_d2_b"
849};
850
851static const char * const sdxc_b_groups[] = {
852 "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
853};
854
855static const char * const uart_ao_groups[] = {
856 "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
857};
858
859static const char * const remote_groups[] = {
860 "remote_input"
861};
862
863static const char * const i2c_slave_ao_groups[] = {
864 "i2c_slave_sck_ao", "i2c_slave_sda_ao"
865};
866
867static const char * const uart_ao_b_groups[] = {
868 "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1"
869};
870
871static const char * const i2c_mst_ao_groups[] = {
872 "i2c_mst_sck_ao", "i2c_mst_sda_ao"
873};
874
875static struct meson_pmx_func meson8_functions[] = {
876 FUNCTION(gpio),
877 FUNCTION(sd_a),
878 FUNCTION(sdxc_a),
879 FUNCTION(pcm_a),
880 FUNCTION(uart_a),
881 FUNCTION(uart_b),
882 FUNCTION(iso7816),
883 FUNCTION(i2c_d),
884 FUNCTION(xtal),
885 FUNCTION(uart_c),
886 FUNCTION(pcm_b),
887 FUNCTION(i2c_c),
888 FUNCTION(dvin),
889 FUNCTION(enc),
890 FUNCTION(vga),
891 FUNCTION(hdmi),
892 FUNCTION(spi),
893 FUNCTION(ethernet),
894 FUNCTION(i2c_a),
895 FUNCTION(i2c_b),
896 FUNCTION(sd_c),
897 FUNCTION(sdxc_c),
898 FUNCTION(nand),
899 FUNCTION(nor),
900 FUNCTION(sd_b),
901 FUNCTION(sdxc_b),
902 FUNCTION(uart_ao),
903 FUNCTION(remote),
904 FUNCTION(i2c_slave_ao),
905 FUNCTION(uart_ao_b),
906 FUNCTION(i2c_mst_ao),
907};
908
909static struct meson_bank meson8_banks[] = {
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]910 /* name first last pullen pull dir out in */
911 BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
912 BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
913 BANK("DV", PIN(GPIODV_0, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
914 BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
915 BANK("Z", PIN(GPIOZ_0, 0), PIN(GPIOZ_14, 0), 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
916 BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
917 BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]918};
919
920static struct meson_bank meson8_ao_banks[] = {
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100[diff] [blame]921 /* name first last pullen pull dir out in */
922 BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]923};
924
925static struct meson_domain_data meson8_domain_data[] = {
926 {
927 .name = "banks",
928 .banks = meson8_banks,
929 .num_banks = ARRAY_SIZE(meson8_banks),
930 .pin_base = 0,
931 .num_pins = 120,
932 },
933 {
934 .name = "ao-bank",
935 .banks = meson8_ao_banks,
936 .num_banks = ARRAY_SIZE(meson8_ao_banks),
937 .pin_base = 120,
938 .num_pins = 16,
939 },
940};
941
942struct meson_pinctrl_data meson8_pinctrl_data = {
943 .pins = meson8_pins,
944 .groups = meson8_groups,
945 .funcs = meson8_functions,
946 .domain_data = meson8_domain_data,
947 .num_pins = ARRAY_SIZE(meson8_pins),
948 .num_groups = ARRAY_SIZE(meson8_groups),
949 .num_funcs = ARRAY_SIZE(meson8_functions),
950 .num_domains = ARRAY_SIZE(meson8_domain_data),
951};