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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
Tom Duffycd4e8fb2005-06-27 14:36:37 -07003 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
34 */
35
36#ifndef MTHCA_DEV_H
37#define MTHCA_DEV_H
38
39#include <linux/spinlock.h>
40#include <linux/kernel.h>
41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <asm/semaphore.h>
44
45#include "mthca_provider.h"
46#include "mthca_doorbell.h"
47
48#define DRV_NAME "ib_mthca"
49#define PFX DRV_NAME ": "
50#define DRV_VERSION "0.06-pre"
51#define DRV_RELDATE "November 8, 2004"
52
Linus Torvalds1da177e2005-04-16 15:20:36 -070053enum {
54 MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
55 MTHCA_FLAG_SRQ = 1 << 2,
56 MTHCA_FLAG_MSI = 1 << 3,
57 MTHCA_FLAG_MSI_X = 1 << 4,
Michael S. Tsirkine0f5fdc2005-04-16 15:26:30 -070058 MTHCA_FLAG_NO_LAM = 1 << 5,
Roland Dreier68a3c212005-04-16 15:26:34 -070059 MTHCA_FLAG_FMR = 1 << 6,
60 MTHCA_FLAG_MEMFREE = 1 << 7,
61 MTHCA_FLAG_PCIE = 1 << 8
Linus Torvalds1da177e2005-04-16 15:20:36 -070062};
63
64enum {
65 MTHCA_MAX_PORTS = 2
66};
67
68enum {
69 MTHCA_EQ_CONTEXT_SIZE = 0x40,
70 MTHCA_CQ_CONTEXT_SIZE = 0x40,
71 MTHCA_QP_CONTEXT_SIZE = 0x200,
72 MTHCA_RDB_ENTRY_SIZE = 0x20,
73 MTHCA_AV_SIZE = 0x20,
74 MTHCA_MGM_ENTRY_SIZE = 0x40,
75
76 /* Arbel FW gives us these, but we need them for Tavor */
77 MTHCA_MPT_ENTRY_SIZE = 0x40,
78 MTHCA_MTT_SEG_SIZE = 0x40,
79};
80
81enum {
82 MTHCA_EQ_CMD,
83 MTHCA_EQ_ASYNC,
84 MTHCA_EQ_COMP,
85 MTHCA_NUM_EQ
86};
87
Michael S. Tsirkin2a4443a2005-04-16 15:26:25 -070088enum {
89 MTHCA_OPCODE_NOP = 0x00,
90 MTHCA_OPCODE_RDMA_WRITE = 0x08,
91 MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
92 MTHCA_OPCODE_SEND = 0x0a,
93 MTHCA_OPCODE_SEND_IMM = 0x0b,
94 MTHCA_OPCODE_RDMA_READ = 0x10,
95 MTHCA_OPCODE_ATOMIC_CS = 0x11,
96 MTHCA_OPCODE_ATOMIC_FA = 0x12,
97 MTHCA_OPCODE_BIND_MW = 0x18,
98 MTHCA_OPCODE_INVALID = 0xff
99};
100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101struct mthca_cmd {
102 int use_events;
103 struct semaphore hcr_sem;
104 struct semaphore poll_sem;
105 struct semaphore event_sem;
106 int max_cmds;
107 spinlock_t context_lock;
108 int free_head;
109 struct mthca_cmd_context *context;
110 u16 token_mask;
111};
112
113struct mthca_limits {
114 int num_ports;
115 int vl_cap;
116 int mtu_cap;
117 int gid_table_len;
118 int pkey_table_len;
119 int local_ca_ack_delay;
120 int num_uars;
121 int max_sg;
122 int num_qps;
123 int reserved_qps;
124 int num_srqs;
125 int reserved_srqs;
126 int num_eecs;
127 int reserved_eecs;
128 int num_cqs;
129 int reserved_cqs;
130 int num_eqs;
131 int reserved_eqs;
132 int num_mpts;
133 int num_mtt_segs;
Michael S. Tsirkine0f5fdc2005-04-16 15:26:30 -0700134 int fmr_reserved_mtts;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 int reserved_mtts;
136 int reserved_mrws;
137 int reserved_uars;
138 int num_mgms;
139 int num_amgms;
140 int reserved_mcgs;
141 int num_pds;
142 int reserved_pds;
143};
144
145struct mthca_alloc {
146 u32 last;
147 u32 top;
148 u32 max;
149 u32 mask;
150 spinlock_t lock;
151 unsigned long *table;
152};
153
154struct mthca_array {
155 struct {
156 void **page;
157 int used;
158 } *page_list;
159};
160
161struct mthca_uar_table {
162 struct mthca_alloc alloc;
163 u64 uarc_base;
164 int uarc_size;
165};
166
167struct mthca_pd_table {
168 struct mthca_alloc alloc;
169};
170
Michael S. Tsirkin9095e202005-04-16 15:26:26 -0700171struct mthca_buddy {
172 unsigned long **bits;
173 int max_order;
174 spinlock_t lock;
175};
176
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177struct mthca_mr_table {
178 struct mthca_alloc mpt_alloc;
Michael S. Tsirkine0f5fdc2005-04-16 15:26:30 -0700179 struct mthca_buddy mtt_buddy;
180 struct mthca_buddy *fmr_mtt_buddy;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 u64 mtt_base;
Michael S. Tsirkine0f5fdc2005-04-16 15:26:30 -0700182 u64 mpt_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183 struct mthca_icm_table *mtt_table;
184 struct mthca_icm_table *mpt_table;
Michael S. Tsirkine0f5fdc2005-04-16 15:26:30 -0700185 struct {
186 void __iomem *mpt_base;
187 void __iomem *mtt_base;
188 struct mthca_buddy mtt_buddy;
189 } tavor_fmr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190};
191
192struct mthca_eq_table {
193 struct mthca_alloc alloc;
194 void __iomem *clr_int;
195 u32 clr_mask;
196 u32 arm_mask;
197 struct mthca_eq eq[MTHCA_NUM_EQ];
198 u64 icm_virt;
199 struct page *icm_page;
200 dma_addr_t icm_dma;
201 int have_irq;
202 u8 inta_pin;
203};
204
205struct mthca_cq_table {
206 struct mthca_alloc alloc;
207 spinlock_t lock;
208 struct mthca_array cq;
209 struct mthca_icm_table *table;
210};
211
212struct mthca_qp_table {
213 struct mthca_alloc alloc;
214 u32 rdb_base;
215 int rdb_shift;
216 int sqp_start;
217 spinlock_t lock;
218 struct mthca_array qp;
219 struct mthca_icm_table *qp_table;
220 struct mthca_icm_table *eqp_table;
Roland Dreier08aeb142005-04-16 15:26:34 -0700221 struct mthca_icm_table *rdb_table;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222};
223
224struct mthca_av_table {
225 struct pci_pool *pool;
226 int num_ddr_avs;
227 u64 ddr_av_base;
228 void __iomem *av_map;
229 struct mthca_alloc alloc;
230};
231
232struct mthca_mcg_table {
233 struct semaphore sem;
234 struct mthca_alloc alloc;
235 struct mthca_icm_table *table;
236};
237
238struct mthca_dev {
239 struct ib_device ib_dev;
240 struct pci_dev *pdev;
241
242 int hca_type;
243 unsigned long mthca_flags;
244 unsigned long device_cap_flags;
245
246 u32 rev_id;
247
248 /* firmware info */
249 u64 fw_ver;
250 union {
251 struct {
252 u64 fw_start;
253 u64 fw_end;
254 } tavor;
255 struct {
256 u64 clr_int_base;
257 u64 eq_arm_base;
258 u64 eq_set_ci_base;
259 struct mthca_icm *fw_icm;
260 struct mthca_icm *aux_icm;
261 u16 fw_pages;
262 } arbel;
263 } fw;
264
265 u64 ddr_start;
266 u64 ddr_end;
267
268 MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
269 struct semaphore cap_mask_mutex;
270
271 void __iomem *hcr;
272 void __iomem *kar;
273 void __iomem *clr_base;
274 union {
275 struct {
276 void __iomem *ecr_base;
277 } tavor;
278 struct {
279 void __iomem *eq_arm;
280 void __iomem *eq_set_ci_base;
281 } arbel;
282 } eq_regs;
283
284 struct mthca_cmd cmd;
285 struct mthca_limits limits;
286
287 struct mthca_uar_table uar_table;
288 struct mthca_pd_table pd_table;
289 struct mthca_mr_table mr_table;
290 struct mthca_eq_table eq_table;
291 struct mthca_cq_table cq_table;
292 struct mthca_qp_table qp_table;
293 struct mthca_av_table av_table;
294 struct mthca_mcg_table mcg_table;
295
296 struct mthca_uar driver_uar;
297 struct mthca_db_table *db_tab;
298 struct mthca_pd driver_pd;
299 struct mthca_mr driver_mr;
300
301 struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
302 struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
303 spinlock_t sm_lock;
304};
305
306#define mthca_dbg(mdev, format, arg...) \
307 dev_dbg(&mdev->pdev->dev, format, ## arg)
308#define mthca_err(mdev, format, arg...) \
309 dev_err(&mdev->pdev->dev, format, ## arg)
310#define mthca_info(mdev, format, arg...) \
311 dev_info(&mdev->pdev->dev, format, ## arg)
312#define mthca_warn(mdev, format, arg...) \
313 dev_warn(&mdev->pdev->dev, format, ## arg)
314
315extern void __buggy_use_of_MTHCA_GET(void);
316extern void __buggy_use_of_MTHCA_PUT(void);
317
318#define MTHCA_GET(dest, source, offset) \
319 do { \
320 void *__p = (char *) (source) + (offset); \
321 switch (sizeof (dest)) { \
322 case 1: (dest) = *(u8 *) __p; break; \
323 case 2: (dest) = be16_to_cpup(__p); break; \
324 case 4: (dest) = be32_to_cpup(__p); break; \
325 case 8: (dest) = be64_to_cpup(__p); break; \
326 default: __buggy_use_of_MTHCA_GET(); \
327 } \
328 } while (0)
329
330#define MTHCA_PUT(dest, source, offset) \
331 do { \
332 __typeof__(source) *__p = \
333 (__typeof__(source) *) ((char *) (dest) + (offset)); \
334 switch (sizeof(source)) { \
335 case 1: *__p = (source); break; \
336 case 2: *__p = cpu_to_be16(source); break; \
337 case 4: *__p = cpu_to_be32(source); break; \
338 case 8: *__p = cpu_to_be64(source); break; \
339 default: __buggy_use_of_MTHCA_PUT(); \
340 } \
341 } while (0)
342
343int mthca_reset(struct mthca_dev *mdev);
344
345u32 mthca_alloc(struct mthca_alloc *alloc);
346void mthca_free(struct mthca_alloc *alloc, u32 obj);
347int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
348 u32 reserved);
349void mthca_alloc_cleanup(struct mthca_alloc *alloc);
350void *mthca_array_get(struct mthca_array *array, int index);
351int mthca_array_set(struct mthca_array *array, int index, void *value);
352void mthca_array_clear(struct mthca_array *array, int index);
353int mthca_array_init(struct mthca_array *array, int nent);
354void mthca_array_cleanup(struct mthca_array *array, int nent);
355
356int mthca_init_uar_table(struct mthca_dev *dev);
357int mthca_init_pd_table(struct mthca_dev *dev);
358int mthca_init_mr_table(struct mthca_dev *dev);
359int mthca_init_eq_table(struct mthca_dev *dev);
360int mthca_init_cq_table(struct mthca_dev *dev);
361int mthca_init_qp_table(struct mthca_dev *dev);
362int mthca_init_av_table(struct mthca_dev *dev);
363int mthca_init_mcg_table(struct mthca_dev *dev);
364
365void mthca_cleanup_uar_table(struct mthca_dev *dev);
366void mthca_cleanup_pd_table(struct mthca_dev *dev);
367void mthca_cleanup_mr_table(struct mthca_dev *dev);
368void mthca_cleanup_eq_table(struct mthca_dev *dev);
369void mthca_cleanup_cq_table(struct mthca_dev *dev);
370void mthca_cleanup_qp_table(struct mthca_dev *dev);
371void mthca_cleanup_av_table(struct mthca_dev *dev);
372void mthca_cleanup_mcg_table(struct mthca_dev *dev);
373
374int mthca_register_device(struct mthca_dev *dev);
375void mthca_unregister_device(struct mthca_dev *dev);
376
377int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
378void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);
379
380int mthca_pd_alloc(struct mthca_dev *dev, struct mthca_pd *pd);
381void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);
382
Roland Dreierd56d6f92005-06-27 14:36:43 -0700383struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);
384void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);
385int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
386 int start_index, u64 *buffer_list, int list_len);
387int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
388 u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
390 u32 access, struct mthca_mr *mr);
391int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
392 u64 *buffer_list, int buffer_size_shift,
393 int list_len, u64 iova, u64 total_size,
394 u32 access, struct mthca_mr *mr);
Michael S. Tsirkine0f5fdc2005-04-16 15:26:30 -0700395void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);
396
397int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
398 u32 access, struct mthca_fmr *fmr);
399int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
400 int list_len, u64 iova);
401void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
402int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
403 int list_len, u64 iova);
404void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
405int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406
407int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
408void mthca_unmap_eq_icm(struct mthca_dev *dev);
409
410int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
411 struct ib_wc *entry);
412int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
413int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
414int mthca_init_cq(struct mthca_dev *dev, int nent,
415 struct mthca_cq *cq);
416void mthca_free_cq(struct mthca_dev *dev,
417 struct mthca_cq *cq);
418void mthca_cq_event(struct mthca_dev *dev, u32 cqn);
419void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn);
420
421void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
422 enum ib_event_type event_type);
423int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
424int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
425 struct ib_send_wr **bad_wr);
426int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
427 struct ib_recv_wr **bad_wr);
428int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
429 struct ib_send_wr **bad_wr);
430int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
431 struct ib_recv_wr **bad_wr);
432int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
433 int index, int *dbd, u32 *new_wqe);
434int mthca_alloc_qp(struct mthca_dev *dev,
435 struct mthca_pd *pd,
436 struct mthca_cq *send_cq,
437 struct mthca_cq *recv_cq,
438 enum ib_qp_type type,
439 enum ib_sig_type send_policy,
440 struct mthca_qp *qp);
441int mthca_alloc_sqp(struct mthca_dev *dev,
442 struct mthca_pd *pd,
443 struct mthca_cq *send_cq,
444 struct mthca_cq *recv_cq,
445 enum ib_sig_type send_policy,
446 int qpn,
447 int port,
448 struct mthca_sqp *sqp);
449void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
450int mthca_create_ah(struct mthca_dev *dev,
451 struct mthca_pd *pd,
452 struct ib_ah_attr *ah_attr,
453 struct mthca_ah *ah);
454int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
455int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
456 struct ib_ud_header *header);
457
458int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
459int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
460
461int mthca_process_mad(struct ib_device *ibdev,
462 int mad_flags,
463 u8 port_num,
464 struct ib_wc *in_wc,
465 struct ib_grh *in_grh,
466 struct ib_mad *in_mad,
467 struct ib_mad *out_mad);
468int mthca_create_agents(struct mthca_dev *dev);
469void mthca_free_agents(struct mthca_dev *dev);
470
471static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
472{
473 return container_of(ibdev, struct mthca_dev, ib_dev);
474}
475
Roland Dreierd10ddbf2005-04-16 15:26:32 -0700476static inline int mthca_is_memfree(struct mthca_dev *dev)
477{
Roland Dreier68a3c212005-04-16 15:26:34 -0700478 return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
Roland Dreierd10ddbf2005-04-16 15:26:32 -0700479}
480
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481#endif /* MTHCA_DEV_H */